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AD9833BRM
+2.5 V to +5.5 V, 25 MHz Low Power CMOS Complete DDS
+2.5 V to +5.5 V, 25 MHz Low PowerCMOS Complete DDS
FEATURES
+2.3 V to +5.5 V Power Supply
25 MHz Speed
Tiny 10-Pin μμμμμSOIC Package
Serial Loading
Sinusoidal/Triangular DAC Output
Power-Down Option
Narrowband SFDR > 72 dB
20 mW Power Consumption at 3 V
APPLICATIONS
Digital Modulation
Portable Equipment
Test Equipment
DDS Tuning
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThis low power DDS device is a numerically controlled
oscillator employing a phase accumulator, a SIN ROM
and a 10-bit D/A converter integrated on a single
CMOS chip. Clock rates up to 25 MHz are supported
with a power supply from +2.3 V to +5.5 V.
Capability for phase modulation and frequency modula-
tion is provided. Frequency accuracy can be controlled to
one part in 0.25 billion. Modulation is effected by loading
registers through the serial interface.
The AD9833 offers a variety of output waveforms from
the VOUT pin. The SIN ROM can be bypassed so that a
linear up/down ramp is output from the DAC. If the SIN
ROM is not by-passed, a sinusoidal output is available.
Also, if a clock output is required, the MSB of the DAC
data can be output.
The digital section is internally operated at +2.5 V, irre-
spective of the value of VDD, by an on board regulator
which steps down VDD to +2.5 V, when VDD exceeds
+2.5 V.
The AD9833 has a power-down function (SLEEP). This
allows sections of the device which are not being used to
be powered down, thus minimising the current consump-
tion of the part e.g the DAC can be powered down when a
clock output is being generated.
The AD9833 is available in a 10-pin μSOIC package.
PRELIMINARY TECHNICAL DATAREV PrG 02/02
AD9833
PRELIMINARY TECHNICAL DATANOTESOperating temperature range is as follows: B Version: –40°C to +85°C; typical specifications are at 25�CGuaranteed by Design.Measured with the digital inputs static and equal to 0 V or DVDD.
Specifications subject to change without notice. There is 95% test coverage of the digital circuitry.
SPECIFICATIONS1(VDD = +2.3 V to +5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX; RSET = 6.8kΩΩΩΩΩ for
VOUT unless otherwise noted)
PRELIMINARY TECHNICAL DATA
TIMING CHARACTERISTICS1(VDD = +2.3 V to +5.5 V; AGND = DGND = 0 V, unless otherwise noted) Guaranteed by design, not production tested.
Figure 2.Master Clock
Figure 3.Serial Timing
Figure 1.Test Circuit With which Specifications are tested.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9833 features proprietary ESD protection circuitry, permanent damage may
AD9833
PRELIMINARY TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
AGND to DGND. . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
CAP/2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.75 V
Digital I/O Voltage to DGND .–0.3 V to VDD + 0.3 V
Analog I/O Voltage to AGND .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . .–65°C to +150°C
PIN CONFIGURATIONMaximum Junction Temperature . . . . . . . . . . . . . .150°C
μSOIC Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . .206°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . .44°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . .300°C
IR Reflow, Peak Temperature . . . . . . . . . . . . . . .220°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ORDERING GUIDE
PIN DESCRIPTION
ANALOG SIGNAL AND REFERENCECOMPA DAC Bias Pin. This pin is used for de-coupling the DAC bias voltage.VOUTVoltage Output. The analog and digital output from the AD9833 is available at this pin. An
external load resistor is not required as the device has a 200W resistor on board.
DIGITAL INTERFACE AND CONTROL
PRELIMINARY TECHNICAL DATA
Typical Performance CharacteristicsTPC 1. Typical Current Consumption
vs. MCLK Frequency
TPC 4. Wide Band SFDR vs. fOUT/fMCLK
for Various MCLK Frequencies
TPC 7. Wake-Up Time vs.
Temperature
TPC 2. Narrow Band SFDR vs. MCLK
Frequency
TPC 5. SNR vs. MCLK Frequency
TPC 3. Wide Band SFDR vs. MCLK
Frequency
TPC 6. SNR vs. fOUT/fMCLK for
Various MCLK Frequencies
AD9833
PRELIMINARY TECHNICAL DATA
Typical Performance CharacteristicsTPC 9. fMCLK = 10 MHz; fOUT = 2.4 kHz;
Frequency Word = 000FBA9
TPC 12. fMCLK = 25 MHz; fOUT = 6 kHz;
Frequency Word = 000FBA9
TPC 15. fMCLK = 25 MHz;
fOUT = 2.4 MHz;
Frequency Word = 189374D
TPC 10. fMCLK = 10 MHz; fOUT = 1.43 kHz
= fMCLK/7 ;
Frequency Word = 2492492
TPC 13. fMCLK = 25 MHz; fOUT = 60 kHz;
Frequency Word = 009D495
TPC 16. fMCLK = 25 MHz;
fOUT = 3.857 MHz = fMCLK/7 ;
Frequency Word = 277EE4F
TPC 11. fMCLK = 10 MHz; fOUT = 3.33 kHz
= fMCLK/3 ;
Frequency Word = 5555555
TPC 14. fMCLK = 25 MHz; fOUT = 600 kHz;
Frequency Word = 0624DD3
TPC 17. fMCLK = 25 MHz;
fOUT = 8.333 MHz = fMCLK/3 ;
Frequency Word = 555475C
PRELIMINARY TECHNICAL DATA
TERMINOLOGY
Integral NonlinearityThis is the maximum deviation of any code from a
straight line passing through the endpoints of the transfer
function. The endpoints of the transfer function are zero
scale, a point 0.5 LSB below the first code transition
(000...00 to 000...01) and full scale, a point 0.5 LSB
above the last code transition (111...10 to 111...11).
The error is expressed in LSBs.
Differential NonlinearityThis is the difference between the measured and ideal 1
LSB change between two adjacent codes in the DAC. A
specified differential nonlinearity of ±1 LSB maximium ensures
monotonicity.
Output ComplianceThe output compliance refers to the maximum voltage
that can be generated at the output of the DAC to meet
the specifications. When voltages greater than that speci-
fied for the output compliance are generated, the AD9833
may not meet the specifications listed in the data sheet.
Spurious Free Dynamic RangeAlong with the frequency of interest, harmonics of the
fundamental frequency and images of the these frequencies
are present at the output of a DDS device. The spurious
free dynamic range (SFDR) refers to the largest spur or
harmonic which is present in the band of interest. The
wide band SFDR gives the magnitude of the largest har-
monic or spur relative to the magnitude of the fundamental
frequency in the 0 to Nyquist bandwidth. The narrow band
SFDR gives the attenuation of the largest spur or harmonic
in a bandwidth of ±200 kHz about the fundamental fre-
quency.
Total Harmonic DistortionTotal Harmonic Distortion (THD) is the ratio of the rms
sum of harmonics to the rms value of the fundameltal. For
the AD9834, THD is defined as:
THD = 20 log√(V22 + V32 + V42 + V52 + V62)/V1
where V1 is the rms amplitude of the fundamental and V2,
V3, V4, V5 and V6 are the rms amplitudes of the second
through thre sixth harmonic.
Signal-to-Noise Ratio (SNR)S/N is the ratio of the rms value of the measured output
signal to the rms sum of all other spectral components
below the Nyquist frequency, excluding the first six har-
monics and dc. The value for SNR is expressed in
decibels.
Clock FeedthroughThere will be feedthrough from the MCLK input to the
analog output. Clock feedthrough refers to the magnitude
of the MCLK signal relative to the fundamental frequency
in the AD9834’s output spectrum.
THEORY OF OPERATIONSine waves are typically thought of in terms of their
magnitude form a(t) = sin (ωt). However, these are
nonlinear and not easy to generate except through piece
wise construction. On the other hand, the angular
information is linear in nature. That is, the phase angle
rotates through a fixed angle for each unit of time. The
angular rate depends on the frequency of the signal by the
traditional rate of ω = 2πf.
Figure 4.Sine Wave
Knowing that the phase of a sine wave is linear and given
a reference interval (clock period), the phase rotation for
that period can be determined.
ΔPhase = ωδt
Solving for ω
ω = ΔPhase/δt = 2πf
Solving for f and substituting the reference clock
frequency for the reference period (1/fMCLK = δt)
f = ΔPhase x fMCLK/2π
The AD9833 builds the output based on this simple
equation. A simple DDS chip can implement this
equation with three major subcircuits:
Numerical Controlled Oscillator + Phase Modulator
SIN ROM
Digital- to- Analog Convertor.
Each of these sub-circuits are discussed in the following
section.
AD9833
PRELIMINARY TECHNICAL DATA
CIRCUIT DESCRIPTIONThe AD9833 is a fully integrated Direct Digital Synthesis
(DDS) chip. The chip requires one reference clock, one
low precision resistor and decoupling capacitors to pro-
vide digitally created sine waves up to 12.5 MHz. In
addition to the generation of this RF signal, the chip is
fully capable of a broad range of simple and complex
modulation schemes. These modulation schemes are fully
implemented in the digital domain allowing accurate and
simple realization of complex modulation algorithms us-
ing DSP techniques.
The internal circuitry of the AD9833 consists of the fol-
lowing main sections: a Numerical Controlled Oscillator
(NCO), Frequency and Phase Modulators, SIN ROM, a
Digital-to-Analog Converter, and a Regulator.
Numerical Controlled Oscillator + Phase ModulatorThis consists of two frequency select registers, a phase
accumulator, two phase offset registers and a phase offset
adder. The main component of the NCO is a 28-bit phase
accumulator which assembles the phase component of the
output signal. Continuous time signals have a phase range
of 0 to 2�. Outside this range of numbers, the sinusoid
functions repeat themselves in a periodic manner. The
digital implementation is no different. The accumulator
simply scales the range of phase numbers into a multibit
digital word. The phase accumulator in the AD9833 is
implemented with 28 bits. Therefore, in the AD9833, 2�
= 228. Likewise, the ΔPhase term is scaled into this range
of numbers 0 < ΔPhase < 228 – 1. Making these substitu-
tions into the equation above
f = ΔPhase x fMCLK/228
where 0 < ΔPhase < 228 - 1.
The input to the phase accumulator (i.e., the phase step)
can be selected either from the FREQ0 Register or
FREQ1 Register and this is controlled by the FSELECT
bit. NCOs inherently generate continuous phase signals,
thus avoiding any output discontinuity when switching
between frequencies.
Following the NCO, a phase offset can be added to
perform phase modulation using the 12-bit Phase
Registers. The contents of one of these phase registers is
added to the most significant bits of the NCO. The
AD9833 has two Phase registers, the resolution of these
registers being 2π/4096.
SIN ROMTo make the output from the NCO useful, it must be
converted from phase information into a sinusoidal value.
Since phase information maps directly into amplitude, the
SIN ROM uses the digital phase information as an ad-
dress to a look-up table, and converts the phase
information into amplitude. Although the NCO contains a
28-bit phase accumulator, the output of the NCO is trun-
cated to 12 bits. Using the full resolution of the phase
accumulator is impractical and unnecessary as this would
require a look-up table of 228 entries. It is necessary only
to have sufficient phase resolution such that the errors due
phase resolution more than the 10-bit DAC.
The SIN ROM is enabled using the MODE bit (D1) in
the control register. This is explained further in Table 11.
Digital-to-Analog ConverterThe AD9833 includes a high impedance current source
10-bit DAC. The DAC receives the digital words from
the SIN ROM and converts them into the corresponding
analog voltages.
The DAC is configured for single-ended operation. An
external load resistor is not required as the device has a
200 Ω resistor on board. The DAC generates an output
voltage of typically 0.6 Vpp.
RegulatorVDD provides the power supply required for the analog
section and the digital section of the AD9833. This supply
can have a value of +2.3V to +5.5V
The internal digital section of the AD9833 is operated at
2.5 V. An on-board regulator steps down the voltage ap-
plied at VDD to 2.5 V. When the applied voltage at the
VDD pin of the AD9833 is equal to or less than 2.7 V,
the pins CAP/2.5V and VDD should be tied together, thus
by-passing the on-board regulator.
PRELIMINARY TECHNICAL DATA
FUNCTIONAL DESCRIPTION
Serial InterfaceThe AD9833 has a standard 3-wire serial interface, which
is compatible with SPI, QSPI, MICROWIRE and DSP
interface standards.
Data is loaded into the device as a 16-bit word under the
control of a serial clock input, SCLK. The timing dia-
gram for this operation is given in Figure 3.
The FSYNC input is a level triggered input that acts as a
frame synchronisation and chip enable. Data can only be
transferred into the device when FSYNC is low. To start
the serial data transfer, FSYNC should be taken low, ob-
serving the minimum FSYNC to SCLK falling edge setup
time, t7. After FSYNC goes low, serial data will be shifted
into the device's input shift register on the falling edges of
SCLK for 16 clock pulses. FSYNC may be taken high
after the sixteenth falling edge of SCLK, observing the
minimum SCLK falling edge to FSYNC rising edge time,
t8. Alternatively, FSYNC can be kept low for a multiple of
16 SCLK pulses, and then brought high at the end of the
data transfer. In this way, a continuous stream of 16 bit
words can be loaded while FSYNC is held low, FSYNC
only going high after the 16th SCLK falling edge of the
last word loaded.
The SCLK can be continuous or, alternatively, the SCLK
can idle high or low between write operations.
Powering up the AD9833The flow chart in Figure 6 shows the operating routine for
the AD9833. When the AD9833 is powered up, the part
should be reset. This will reset appropriate internal regis-
ters to zero to provide an analog output of midscale. To
avoid spurious DAC outputs while the AD9833 is being
initialized, the RESET bit should be set to 1 until the part
is ready to begin generating an output. RESET does not
reset the phase, frequency or control registers. These reg-
isters will contain invalid data and, therefore, should be set
to a known value by the user. The RESET bit should then
be set to 0 to begin generating an output. A signal will
appear at the DAC output 7 MCLK cycles after RESET is
set to 0.
LatencyAssociated with each asynchronous write operation in the
AD9833 is a latency. If a selected frequency/phase register
is loaded with a new word there is a delay of 7 to 8 MCLK
cycles before the analog output will change. (There is an
uncertainty of one MCLK cycle as it depends on the posi-
tion of the MCLK rising edge when the data is loaded into
the destination register.)
The Control RegisterThe AD9833 contains a 16-bit control register which sets
up the AD9833 as the user wishes to operate it. All control
bits, except MODE, are sampled on the internal negative
edge of MCLK.
Table 2, on the following page, describes the individual
bits of the control register. The different functions and the
various output options from the AD9833 are described in
more detail in the section following Table 2.
To inform the AD9833 that you wish to alter the contents
of the Control register, D15 and D14 must be set to '0' as
shown below.
Table 1. Control RegisterFigure 5. Function of Control Bits
