AD9832BRU Fast Delivery |IC PHOENIX CO.,LIMITED

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AD9832BRU
CMOS Complete DDS
REV.A
CMOS
Complete DDS
FUNCTIONAL BLOCK DIAGRAM
IOUT
COMP
REFINFS ADJUSTREFOUTAGNDAVDDDGNDDVDD
MCLK
PSEL0PSEL1FSELECT
FSYNCSCLKSDATA
FEATURES
3 V/5 V Power Supply
25 MHz Speed
On-Chip SINE Look-Up Table
On-Chip 10-Bit DAC
Serial Loading
Power-Down Option
45 mW Power Consumption
16-Lead TSSOP
APPLICATIONS
DDS Tuning
Digital Demodulation
GENERAL DESCRIPTION
The AD9832 is a numerically controlled oscillator employing
a phase accumulator, a sine look-up table and a 10-bit D/A
converter integrated on a single CMOS chip. Modulation
capabilities are provided for phase modulation and frequency
modulation.
Clock rates up to 25 MHz are supported. Frequency accuracy
can be controlled to one part in 4 billion. Modulation is effected
by loading registers through the serial interface.
A power-down bit allows the user to power down the AD9832
when it is not in use, the power consumption being reduced tomW (5 V) or 3mW (3 V). The part is available in a 16-lead
TSSOP package.
AD9832–SPECIFICATIONS1(VDD = +3.3 V 6 10%; +5 V 6 10%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN =
REFOUT; RSET = 3.9 kV; RLOAD = 300 V for IOUT unless otherwise noted)
NOTESOperating temperature range is as follows: B Version, –40°C to +85°C.100% production tested.fMCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, fOUT = 2.11 MHz.See Figure 11. To reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested.Measured with the digital inputs static and equal to 0 V or DVDD.
The AD9832 is tested with a capacitive load of 50 pF. The part can be operated with higher capacitive loads, but the magnitude of the analog output will be attenuated.
For example, a 5 MHz output signal will be attenuated by 3 dB when the load capacitance equals 85 pF.
Specifications subject to change without notice.
RSET
TIMING CHARACTERISTICS(VDD = +3.3 V 6 10%; +5 V 6 10%; AGND = DGND = 0 V, unless otherwise noted)
*See Pin Function Descriptions.
Guaranteed by design but not production tested.
MCLK
Figure 2.Master Clock
SCLK
FSYNC
SDATAt8
Figure 3.Serial Timing
Figure 4.Control Timing
AD9832
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AGND to DGND. . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
TSSOP qJA Thermal Impedance . . . . . . . . . . . . . . . 158°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 4500 V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
*RU = Thin Shrink Small Outline Package (TSSOP).
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
ANALOG SIGNAL AND REFERENCEFS ADJUSTFull-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines
the magnitude of the full-scale DAC current. The relationship between RSET and the full-scale current is
as follows:
IOUTFULL-SCALE = 12.5 · VREFIN/RSET
VREFIN = 1.21 V nominal, RSET = 3.9 kW typicalREFINVoltage Reference Input. The AD9832 can be used with either the onboard reference, which is available
from pin REFOUT, or an external reference. The reference to be used is connected to the REFIN pin.
The AD9832 accepts a reference of 1.21 V nominal.REFOUTVoltage Reference Output. The AD9832 has an onboard reference of value 1.21 V nominal. The refer-
ence is made available on the REFOUT pin. This reference is used as the reference to the DAC by con-
necting REFOUT to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.IOUTCurrent Output. This is a high impedance current source. A load resistor should be connected between
IOUT and AGND.COMPCompensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling
ceramic capacitor should be connected between COMP and AVDD.
POWER SUPPLYDVDDPositive Power Supply for the Digital Section. A 0.1 mF decoupling capacitor should be connected be-
tween DVDD and DGND. DVDD can have a value of +5 V – 10% or +3.3 V – 10%.DGNDDigital Ground.AGNDAnalog Ground.AVDDPositive Power Supply for the Analog Section. A 0.1 mF decoupling capacitor should be connected be-
tween AVDD and AGND. AVDD can have a value of +5 V – 10% or +3.3 V – 10%.
DIGITAL INTERFACE AND CONTROL
AD9832
MCLK FREQUENCY – MHz
TOTAL CURRENT – mA510251520
Figure 5.Typical Current Consump-
tion vs. MCLK Frequency
fOUT/fMCLK
SFDR (
Hz) – dB
–55
Figure 8.Wide Band SFDR vs. fOUT/
fMCLK for Various MCLK Frequencies
TEMPERATURE – °C
WAKE-UP TIME – ms
2.5
Figure 11.Wake-Up Time vs.
Temperature
–Typical Performance Characteristics
MCLK FREQUENCY – MHz
SFDR (
50kHz) – dB
–70
Figure 6.Narrow Band SFDR vs.
MCLK Frequency
MCLK FREQUENCY – MHz
SNR – dB10152520
Figure 9.SNR vs. MCLK Frequency
VBW 1kHz
10dB/DIV
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
–30
Figure 12.fMCLK = 25 MHz, fOUT = 1.1MHz,
Frequency Word = B439581
MCLK FREQUENCY – MHz
SFDR (
Hz) – dB
–60
Figure 7.Wide Band SFDR vs. MCLK
Frequency
fOUT/fMCLK
SNR – dB00.10.40.20.3
Figure 10.SNR vs. fOUT/fMCLK for Vari-
ous MCLK Frequencies
Figure 13.fMCLK = 25 MHz, fOUT = 2.1MHz,
Frequency Word = 15810625
VBW 1kHz
10dB/DIV
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
–30
Figure 14.fMCLK = 25 MHz, fOUT = 3.1MHz,
Frequency Word = 1FBE76C9
VBW 1kHz
10dB/DIV
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
–30
Figure 17.fMCLK = 25 MHz, fOUT = 6.1MHz,
Frequency Word = 3E76C8B4
VBW 1kHz
10dB/DIV
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
–30
Figure 20.fMCLK = 25 MHz, fOUT = 9.1MHz,
Frequency Word = 5D2F1AA0
VBW 1kHz
10dB/DIV
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
–30
Figure 15.fMCLK = 25 MHz, fOUT = 4.1MHz,
Frequency Word = 29FBE76D
VBW 1kHz
10dB/DIV
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
–30
Figure 18.fMCLK = 25 MHz, fOUT = 7.1MHz,
Frequency Word = 48B43958
Figure 16.fMCLK = 25 MHz, fOUT = 5.1MHz,
Frequency Word = 34395810
Figure 19.fMCLK = 25 MHz, fOUT = 8.1MHz,
Frequency Word = 52F1A9FC
AD9832
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end-
points of the transfer function are zero scale, a point 0.5LSB be-
low the first code transition (000...00 to 000...01) and full
scale, a point 0.5 LSB above the last code transition (111...10
to 111...11). The error is expressed in LSBs.
Differential Nonlinearity
This is the difference between the measured and ideal 1 LSB
change between two adjacent codes in the DAC.
Signal to (Noise + Distortion)
Signal to (Noise + Distortion) is measured signal to noise at the
output of the DAC. The signal is the rms magnitude of the
fundamental. Noise is the rms sum of all the nonfundamental
signals up to half the sampling frequency (fMCLK/2) but exclud-
ing the dc component. Signal to (Noise + Distortion) is depen-
dent on the number of quantization levels used in the digitization
process; the more levels, the smaller the quantization noise. The
theoretical Signal to (Noise + Distortion) ratio for a sine wave
input is given by
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
where N is the number of bits. Thus, for an ideal 10-bit con-
verter, Signal to (Noise + Distortion) = 61.96 dB.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the rms
sum of harmonics to the rms value of the fundamental. For
the AD9832, THD is defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic.
Output Compliance
The output compliance refers to the maximum voltage that can
be generated at the output of the DAC to meet the specifica-
tions. When voltages greater than those specified for the output
compliance are generated, the AD9832 may not meet the speci-
fications listed in the data sheet.
Spurious Free Dynamic Range
Along with the frequency of interest, harmonics of the fundamental
frequency and images of the MCLK frequency are present at the
output of a DDS device. The spurious free dynamic range (SFDR)
refers to the largest spur or harmonic present in the band of
interest. The wide band SFDR gives the magnitude of the larg-
est harmonic or spur relative to the magnitude of the fundamental
frequency in the bandwidth –2 MHz about the fundamental fre-
quency. The narrow band SFDR gives the attenuation of the
largest spur or harmonic in a bandwidth of –50kHz about the
fundamental frequency.
Clock Feedthrough
There will be feedthrough from the MCLK input to the analog
Table I.Control Registers
Table II.Addressing the Registers
Table III.32-Bit Frequency Word
Table IV.12-Bit Frequency Word

Partno	Mfg	Dc	Qty	Available	Descript
AD9832BRU	AD	N/a	3	avai	CMOS Complete DDS