AD9831AST Fast Delivery |IC PHOENIX CO.,LIMITED

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AD9831AST
CMOS Complete DDS
REV.ACMOS
Complete DDS
FEATURES
3 V/5 V Power Supply
25 MHz Speed
On-Chip SINE Look-Up Table
On-Chip 10-Bit DAC
Parallel Loading
Powerdown Option
72 dB SFDR
125 mW (5 V) Power Consumption
40 mW (3 V) Power Consumption
48-Pin TQFP
APPLICATIONS
DDS Tuning
Digital Demodulation
GENERAL DESCRIPTION
This DDS device is a numerically controlled oscillator employ-
ing a phase accumulator, a sine look-up table and a 10-bit D/A
converter integrated on a single CMOS chip. Modulation
capabilities are provided for phase modulation and frequency
modulation.
Clock rates up to 25 MHz are supported. Frequency accuracy
can be controlled to one part in 4 billion. Modulation is effected
by loading registers through the parallel microprocessor
MCLK
FSELECT
D15WRA0A1A2PSEL0PSEL1
AD9831–SPECIFICATIONS1
NOTESOperating temperature range is as follows: A Version: –40°C to +85°C.100% production tested.fMCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, fOUT = 2.11 MHz.See Figure 11. To reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested.Measured with the digital inputs static and equal to 0 V or DVDD.The Low Power Sleep Mode current is typically 2 mA when a 1 MΩ resistor is not tied between REFOUT and AGND.
The AD9831 is tested with a capacitive load of 50 pF. The part can be operated with higher capacitive loads, but the magnitude of the analog output will be attenu-
ated. For example, a 5 MHz output signal will be attenuated by 3 dB when the load capacitance equals 85 pF.
Specifications subject to change without notice.
(VDD = +3.3 V 6 10%; +5 V 6 10%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN =
REFOUT; RSET = 3.9 kV; RLOAD = 300 V for IOUT unless otherwise noted)
RSET
*See Pin Description section.
Guaranteed by design but not production tested.
MCLK
Figure 2.Clock Synchronization Timing
A0, A1, A2
DATA
t7
Figure 3.Parallel Timing
MCLK
FSELECT
PSEL0, PSEL1
RESET
t9A
Figure 4.Control Timing
AD9831
ORDERING GUIDE
*ST = Thin Quad Flatpack (TQFP).
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
AGND to DGND. . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . .–0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . .–0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . .+150°C
TQFP θJA Thermal Impedance . . . . . . . . . . . . . . . . .75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 4500 V
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PIN CONFIGURATIONAVDDFS ADJUSTIOUTNCAGNDNCCOMPAVDDNCAVDDREFIN
AGND
RESET
DB0
DB1
DGND
DB2
DB3
DB4
DVDD
AGND
REFOUT
SLEEP
DVDD
DVDD
DGND
MCLK
DVDD
FSELECT
PSEL0
PSEL1
NC = NO CONNECT
DB9
DB11
DGND
DB15DB14DB13DB12
DB10
DB8DB7DB6DB5
PIN DESCRIPTION
POWER SUPPLY
AVDDPositive power supply for the analog section. A 0.1 μF decoupling capacitor should be connected between AVDD
and AGND. AVDD can have a value of +5 V ± 10% or +3.3 V ± 10%.
AGNDAnalog Ground.
DVDDPositive power supply for the digital section. A 0.1 μF decoupling capacitor should be connected between DVDD
and DGND. DVDD can have a value of +5 V ± 10% or +3.3 V ± 10%.
DGNDDigital Ground.
ANALOG SIGNAL AND REFERENCE
IOUTCurrent Output. This is a high impedance current source. A load resistor should be connected between IOUT
and AGND.
FS ADJUSTFull-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines the
magnitude of the full-scale DAC current. The relationship between RSET and the full-scale current is as follows:
IOUTFULL-SCALE = 12.5 × VREFIN/RSET
VREFIN = 1.21 V nominal, RSET = 3.9 kΩ typical
REFINVoltage Reference Input. The AD9831 can be used with either the on-board reference, which is available from pin
REFOUT, or an external reference. The reference to be used is connected to the REFIN pin. The AD9831
accepts a reference of 1.21 V nominal.
REFOUTVoltage Reference Output. The AD9831 has an on-board reference of value 1.21 V nominal. The reference is
made available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUT
to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.
COMPCompensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic
capacitor should be connected between COMP and AVDD.
DIGITAL INTERFACE AND CONTROL
AD9831
±2 MHz about the fundamental frequency. The narrow band
SFDR gives the attenuation of the largest spur or harmonic in a
bandwidth of ±50 kHz about the fundamental frequency.
Clock Feedthrough
There will be feedthrough from the MCLK input to the analog
output. Clock feedthrough refers to the magnitude of the
MCLK signal relative to the fundamental frequency in the
AD9831’s output spectrum.
Table I.Control Registers
Table II.Addressing the Control Registers
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale, a point 0.5
LSB below the first code transition (000...00 to 000...01)
and full scale, a point 0.5 LSB above the last code transition
(111...10 to 111...11). The error is expressed in LSBs.
Differential Nonlinearity
This is the difference between the measured and ideal 1 LSB
change between two adjacent codes in the DAC.
Signal to (Noise + Distortion)
Signal to (Noise + Distortion) is measured signal to noise at the
output of the DAC. The signal is the rms magnitude of the
fundamental. Noise is the rms sum of all the nonfundamental
signals up to half the sampling frequency (fMCLK/2) but exclud-
ing the dc component. Signal to (Noise + Distortion) is
dependent on the number of quantization levels used in the
digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical Signal to (Noise + Distortion) ratio
for a sine wave input is given by
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
where N is the number of bits. Thus, for an ideal 10-bit con-
verter, Signal to (Noise + Distortion) = 61.96 dB.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the rms sum
of harmonics to the rms value of the fundamental. For the
AD9831, THD is defined as
THD=20log
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic.
Output Compliance
The output compliance refers to the maximum voltage which
can be generated at the output of the DAC to meet the specifi-
cations. When voltages greater than that specified for the
output compliance are generated, the AD9831 may not meet
the specifications listed in the data sheet.
Spurious Free Dynamic Range
Along with the frequency of interest, harmonics of the funda-
mental frequency and images of the MCLK frequency are
present at the output of a DDS device. The spurious free dy-
namic range (SFDR) refers to the largest spur or harmonic
which is present in the band of interest. The wide band SFDR
gives the magnitude of the largest harmonic or spur relative to
the magnitude of the fundamental frequency in the bandwidth
Table III.Frequency Register Bits
MCLK FREQUENCY – MHz
TOTAL CURRENT – mA510152025
Figure 5.Typical Current Consumption vs. MCLK
Frequency
MCLK FREQUENCY – MHz
SFDR (
50kHz) – dB
–70
Figure 6.Narrow Band SFDR vs. MCLK Frequency
MCLK FREQUENCY – MHz
SFDR (
Hz) – dB20
–45
Figure 7.Wide Band SFDR vs. MCLK Frequency
Figure 8.Wide Band SFDR vs. fOUT/fMCLK for Various
MCLK Frequencies
Figure 9.SNR vs. MCLK Frequency
Figure 10.SNR vs. fOUT/fMCLK for Various MCLK
Frequencies
AD9831–Typical Performance Characteristics
TEMPERATURE – °C
WAKE-UP TIME – ms
–10
Figure 11.Wake-Up Time vs. Temperature
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
10dB/DIV
VBW 1kHz
Figure 12.fMCLK = 25 MHz, fOUT = 1.1 MHz, Frequency
Word = B439581
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
10dB/DIV
VBW 1kHz
Figure 13.fMCLK = 25 MHz, fOUT = 2.1 MHz, Frequency
Word = 15810625
Figure 14.fMCLK = 25 MHz, fOUT = 3.1 MHz, Frequency
Word = 1FBE76C9
Figure 15.fMCLK = 25 MHz, fOUT = 4.1 MHz, Frequency
Word = 29FBE76D
Figure 16.fMCLK = 25 MHz, fOUT = 5.1 MHz, Frequency
Word = 34395810

Partno	Mfg	Dc	Qty	Available	Descript
AD9831AST	AD	N/a	37	avai	CMOS Complete DDS
AD9831AST	ADI	N/a	101	avai	CMOS Complete DDS