AD9830AST Fast Delivery |IC PHOENIX CO.,LIMITED

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AD9830AST
CMOS Complete DDS
REV.ACMOS
Complete DDS
FEATURES
+5 V Power Supply
50 MHz Speed
On-Chip SINE Look-Up Table
On-Chip 10-Bit DAC
Parallel Loading
Power-Down Option
72 dB SFDR
250 mW Power Consumption
48-Pin TQFP
APPLICATIONS
DDS Tuning
Digital Demodulation
GENERAL DESCRIPTION
This DDS device is a numerically controlled oscillator em-
ploying a phase accumulator, a sine look-up table and a
10-bit D/A converter integrated on a single CMOS chip.
Modulation capabilities are provided for phase modulation
and frequency modulation.
Clock rates up to 50 MHz are supported. Frequency accu-
racy can be controlled to one part in 4 billion. Modulation
is effected by loading registers through the parallel micro-
processor interface.
A power-down pin allows external control of a power-down
mode. The part is available in a 48-pin TQFP package.
FUNCTIONAL BLOCK DIAGRAM
RESET
SLEEP
IOUT
IOUT
COMP
REFINFS ADJUSTREFOUTAGNDAVDDDGNDDVDD
MCLK
FSELECT
D15WRA0A1A2PSEL0PSEL1
AD9830–SPECIFICATIONS1
(VDD = +5 V 6 5%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN = REFOUT;
RSET = 1kV; RLOAD = 51 V for IOUT and IOUT unless otherwise noted)
NOTES
1Operating temperature range is as follows: A Version: –40°C to +85°C.
2All dynamic specifications are measured using IOUT. 100% production tested.
3fMCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, fOUT = 2.11MHz.
4Measured with the digital inputs static and equal to 0 V or DVDD.
5The Low Power Sleep Mode current is 2 mA typically when a 1 MΩ resistor is
not tied from REFOUT to AGND.
The AD9830 is tested with a capacitive load of 50 pF. The part can be operated
with higher capacitive loads, but the magnitude of the analog output will be attenu-
ated. For example, a 10 MHz output signal will be attenuated by 3 dB when the
load capacitance equals 250 pF.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
NOTESSee Pin Description section.
Guaranteed by design, but not production tested.
MCLK
Figure 2.WR–MCLK Relationship
A0, A1, A2
DATA
Figure 3.Writing to a Phase/Frequency Register
t9A
MCLK
FSELECT
PSEL0, PSEL1
(VDD = +5 V 6 5%; AGND = DGND = 0 V, unless otherwise noted)
AD9830
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . .–0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . .–0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . .+150°C
TQFP θJA Thermal Impedance . . . . . . . . . . . . . . . . .75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although this device features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
*ST = Thin Quad Flatpack (TQFP).
PIN CONFIGURATIONAVDDFS ADJUSTAGNDNCAGND
AGND
AGND
RESET
DB0
DB1
DB11
DGND
DB15DB14DB13
DB12DB10
REFIN
REFOUT
SLEEP
DVDD
DVDD
DGND
MCLK
NC = NO CONNECT
DVDD
FSELECT
PSEL0
DGND
DB2
DB3
DB4
DB9DB8
DB7DB6
COMP
DB5
PSEL1DVDD
AVDDIOUT
IOUT
PIN DESCRIPTION
POWER SUPPLY
AVDDPositive power supply for the analog section. A 0.1 μF capacitor should be connected between AVDD and
AGND. AVDD has a value of +5 V ± 5%.
AGNDAnalog Ground.
DVDDPositive power supply for the digital section. A 0.1 μF decoupling capacitor should be connected between DVDD
and DGND. DVDD has a value of +5 V ± 5%.
DGNDDigital Ground.
ANALOG SIGNAL AND REFERENCE
IOUT, IOUTCurrent Output. This is a high impedance current source. A load resistor should be connected between IOUT
and AGND. IOUT should be either tied directly to AGND or through an external load resistor to AGND.
FS ADJUSTFull-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines the mag-
nitude of the full-scale DAC current. The relationship between RSET and the full-scale current is as follows:
IOUTFULL-SCALE = 16 VREFIN/RSET
VREFIN = 1.21 V nominal, RSET = 1 kΩ typical
REFINVoltage Reference Input. The AD9830 can be used with either the on-board reference, which is available from pin
REFOUT, or an external reference. The reference to be used is connected to the REFIN pin. The AD9830 ac-
cepts a reference of 1.21 V nominal.
REFOUTVoltage Reference Output. The AD9830 has an on-board reference of value 1.21 V nominal. The reference is
made available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUT
to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.
COMPCompensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic
capacitor should be connected between COMP and AVDD.
DIGITAL INTERFACE AND CONTROL
AD9830
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale, a point 0.5
LSB below the first code transition (000 . . . 00 to 000 . . . 01)
and full scale, a point 0.5 LSB above the last code transition
(111 . . . 10 to 111 . . . 11). The error is expressed in LSBs.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between two adjacent codes in the DAC.
Signal to (Noise + Distortion)
Signal to (Noise + Distortion) is measured signal to noise at the
output of the DAC. The signal is the rms magnitude of the fun-
damental. Noise is the rms sum of all the nonfundamental sig-
nals up to half the sampling frequency (fMCLK/2) but excluding
the dc component. Signal to (Noise + Distortion) is dependent
on the number of quantization levels used in the digitization
process; the more levels, the smaller the quantization noise.
The theoretical Signal to (Noise + Distortion) ratio for a sine
wave input is given by
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
where N is the number of bits. Thus, for an ideal 10-bit con-
verter, Signal to (Noise + Distortion) = 61.96 dB.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the rms sum
of harmonics to the rms value of the fundamental. For the
AD9830, THD is defined as
THD=20log
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic.
Output Compliance
The output compliance refers to the maximum voltage which
can be generated at the output of the DAC to meet the specifi-
cations. When voltages greater than that specified for the out-
put compliance are generated, the AD9830 may not meet the
specifications listed in the data sheet. For the AD9830, the
maximum voltage which can be generated by the DAC is 1V.
Spurious Free Dynamic Range
Along with the frequency of interest, harmonics of the funda-
mental frequency and images of the MCLK frequency will be
present at the output of a DDS device. The spurious free dy-
namic range (SFDR) refers to the largest spur or harmonic
which is present in the band of interest. The wideband SFDR
gives the magnitude of the largest harmonic or spur relative to
the magnitude of the fundamental frequency in the bandwidth
±2 MHz about the fundamental frequency. The narrowband
SFDR gives the attenuation of the largest spur or harmonic in a
bandwidth of ±200 kHz and ±50 kHz about the fundamental
frequency.
Clock Feedthrough
There will be feedthrough from the MCLK input to the analog
output. The clock feedthrough refers to the magnitude of the
MCLK signal relative to the fundamental frequency in the
AD9830’s output spectrum.
MCLK FREQUENCY – MHz
TOTAL CURRENT – mA1020304050
Figure 5.Typical Current Consumption vs. MCLK
Frequency
MCLK FREQUENCY – MHz
SFDR (
200kHz) - dB
–75
Figure 6.Narrow Band SFDR vs. MCLK Frequency
MCLK FREQUENCY – MHz
SFDR (
2MHz
) – dB40
–45
Figure 7.Wide Band SFDR vs. MCLK Frequency
Figure 8.WB SFDR vs. fOUT/fMCLK for Various MCLK
Frequencies
SNR – dB
MCLK FREQUENCY – MHz1050203040
Figure 9.SNR vs. MCLK Frequency
fOUT/fMCLK0.40.10.20.3
SNR – dB
Figure 10.SNR vs. fOUT/fMCLK for Various MCLK
Frequencies
AD9830
RBW 1kHz VBW 3kHz ST 50 SEC
10dB/DIV
START 0HzSTOP 25MHz
–50
Figure 14.fMCLK = 50 MHz, fOUT = 9.1 MHz, Frequency
Word = 2E978D50
RBW 1kHz VBW 3kHz ST 50 SEC
10dB/DIV
START 0HzSTOP 25MHz
–50
Figure 15.fMCLK = 50 MHz, fOUT = 11.1 MHz, Frequency
Word = 38D4FDF4
RBW 1kHz VBW 3kHz ST 50 SEC
10dB/DIV
START 0HzSTOP 25MHz
–50
Figure 16.fMCLK = 50 MHz, fOUT = 13.1 MHz, Frequency
Word = 43126E98
RBW 1kHz VBW 3kHz ST 50 SEC
10dB/DIV
START 0HzSTOP 25MHz
–50
Figure 11.fMCLK = 50 MHz, fOUT = 2.1 MHz, Frequency
Word = ACO8312
RBW 1kHz VBW 3kHz ST 50 SEC
10dB/DIV
START 0HzSTOP 25MHz
–50
Figure 12.fMCLK = 50 MHz, fOUT = 3.1 MHz, Frequency
Word = FDF3B64
RBW 1kHz VBW 3kHz ST 50 SEC
10dB/DIV
START 0HzSTOP 25MHz
–50
Figure 13.fMCLK = 50 MHz, fOUT = 7.1 MHz, Frequency
Word = 245A1CAC

Partno	Mfg	Dc	Qty	Available	Descript
AD9830AST	ADI	N/a	452	avai	CMOS Complete DDS
AD9830AST	AD	N/a	119	avai	CMOS Complete DDS