AD9826KRSRL ,Complete 16-Bit Imaging Signal ProcessorSPECIFICATIONSMIN MAXParameter Symbol Min Typ Max UnitCLOCK PARAMETERS3-Channel Pixel Rate t 200 ns ..
AD9826KRSZ ,Complete 16-Bit Imaging Signal ProcessorSPECIFICATIONS Gain = 1, Input range = 4 V p-p, unless otherwise noted.)Parameter Min Typ Max UnitM ..
AD9826KRSZRL , Complete 16-Bit Imaging Signal Processor
AD9826KRSZRL , Complete 16-Bit Imaging Signal Processor
AD9830AST ,CMOS Complete DDSSpecificationsSignal-to-Noise Ratio 50 dB min f = f , f = 2 MHzMCLK MAX OUTTotal Harmonic Distortio ..
AD9830AST ,CMOS Complete DDSAPPLICATIONSA power-down pin allows external control of a power-downDDS Tuningmode. The part is ava ..
ADSP/2101KG/66 ,ADSP-2100 Family DSP MicrocomputersOVERVIEW . . . . . . . . . . . . . . . . . . . . 4Supply Current & Power . . . . . . . . . . . . . ..
ADSP/2181KST/133 ,DSP Microcomputerapplications.and Data StorageIndependent ALU, Multiplier/Accumulator, and BarrelThe ADSP-2181 combi ..
ADSP/2186BST/160 ,DSP Microcomputeroverview of ADSP-2186 func-tionality. For additional information on the architecture andDevelopment ..
ADSP-2100AJG ,12.5 MIPS DSP Microprocessorspecifications differ as shown in those sections of the data sheet.
Both processors integrate co ..
ADSP-2101BP-100 ,ADSP-2100 Family DSP MicrocomputersOVERVIEW . . . . . . . . . . . . . . . . . . . . 4Supply Current & Power . . . . . . . . . . . . . ..
ADSP-2101BP-66 ,ADSP-2100 Family DSP MicrocomputersCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 2180-Lead PQFP, 80-Lead TQFP . ..
AD9826KRSRL-AD9826KRSZ
Complete 16-Bit Imaging Signal Processor
REV. A
Complete 16-Bit Imaging
Signal Processor
FUNCTIONAL BLOCK DIAGRAM
OEB
DOUT
SCLK
SLOAD
SDATA
ADCCLKCDSCLK2CDSCLK1
OFFSET
VINB
VING
VINR
AVDDAVSSCMLCAPTAVDDAVSS
DRVDDDRVSS
CAPB
FEATURES
16-Bit 15 MSPS A/D Converter
3-Channel 16-Bit Operation up to 15 MSPS
1-Channel 16-Bit Operation up to 12.5 MSPS
2-Channel Mode for Mono Sensors with Odd/Even Outputs
Correlated Double Sampling
1~6� Programmable Gain�300 mV Programmable Offset
Input Clamp Circuitry
Internal Voltage Reference
Multiplexed Byte-Wide Output
Optional Single Byte Output Mode
3-Wire Serial Digital Interface
3 V/5 V Digital I/O Compatibility
28-Lead SSOP Package
Low Power CMOS: 400 mW (Typ)
Power-Down Mode Available
APPLICATIONS
Flatbed Document Scanners
Digital Copier
Multifunction Peripherals
Infrared Imaging Applications
Machine Vision
PRODUCT DESCRIPTIONThe AD9826 is a complete analog signal processor for imaging
applications. It features a 3-channel architecture designed to
sample and condition the outputs of trilinear color CCD arrays.
Each channel consists of an input clamp, Correlated Double
Sampler (CDS), offset DAC, and Programmable Gain Amplifier
(PGA), multiplexed to a high-performance 16-bit A/D converter.
The AD9826 can operate at speeds greater than 15 MSPS with
reduced performance.
The CDS amplifiers may be disabled for use with sensors that
do not require CDS, such as Contact Image Sensors (CIS),
CMOS active pixel sensors, and Focal Plane Arrays.
The 16-bit digital output is multiplexed into an 8-bit output word,
which is accessed using two read cycles. There is an optional
single byte output mode. The internal registers are programmed
through a 3-wire serial interface, and provide adjustment of
the gain, offset, and operating mode.
The AD9826 operates from a single 5 V power supply, typically
consumes 400 mW of power, and is packaged in a 28-lead SSOP.
AD9826–SPECIFICATIONS
ANALOG SPECIFICATIONSPOWER SUPPLY REJECTION
DIFFERENTIAL VREF (at 25°C)
NOTESLinear Input Signal Range is from 0 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9826’s input clamp.The PGA Gain is approximately “linear in dB” and follows the equation:
(TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS Mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz, PGA
Gain = 1, Input range = 4 V p-p, unless otherwise noted.)
AD9826
DIGITAL SPECIFICATIONSLOGIC OUTPUTS
SERIAL INTERFACE
NOTES
It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge.
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS Mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz,
CL = 10 pF, unless otherwise noted.)
AD9826
ORDERING GUIDE
THERMAL CHARACTERISTICS
Thermal Resistance28-Lead 5.3 mm SSOP
θJA = 109°C/W
θJC = 39°C/W
ABSOLUTE MAXIMUM RATINGS*Digital Outputs
Junction Temperature
Storage Temperature
Lead Temperature
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9826 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recom-
mended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONSTYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
PIN CONFIGURATION
AD9826
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)Integral nonlinearity error refers to the deviation of each individual
code from a line drawn from “zero scale” through “positive full
scale.” The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a level
1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL)An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width. No missing codes guaranteed
to 16-bit resolution indicates that all 65536 codes, respec-
tively, must be present over all operating ranges.
OFFSET ERRORThe first ADC code transition should occur at a level 1/2 LSB
above the nominal zero scale voltage. The offset error is the
deviation of the actual first code transition level from the
ideal level.
GAIN ERRORThe last code transition should occur for an analog value
1 1/2 LSB below the nominal full scale voltage. Gain error is
the deviation of the actual difference between first and last
code transitions and the ideal difference between the first and
last code transitions.
INPUT REFERRED NOISEThe rms output noise is measured using histogram techniques.
The ADC output codes’ standard deviation is calculated in
LSB, and can be converted to an equivalent voltage, using the
relationship 1 LSB = 4 V/65536 = 61 μV. The noise may then
be referred to the input of the AD9826 by dividing by the
PGA gain.
CHANNEL-TO-CHANNEL CROSSTALKIn an ideal 3-channel system, the signal in one channel will not
influence the signal level of another channel. The channel-to-
channel crosstalk specification is a measure of the change that
occurs in one channel as the other two channels are varied. In
the AD9826, one channel is grounded and the other two chan-
nels are exercised with full scale input signals. The change in the
output codes from the first channel is measured and compared
with the result when all three channels are grounded. The differ-
ence is the channel-to-channel crosstalk, stated in LSB.
APERTURE DELAYThe aperture delay is the time delay that occurs from when a
sampling edge is applied to the AD9826 until the actual sample
of the input signal is held. Both CDSCLK1 and CDSCLK2
sample the input signal during the transition from high to low,
so the aperture delay is measured from each clock’s falling edge
to the instant the actual internal sample is taken.
POWER SUPPLY REJECTIONPower supply rejection specifies the maximum full-scale change
that occurs from the initial value when the supplies are varied
over the specified limits.
TPC 1. Typical INL Performance at 15 MSPS
TPC 2. Typical DNL Performance at 15 MSPS
TPC 3.Output Noise vs. Gain
TPC 4. Typical INL Performance at 30 MSPS
TPC 5. Typical DNL Performance at 30 MSPS
GAIN SETTING015
NOISE
LSB RMS54563TPC 6.Input Referred Noise vs. Gain
AD9826
TIMING DIAGRAMSFigure 1.3-Channel CDS Mode Timing
It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge.
Figure 2.1-Channel CDS Mode Timing
Figure 3.2-Channel CDS Mode Timing
tADCLKtADCLK
tC2ADR
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
PIXEL n
PIXEL
(n+1)
tC2
tC2ADFtADC2
HIGH
BYTE
LOW
BYTE
LOW
BYTE
LOW
BYTE
LOW
BYTE
LOW
BYTE
HIGH
BYTE
HIGH
BYTE
HIGH
BYTE
HIGH
BYTEFigure 4.2-Channel SHA Mode Timing
AD9826Figure 5.3-Channel SHA Mode Timing
Figure 6.1-Channel SHA Mode Timing
