AD9822JRSRL ,Complete 14-Bit CCD/CIS Signal ProcessorAPPLICATIONSconsumes 385 mW of power, and is packaged in a 28-lead SOICFlatbed Document Scannersor ..
AD9822JRSZ ,Complete 14-Bit CCD/CIS Signal ProcessorSPECIFICATIONS Gain = 1, unless otherwise noted.)Parameter Min Typ Max UnitMAXIMUM CONVERSION RATE3 ..
AD9822JRSZRL , Complete 14-Bit CCD/CIS Signal Processor
AD9826KRS ,Complete 16-Bit Imaging Signal ProcessorSPECIFICATIONSMIN MAXParameter Symbol Min Typ Max UnitCLOCK PARAMETERS3-Channel Pixel Rate t 200 ns ..
AD9826KRSRL ,Complete 16-Bit Imaging Signal ProcessorSPECIFICATIONSMIN MAXParameter Symbol Min Typ Max UnitCLOCK PARAMETERS3-Channel Pixel Rate t 200 ns ..
AD9826KRSZ ,Complete 16-Bit Imaging Signal ProcessorSPECIFICATIONS Gain = 1, Input range = 4 V p-p, unless otherwise noted.)Parameter Min Typ Max UnitM ..
ADSP/2101KG/66 ,ADSP-2100 Family DSP MicrocomputersOVERVIEW . . . . . . . . . . . . . . . . . . . . 4Supply Current & Power . . . . . . . . . . . . . ..
ADSP/2181KST/133 ,DSP Microcomputerapplications.and Data StorageIndependent ALU, Multiplier/Accumulator, and BarrelThe ADSP-2181 combi ..
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ADSP-2100AJG ,12.5 MIPS DSP Microprocessorspecifications differ as shown in those sections of the data sheet.
Both processors integrate co ..
ADSP-2101BP-100 ,ADSP-2100 Family DSP MicrocomputersOVERVIEW . . . . . . . . . . . . . . . . . . . . 4Supply Current & Power . . . . . . . . . . . . . ..
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AD9822JRSRL-AD9822JRSZ
Complete 14-Bit CCD/CIS Signal Processor
REV. A
Complete 14-Bit
CCD/CIS Signal Processor
FUNCTIONAL BLOCK DIAGRAM
BANDGAP
REFERENCE
BLUE
GREEN
RED
BLUE
GREEN
RED
GAIN
REGISTERS
OFFSET
REGISTERS
AD9822
DRVDDDRVSSAVDDAVSSCAPTCAPBAVDDAVSSCML
OEB
DOUT
SCLK
SLOAD
SDATA
ADCCLKCDSCLK2CDSCLK1
OFFSET
VINB
VING
VINR
FEATURES
14-Bit 15 MSPS A/D Converter
No Missing Codes Guaranteed
3-Channel Operation Up to 15 MSPS
1-Channel Operation Up to 12.5 MSPS
Correlated Double Sampling
1–6x Programmable Gain6350 mV Programmable Offset
Input Clamp Circuitry
Internal Voltage Reference
Multiplexed Byte-Wide Output (8+6 Format)
3-Wire Serial Digital Interface
3 V/5 V Digital I/O Compatibility
28-Lead SOIC or SSOP
Low Power CMOS: 385 mW (Typ)
Power-Down Mode: <1 mW
APPLICATIONS
Flatbed Document Scanners
Film Scanners
Digital Color Copiers
Multifunction Peripherals
PRODUCT DESCRIPTIONThe AD9822 is a complete analog signal processor for CCD
imaging applications. It features a 3-channel architecture
designed to sample and condition the outputs of trilinear
color CCD arrays. Each channel consists of an input clamp,
Correlated Double Sampler (CDS), offset DAC and Pro-
grammable Gain Amplifier (PGA), multiplexed to a high
performance 14-bit A/D converter.
The CDS amplifiers may be disabled for use with sensors such
as Contact Image Sensors (CIS) and CMOS active pixel sensors,
which do not require CDS.
The 14-bit digital output is multiplexed into an 8-bit output
word that is accessed using two read cycles. The internal
registers are programmed through a 3-wire serial interface, and
provide adjustment of the gain, offset, and operating mode.
The AD9822 operates from a single 5 V power supply, typically
consumes 385 mW of power, and is packaged in a 28-lead SOIC
or SSOP.
AD9822–SPECIFICATIONS
ANALOG SPECIFICATIONS
(TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS Mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz, PGA
Gain = 1, unless otherwise noted.)
DIGITAL SPECIFICATIONSSpecifications subject to change without notice.
TIMING SPECIFICATIONS
(TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS Mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz,
CL = 10 pF, unless otherwise noted.)
(TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V)NOTESLinear input signal range is from 2 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9822’s input clamp.
RESET TRANSIENT
4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE)The PGA Gain is approximately “linear in dB” and follows the equation:
Specifications subject to change without notice.
AD9822
AD9822
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9822 features proprietary ESD protection circuitry, permanent damage may
ABSOLUTE MAXIMUM RATINGS*Storage Temperature
Lead Temperature
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
ORDERING GUIDE
THERMAL CHARACTERISTICS
Thermal Resistance28-Lead 300 Mil SOIC28-Lead 5.3 mm SSOPJA = 71.4°C/WqJA = 109°C/WJC = 23°C/WqJC = 39°C/W
PIN CONFIGURATION
CDSCLK1AVDD
CDSCLK2AVSS
ADCCLKVINR
OEBOFFSET
DRVDDVING
DRVSSCML
(MSB) D7VINBCAPTCAPBAVSSAVDDSLOADSCLK
(LSB) D0SDATA
PIN FUNCTION DESCRIPTIONSTYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO =
Digital Output, P = Power.
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)Integral nonlinearity error refers to the deviation of each individual
code from a line drawn from “zero scale” through “positive full
scale.” The point used as “zero scale” occurs 1/2 LSB before
the first code transition. “Positive full scale” is defined as a level
1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL)An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width. No missing codes guaranteed to
14-bit resolution indicates that all 16384 codes, respectively,
must be present over all operating ranges.
OFFSET ERRORThe first ADC code transition should occur at a level 1/2 LSB
above the nominal zero scale voltage. The offset error is the
deviation of the actual first code transition level from the
ideal level.
GAIN ERRORThe last code transition should occur for an analog value
1 1/2 LSB below the nominal full-scale voltage. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between the first and last
code transitions.
INPUT REFERRED NOISEThe rms output noise is measured using histogram techniques.
The ADC output codes’ standard deviation is calculated in LSB,
and converted to an equivalent voltage, using the relationship
1 LSB = 4 V/16384 = 244 mV. The noise is then referred to the
input of the AD9822 by dividing by the PGA gain.
CHANNEL-TO-CHANNEL CROSSTALKIn an ideal 3-channel system, the signal in one channel will not
influence the signal level of another channel. The channel-to-
channel crosstalk specification is a measure of the change that
occurs in one channel as the other two channels are varied. In the
AD9822, one channel is grounded and the other two channels
are exercised with full-scale input signals. The change in the
output codes from the first channel is measured and compared
with the result when all three channels are grounded. The
difference is the channel-to-channel crosstalk, stated in LSB.
APERTURE DELAYThe aperture delay is the time delay that occurs from when a
sampling edge is applied to the AD9822 until the actual sample
of the input signal is held. Both CDSCLK1 and CDSCLK2
sample the input signal during the transition from high to low,
so the aperture delay is measured from each clock’s falling edge
to the instant the actual internal sample is taken.
POWER SUPPLY REJECTIONPower Supply Rejection specifies the maximum full-scale change
that occurs from the initial value when the supplies are varied
over the specified limits.
AD9822
PIXEL N (R, G, B)
tADC2tC2ADRtOD
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
tAD
tC1
CDSCLK1Figure 1.3-Channel CDS Mode Timing
tADPIXEL N
tAD
ANALOG
INPUTS
tOD
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
tC2
PIXEL (N–4)PIXEL (N–4)PIXEL (N–3)PIXEL (N–3)
tC1C2
tC1
CDSCLK1
tADC1
HIGH BYTELOW BYTELOW BYTEHIGH BYTE
tC2ADRFigure 2.1-Channel CDS Mode Timing
PIXEL N (R, G, B)
tC2
tADC2tC2ADRtOD
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTEFigure 3.3-Channel SHA Mode Timing
Figure 4.1-Channel SHA Mode Timing
AD9822
tHZ
tODtOD
ADCCLK
OUTPUT
DATA
OEB
PIXEL NPIXEL NFigure 5.Digital Output Data Timing
SDATA
SCLK
SLOAD
tDStDH
tLStLHFigure 6.Serial Write Operation Timing
SDATA
SCLK
SLOAD
tDStRDVtDH
tLStLHFigure 7.Serial Read Operation Timing
