AD9821KSTRL Fast Delivery |IC PHOENIX CO.,LIMITED

AD9821KSTRL ,12-Bit 40 MSPS Imaging Signal ProcessorAPPLICATIONSment, black level adjustment, and power-down modes.Digital Still Cameras Using CMOS Ima ..
AD9822JR ,Complete 14-Bit CCD/CIS Signal ProcessorSPECIFICATIONS C = 10 pF, unless otherwise noted.)LParameter Symbol Min Typ Max UnitLOGIC INPUTSHig ..
AD9822JRS ,Complete 14-Bit CCD/CIS Signal ProcessorSPECIFICATIONS Gain = 1, unless otherwise noted.)Parameter Min Typ Max UnitMAXIMUM CONVERSION RATE3 ..
AD9822JRSRL ,Complete 14-Bit CCD/CIS Signal ProcessorAPPLICATIONSconsumes 385 mW of power, and is packaged in a 28-lead SOICFlatbed Document Scannersor ..
AD9822JRSZ ,Complete 14-Bit CCD/CIS Signal ProcessorSPECIFICATIONS Gain = 1, unless otherwise noted.)Parameter Min Typ Max UnitMAXIMUM CONVERSION RATE3 ..
AD9822JRSZRL , Complete 14-Bit CCD/CIS Signal Processor
ADSP/2101KG/66 ,ADSP-2100 Family DSP MicrocomputersOVERVIEW . . . . . . . . . . . . . . . . . . . . 4Supply Current & Power . . . . . . . . . . . . . ..
ADSP/2181KST/133 ,DSP Microcomputerapplications.and Data StorageIndependent ALU, Multiplier/Accumulator, and BarrelThe ADSP-2181 combi ..
ADSP/2186BST/160 ,DSP Microcomputeroverview of ADSP-2186 func-tionality. For additional information on the architecture andDevelopment ..
ADSP-2100AJG ,12.5 MIPS DSP Microprocessorspecifications differ as shown in those sections of the data sheet. Both processors integrate co ..
ADSP-2101BP-100 ,ADSP-2100 Family DSP MicrocomputersOVERVIEW . . . . . . . . . . . . . . . . . . . . 4Supply Current & Power . . . . . . . . . . . . . ..
ADSP-2101BP-66 ,ADSP-2100 Family DSP MicrocomputersCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 2180-Lead PQFP, 80-Lead TQFP . ..

AD9821KSTRL
12-Bit 40 MSPS Imaging Signal Processor
REV.0
Complete 12-Bit 40 MSPS
Imaging Signal Processor
FEATURES
Differential Sensor Input with 1 V p-p Input Range
0 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Optical Black Clamp Circuit
Analog Preblanking Function
12-Bit 40 MSPS A/D Converter (ADC)
3-Wire Serial Digital Interface
3 V Single-Supply Operation
Low Power: 150 mW @ 3V Supply
48-Lead LQFP Package
APPLICATIONS
Digital Still Cameras Using CMOS Imagers
Industrial/Scientific Imaging
FUNCTIONAL BLOCK DIAGRAM
DATACLK
DOUTVIN+
PBLKVRTVRB
AVDD
DVDD
DVSS
AVSS
DRVDD
DRVSS
SDATASCKSL
CLPOB
VIN–
BYP1
GENERAL DESCRIPTION
The AD9821 is a complete analog signal processor for imaging
applications that do not require Correlated Double Sampling
(CDS). It features a 40 MHz single-channel architecture designed
to sample and condition the outputs of CMOS imagers and CCD
arrays already containing on-chip CDS. The AD9821’s signal
chain consists of a differential input sample-and-hold amplifier
(SHA), digitally controlled variable gain amplifier (VGA), black
level clamp, and a 12-bit ADC.
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjust-
ment, black level adjustment, and power-down modes.
The AD9821 operates from a single 3 V power supply, typically
dissipates 150 mW, and is packaged in a 48-lead LQFP.
AD9821–SPECIFICATIONS
GENERAL SPECIFICATIONS
POWER SUPPLY VOLTAGE
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Specifications subject to change without notice.
(DRVDD = 2.7 V, CL = 20 pF, unless otherwise noted.)
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 40 MHz, unless otherwise noted.)
IMAGER-MODE SPECIFICATIONS
VARIABLE GAIN AMPLIFIER (VGA)
BLACK LEVEL CLAMP
SYSTEM PERFORMANCE
*Input Signal Characteristics defined as follows:
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 40 MHz, unless otherwise noted.)
AD9821
ABSOLUTE MAXIMUM RATINGS
TIMING SPECIFICATIONS
DATA OUTPUTS
SERIAL INTERFACE
*Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
(CL = 20 pF, fSAMP = 40 MHz, Imager-Mode Timing in Figures 5 and 6, Serial Timing in Figures 7–9)
ORDERING GUIDE
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
θJA = 56°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9821 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
TEST
AVSS
TEST
AVDD2
BYP1
VIN–
VIN+
(LSB) D0
NC = NO CONNECT
D10
TEST
TEST
AVDD1
AVSS
(MSB) D11AVSSNCSCKSDATASLSTBYNCDVSSDVDD2VRBVRTNC
DRVDD
DRVSS
DVSS
DATACLK
DVDD1
PBLK
CLPOB
TESTTESTTEST
PIN FUNCTION DESCRIPTIONS
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
AD9821
DEFINITIONS OF SPECIFICATIONS
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus, every
code must have a finite width. No missing codes guaranteed to
12-bit resolution indicates that all 4096 codes, respectively,
must be present over all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9821 from a true straight
line. The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a Level 1,
1/2 LSB beyond the last code transition. The deviation is mea-
sured from the middle of each particular output code to the true
straight line. The error is then expressed as a percentage of the
2 V ADC full-scale signal. The input signal is always appropriately
gained up to fill the ADC’s full-scale range.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage using the relationship 1 LSB =
(ADC Full Scale/2N codes) when N is the bit resolution of the ADC.
For the AD9821, 1 LSB is 500 µV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD9821’s power supply. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
Internal Delay for SHA
The internal delay (also called aperture delay) is the time delay
that occurs from when the sampling edge is applied to the AD9821
until the actual sample of the input signal is held. The DATACLK
samples the input signal during the transition from low to high,
so the internal delay is measured from each clock’s rising edge
to the instant the actual internal sample is taken.
EQUIVALENT INPUT CIRCUITS
Figure 1.Digital Inputs— DATACLK, CLPOB, PBLK, SCK, SL
DVDD
DRVDD
THREE-
STATE
DATA
DOUT
Figure 3.VIN+ and VIN– (Pins 30 and 31)
TPC 1.Power vs. Sample Rate
TPC 2.Typical DNL Performance
TPC 3.Output Noise vs. VGA Gain
AD9821
IMAGER MODE AND AUX MODE TIMING
Figure 5.Imager Mode Timing
IMAGER
SIGNAL
EFFECTIVE PIXELS
CLPOB
OPTICAL BLACK PIXELS
HORIZONTAL
BLANKINGEFFECTIVE PIXELS
PBLK
NOTES:
1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
OUTPUT
DATA
Figure 6.Typical Imager Mode Line Clamp Timing

Partno	Mfg	Dc	Qty	Available	Descript
AD9821KSTRL	AD	N/a	1587	avai	12-Bit 40 MSPS Imaging Signal Processor