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ADS931E ,SpeedPlus 8-Bit, 30MHz Sampling Analog-To-Digital ConverterMAXIMUM RATINGSELECTROSTATIC+V .... +6VSDISCHARGE SENSITIVITYAnalog Input ..... (–0.3V) to (+V +0.3 ..
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AD9816JS
Complete 12-Bit 6 MSPS CCD/CIS Signal Processor
REV.A
Complete 12-Bit 6 MSPS
CCD/CIS Signal Processor
FUNCTIONAL BLOCK DIAGRAM
FEATURES
12-Bit 6 MSPS A/D Converter
No Missing Codes Guaranteed
3-Channel or 1-Channel Operation
Correlated Double Sampling
8-Bit Programmable Gain
8-Bit Offset Adjustment
PGA Output Monitor
Input Clamp Circuitry
Internal Voltage Reference
3-Wire Serial Interface
+3.3 V/+5 V Digital Output Compatibility
44-Lead MQFP Package
Low Power CMOS: 420 mW Typ
PRODUCT DESCRIPTIONThe AD9816 is a complete analog signal processor for CCD
and CIS applications. Included is all the necessary circuitry to
perform three-channel conditioning and sampling for a variety
of imaging applications.
The signal chain consists of an input clamp, correlated double
sampler (CDS), offset adjust DAC, programmable gain ampli-
fier and a 12-bit A/D converter. The CDS and input clamp may
be disabled for CIS applications.
The internal registers are programmed using a 3-wire serial
interface and provide adjustment of the gain, offset and operat-
ing mode.
The AD9816 operates from a +5 V supply, typically consumes
420 mW of power and is packaged in a 44-lead MQFP.
AD9816–SPECIFICATIONS
ANALOG SPECIFICATIONS(TMIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, DRVDD = +5.0 V, CDS Mode, fADCCLK = 6 MHz,
fCDSCLK1 = 2 MHz, fCDSCLK2 = 2 MHz, PGA Gain = 1, Input Range = 3 V p-p, Input Capacitor = 1200 pF, unless otherwise noted)NOTESIncludes internal voltage reference error.Input voltage range is the linear region over which the input signal can be processed by the input stage of the AD9816.
AD9816DIGITAL SPECIFICATIONS(TMIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, DRVDD = +5.0 V, fADCCLK = 6 MHz,
fCDSCLK1 = 2 MHz, fCDSCLK2 = 2 MHz, CL = 10 pF unless otherwise noted)Specifications subject to change without notice.
TIMING SPECIFICATIONS(TMIN to TMAX with DVDD = +5.0 V, DRVDD = +5.0 V)
AD9816Figure 1.3-Channel CDS Mode Timing
Figure 2.3-Channel SHA Mode Timing
Figure 3.1-Channel CDS Mode Timing
Figure 4.1-Channel SHA Mode Timing
Figure 5.Line Clamp Timing for 3-Channel CDS Mode
tOD
ADCCLK
OUTPUT
DATA,D11:D0.
OEB
tHZtDVFigure 6.Output Enable Timing
AD9816
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9816 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS**Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
ORDERING GUIDE
PIN FUNCTION DESCRIPTIONSNOTES
See Applications Information for circuit configurations.
TYPE:AI = Analog Input, AO = Analog Output, DI = Digital Input,
DO = Digital Output, DIO = Digital Input/Output, P = Power.
PIN CONFIGURATION
AD9816
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)Integral nonlinearity error refers to the deviation of each indi-
vidual code from a line drawn from “zero scale” through “posi-
tive full scale.” The point used as “zero scale” occurs 1/2 LSB
before the first code transition. “Positive full scale” is defined as
a level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL)An ideal ADC exhibits code transitions which are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width. No missing codes guaranteed to
12-bit resolution indicates that all 4096 codes, respectively,
must be present over all operating ranges.
OFFSET ERRORThe first ADC code transition should occur at a level 1/2 LSB
above the nominal zero scale voltage. The offset error is the
deviation of the actual first code transition level from the ideal
level.
GAIN ERRORThe last code transition should occur for an analog value
1 1/2 LSB below the nominal full scale voltage. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between the first and last
code transitions.
TOTAL OUTPUT NOISEAn ideal ADC outputs only one code value for a dc input
voltage. A real converter has noise sources that will cause a
spread of codes at the output for a dc input voltage. The total
output noise is measured with a grounded input and is equal to
the standard deviation of the histogram of output codes.
CHANNEL-TO-CHANNEL CROSSTALKIn an ideal three-channel system, the signal in one channel will
not influence the signal level of another channel. The channel-
to-channel crosstalk specification is a measure of the change that
occurs in one channel as the other two channels are varied. In
the AD9816, one channel is grounded and the other two chan-
nels are exercised with full-scale input signals. The change in
the output codes from the first channel is measured and com-
pared with the result when all three channels are grounded. The
difference is the channel-to-channel crosstalk, stated in LSBs.
APERTURE DELAYThe aperture delay is the time delay that occurs from when a
sampling edge is applied to the AD9816 until the actual sample
of the input signal is held. For CDSCLK1, the aperture delay
represents the amount of time it takes for the clamp switch
to open after CDSCLK1 transitions from high to low. For
CDSCLK2, the aperture delay is the amount of time after the
CDSCLK2 falling edge that the input signal is sampled.
POWER SUPPLY REJECTION
FUNCTIONAL DESCRIPTIONThe AD9816 can be operated in several different modes:
3-channel CDS mode, 3-channel SHA mode, 1-channel CDS
mode, and 1-channel SHA mode. Each mode is selected by
programming the Configuration Register through the serial
interface. For more detail on CDS or SHA mode operation, see
Circuit Descriptions section.
3-Channel CDS ModeIn 3-channel CDS mode, the AD9816 simultaneously samples
the red, green and blue input voltages from the CCD outputs.
The sampling points for each Correlated Double Sampler (CDS)
are controlled by CDSCLK1 and CDSCLK2. CDSCLK1’s fall-
ing edge clamps the reference level of the CCD waveform at the
analog inputs of the AD9816. CDSCLK2’s falling edge samples
the data level of the CCD waveform. Each CDS amplifier out-
puts the difference between the CCD reference and data levels.
Next, the output voltage of each CDS amplifier is level-shifted
by an Offset DAC. The voltages are then scaled by the three
Programmable Gain Amplifiers before being multiplexed to the
common 12-bit ADC. The ADC sequentially samples the PGA
outputs on the falling edges of ADCCLK.
Timing for this mode is shown in Figure 1, using a 2· master
clock. Although it is not required, it is recommended that the
falling edge of CDSCLK2 be aligned with the rising edge of
ADCCLK. The rising edge of CDSCLK2 should not occur
before the previous falling edge of ADCCLK, as shown by tADC2.
The maximum allowable width of CDSCLK2 will be dependent
on the ADCCLK period, and equal to one ADCCLK period
minus 30 ns. The output data latency is three clock cycles.
The offset and gain values for the red, green, and blue channels
are programmed using the serial interface. The order in which
the channels are switched through the multiplexer is selected by
programming the MUX register. The rising edge of CDSCLK2
always resets the multiplexer.
3-Channel SHA ModeIn 3-channel SHA mode, the AD9816 simultaneously samples
the red, green, and blue input voltages. The sample-and-hold
amplifier’s sampling point is controlled by CDSCLK2. CDSCLK2’s
falling edge samples the input waveforms on each channel. The
output voltages from the three SHAs are modified by the offset
DACs and then scaled by the three PGAs. The outputs of the
PGAs are then multiplexed through the 12-bit ADC. The ADC
sequentially samples the PGA outputs on the falling edges of
ADCCLK.
The input signal is sampled with respect to the voltage applied
to the OFFSET pin. With the OFFSET pin grounded, a zero
volt input corresponds to the ADC’s zero scale output. The
input clamp is disabled in this mode. However, the OFFSET
pin may be used as a coarse offset adjust pin. A voltage applied
to this pin will be subtracted from the voltages applied to the
red, green and blue inputs in the first amplifier stage of the
AD9816. For more information, see the Circuit Descriptions
section.
Timing for this mode is shown in Figure 2, using a 1· master
clock. CDSCLK1 should be grounded in this mode. Although
it is not required, it is recommended that the falling edge of
