AD9807JS ,Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal ProcessorsSPECIFICATIONS PGA Gain = 1 unless otherwise noted)Parameter Min Typ Max UnitsRESOLUTION 10 BitsCO ..
AD9814JR ,Complete 14-Bit CCD/CIS Signal Processorfeatures a 3-channel architecture de-3-Channel Operation Up to 10 MSPS signed to sample and conditi ..
AD9814JR ,Complete 14-Bit CCD/CIS Signal ProcessorSpecifications.2The Gain Error specification is dominated by the tolerance of the internal differen ..
AD9814JRRL ,Low Power 14-Bit, 3-Channel CCD Signal Processor with Progammable Serial Interface and Byte-Wide Data Output FormatSPECIFICATIONS (T to T , AVDD = +5 V, DRVDD = +5 V, 3-Channel CDS Mode, f = 6 MHz, f = f =MIN MAX A ..
AD9814KR ,Complete 14-Bit CCD/CIS Signal ProcessorSPECIFICATIONS (T to T , AVDD = +5 V, DRVDD = +5 V)MIN MAXParameter Symbol Min Typ Max UnitsCLOCK P ..
AD9814KR ,Complete 14-Bit CCD/CIS Signal ProcessorAPPLICATIONScally consumes 330 mW of power, and is packaged in a 28-leadFlatbed Document ScannersSO ..
ADS8558IPM ,730kSPS, 12-Bit, 6-Channels, Simultaneous Sampling Analog-to-Digital Converter 64-LQFP -40 to 125Features 2 Applications1• Family of 16-, 14-, 12-Bit, Pin- and • Power Quality MeasurementSoftware- ..
ADS8558IPM ,730kSPS, 12-Bit, 6-Channels, Simultaneous Sampling Analog-to-Digital Converter 64-LQFP -40 to 125Electrical Characteristics tables..... 8• Added text reference for Figure 42 ........ 32• Changed F ..
ADS900 ,10-Bit, 20MHz, +3V Supply ANALOG-TO-DIGITAL CONVERTERADS900EADS900SBAS058A – MAY 2001 10-Bit, 20MHz, +3V Supply TM ANALOG-TO-DIG ..
ADS900E ,10-Bit/ 20MHz/ #V Supply ANALOG-TO-DIGITAL CONVERTERMAXIMUM RATINGSELECTROSTATIC+V .... +6VSAnalog Input ....... +V +0.3VDISCHARGE SENSITIVITYSLogic In ..
ADS900E/1KG4 ,10-Bit, 20 MSPS ADC SE/Diff Inputs, Int Reference and Adjustable Fullscale Range 28-SSOP ABSOLUTE
ADS901E ,10-Bit/ 20MHz/ #V Supply ANALOG-TO-DIGITAL CONVERTERFEATURES DESCRIPTION* LOW POWER: 48mW at +3V The ADS901 is a high-speed pipelined analog-to-digital ..
AD9805JS-AD9807JS
Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors
REV.0
Complete 12-Bit/10-Bit 6 MSPS
CCD/CIS Signal Processors
FUNCTIONAL BLOCK DIAGRAM
CSB
VREF
PIXEL
OFFSET
PIXEL
GAIN
CDSCLK1CDSCLK2ADCCLK
VINR
VING
VINB
DOUT
PRODUCTION DESCRIPTIONThe AD9807 and AD9805 are complete CCD/CIS imaging
decoders and signal processors on a single monolithic integrated
circuit. The input of the AD9807/AD9805 allows direct ac
coupling of the charge-coupled device (CCD) or contact image
sensor (CIS) output(s). The AD9807/AD9805 includes all the
circuitry to perform three-channel correlated double sampling
(CDS) and programmable gain adjustment of the CCD output;
a 12-bit or 10-bit analog-to-digital converter (ADC) quantizes
the analog signal. After digitization, the on-board digital signal
processor (DSP) circuitry allows pixel rate offset and gain correc-
tion. The DSP also corrects odd/even CCD register imbalance
errors. A parallel control bus provides a simple interface to
8-bit microcontrollers. The AD9807/AD9805 comes in a
space saving 64-pin plastic quad flatpack (PQFP) and is specified
over the commercial (0°C to +70°C) temperature range. By
disabling the CDS, the AD9807/AD9805 are also suitable for
non-CCD applications, or applications that do not require
CDS, such as CIS signal processing.
PRODUCT HIGHLIGHTSThe AD9807/AD9805 offers a complete, single chip CCD
imaging front end in a 64-pin plastic quad flatpack (PQFP).
On-Chip PGA—The AD9807/AD9805 includes a 3-channel
analog programmable gain amplifier; it is programmable from
1× to 4× in 16 increments.
On-Chip CDS—An integrated 3-channel correlated double
sampler allows easy ac coupling directly from the CCD sensor
outputs. Additionally, the CDS reduces low frequency noise
and reset feedthrough.
On-Chip Voltage Reference—The AD9807/AD9805 includes a
2 V bandgap reference that allows the input range of the device to
be configured for input spans up to 4 V.
6 MSPS A/D Converter—A highly linear 12-bit or 10-bit A/D
converter sequentially digitizes the red, green and blue CDS
outputs ensuring no missing code performance. The user may also
configure the AD9807/AD9805 for single channel operation.
Digital Gain & Offset Correction—Pixel rate digital gain and
offset correction blocks allow precise repeatable correction of
imaging system error sources.
Digital I/O Compatibility—The AD9807/AD9805 offers
+3.3 V/+5 V logic level compatibility.
Pin-Compatible 12-Bit and 10-Bit Versions—The AD9807 is
also offered in a pin-compatible 10-bit version, the AD9805,
allowing upgrade-ability and simplifying design issues across
different scanner models.
FEATURES
Pin Compatible 12-Bit and 10-Bit Versions
12-Bit/10-Bit 6 MSPS A/D Converter
Integrated Triple Correlated Double Sampler
3-Channel, 2 MSPS Color Mode
13 – 43 Analog Programmable Gain Amplifier
Pixel-Rate Digital Gain Adjustment
Pixel-Rate Digital Offset Adjustment
Internal Voltage Reference
No Missing Codes Guaranteed
Microprocessor-Compatible Control Interface
+3.3 V/+5 V Digital I/O Compatibility
Low Power CMOS: 500 mW
64-Pin PQFP Surface Mount Package
ANALOG INPUTS
INTERNAL VOLTAGE REFERENCE
POWER SUPPLIES
NOTESBlue and green channels. Red channel conversion rate for 1-channel mode is 5 MSPS.Measured with 4 V p-p input range.Input signals exceeding these limits are subject to excessive overvoltage recovery times.
Specifications subject to change without notice.
ANALOG SPECIFICATIONS
DIGITAL SPECIFICATIONSLOGIC OUTPUTS
(TMIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, fADCCLK = 6 MSPS, fCDSCLK1 = 2 MSPS, fCDSCLK2 = 2 MSPS,
CL = 20 pF, unless otherwise noted)
(TMIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, fADCCLK = 6 MSPS, fCDSCLK1 = 2 MSPS, fCDSCLK2 = 2 MSPS,
PGA Gain = 1 unless otherwise noted)
AD9807–SPECIFICATIONS
AD9807/AD9805ANALOG INPUTS
INTERNAL VOLTAGE REFERENCE
POWER SUPPLIES
NOTESBlue and green channels. Red channel conversion rate for 1-channel mode is 5 MSPS.Measured with 4 V p-p input range.Input signals exceeding these limits are subject to excessive overvoltage recovery times.
Specifications subject to change without notice.
ANALOG SPECIFICATIONS
DIGITAL SPECIFICATIONSLOGIC OUTPUTS
(TMIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, fADCCLK = 6 MSPS, fCDSCLK1 = 2 MSPS, fCDSCLK2 = 2 MSPS,
CL = 20 pF, unless otherwise noted)
(TMIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, fADCCLK = 6 MSPS, fCDSCLK1 = 2 MSPS, fCDSCLK2 = 2 MSPS,
PGA Gain = 1 unless otherwise noted)
AD9805–SPECIFICATIONS
AD9807/AD9805
TIMING SPECIFICATIONS
(TMIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, unless otherwise noted)
Table I.Output ControlsLEGEND:
x = Don't Care
X = Unknown (Not Recommended)
Q = Outputs
D = Inputs
Z = 3-State
PIN CONFIGURATION
GAIN<11>GAIN<10>GAIN<9>GAIN<8>GAIN<7>GAIN<6>GAIN<5>GAIN<4>GAIN<3>GAIN<2>GAIN<1>GAIN<0>DVSSDVDDA2A1
AVDD
AVSS
CAPT
CAPT
CAPB
CAPB
VREF
CML
VINR
AVSS
VING
AVSS
VINB
AVSS
AVDD
STRTLN
DOUT<11>
DOUT<10>
DOUT<9>
DOUT<8>
DOUT<7>/MPU<7>
DOUT<6>/MPU<6>
DRVDD
DRVSS
DOUT<5>/MPU<5>
DOUT<4>/MPU<4>
DOUT<3>/MPU<3>
DOUT<2>/MPU<2>
DOUT<1>/MPU<1>
DOUT<0>/MPU<0>
OEB
CDSCLK1
CDSCLK2
ADCCLK
OFFSET<7>OFFSET<6>OFFSET<5>OFFSET<4>OFFSET<3>OFFSET<2>OFFSET<1>
DVSSDVDD
CSBRDB
WRB
OFFSET<0>
PIN DESCRIPTIONS
AD9807/AD9805
PIN CONFIGURATION
GAIN<9>GAIN<8>GAIN<7>NCGAIN<6>GAIN<5>GAIN<4>GAIN<3>GAIN<2>GAIN<1>GAIN<0>DVSSDVDDA2A1
AVDD
AVSS
CAPT
CAPT
CAPB
CAPB
VREF
CML
VINR
AVSS
VING
AVSS
VINB
AVSS
AVDD
STRTLN
DOUT<9>
DOUT<8>
DOUT<7>
DOUT<6>
DOUT<5>/MPU<7>
DOUT<4>/MPU<6>
DRVDD
DRVSS
DOUT<3>/MPU<5>
DOUT<2>/MPU<4>
DOUT<1>/MPU<3>
DOUT<0>/MPU<2>
MPU<1>
MPU<0>
OEB
CDSCLK1
CDSCLK2
ADCCLK
OFFSET<7>OFFSET<6>OFFSET<5>OFFSET<4>OFFSET<3>OFFSET<2>OFFSET<1>
DVSS
DVDD
CSBRDB
WRB
OFFSET<0>
NC = NO CONNECT
PIN DESCRIPTIONS
WARNING!
ESD SENSITIVE DEVICE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9807/AD9805 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS**Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods may affect device reliability.
ORDERING GUIDE*S = Plastic Quad Flatpack.
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITYLinearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as “negative full scale” occurs 1/2 LSB
before the first code transition. “Positive full scale” is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL LINEARITY ERROR (DNL, NO MISSING
CODES)An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width. Guaranteed no missing codes
to 12-bit resolution indicates that all 4096 codes, respectively,
must be present over all operating ranges.
UNIPOLAR OFFSET ERRORIn the unipolar mode, the first transition should occur at a level
1/2 LSB above analog common. Unipolar offset is defined as
the deviation of the actual from that point. The unipolar offset
temperature coefficient specifies the maximum change of the
transition point over temperature, with or without external
adjustments.
GAIN ERRORThe last transition should occur for an analog value 1 1/2 LSB
below the nominal full scale. Gain error is the deviation of the
actual difference between first and last code transitions and the
ideal difference between first and last code transitions.
POWER SUPPLY REJECTIONPower Supply Rejection specifies the maximum full-scale change
from the initial value with the supplies at the various limits.
APERTURE DELAYAperture delay is a timing measurement between the sampling
clocks and the CDS. It is measured from the falling edge of the
CDSCLK2 input to when the input signal is held for conversion
in CDS mode. In non-CDS mode, it is the falling edge of
CDSCLK1.
AD9807/AD9805tS
tGOH
tC1AD
tACLKtSTL1
ANALOG
INPUTS
STRTLN
CDSCLK1
CDSCLK2
ADCCLK
GAIN
OFFSETFigure 1a.3-Channel CDS-Mode Clock Timing
tGOStCP
tC2A
CDSCLK1
ADCCLK
GAIN
OFFSETtStH
STRTLN
(0V)
ANALOG
INPUTSFigure 1b.3-Channel SHA-Mode Clock Timing
tGOH
CDSCLK1
tAD
ANALOG
INPUTS
STRTLN
CDSCLK2
ADCCLK
GAIN
OFFSET
tGOHtGOS
CDSCLK1
tAD
ANALOG
INPUTS
STRTLN
CDSCLK2
ADCCLK
GAIN
OFFSET
Figure 1d.1-Channel CDS-Mode Clock Timing (Red Channel)
CDSCLK1
tCRBtStH
STRTLN
tAD
(0V)
ANALOG
INPUTStSTL2tGOH
ADCCLK
GAIN
OFFSET
Figure 1e.1-Channel SHA-Mode Clock Timing (for Blue and Green Channels)
CDSCLK1
tCRBtStH
STRTLN
tAD
(0V)
ANALOG
INPUTStGOH
ADCCLK
GAIN
OFFSET
Figure 1f.1-Channel SHA-Mode Clock Timing (Red Channel)
AD9807/AD9805
CDSCLK1
STRTLN
ANALOG
INPUTSR0
ADCCLK
GAIN
OFFSET
CDSCLK2
tGOS
tGOH
Figure 1g.CDS Clocks Digital Quiet Time
tDStDH
OEB
CSB
A0, A1, A2
WRB
MPU<7:0>
Figure 2.Write Timing
65432108X FULL SCALE
4X FULL SCALE
2X FULL SCALE
10-BIT GAIN, 10-BIT OFFSET
11-BIT GAIN, 9-BIT OFFSET
12-BIT GAIN, 8-BIT OFFSET
COLOR0
COLOR1
Figure 5.AD9807 Configuration Register Format
Configuration Register/AD9805
The Configuration Register controls three functions: a color
pointer, gain and offset pin configurations, and digital gain
scaling. Figure 6 shows the AD9805 Configuration Register.
Bits 0–2 control the digital scaling function. Setting a Bit
makes the corresponding condition true. Resetting Bits 0–2
disables and bypasses the digital multiplier. Bits 3–5 control
the gain and offset pin distribution. Resetting Bits 3–5 disables
and bypasses the digital subtracter and sets the gain word width
to 10. Setting any bit makes the corresponding condition true.
If Bit 3 is set, the 2 LSBs of the gain word become the 2 MSBs
of the offset word. If Bit 4 is set, the LSB of the gain word
becomes MSB of the offset word. Bits 6 and 7 direct register
data written to the MPU<7:0> bus to the appropriate red,
green or blue register.6543210
8X FULL SCALE
4X FULL SCALE
2X FULL SCALE
8-BIT GAIN, 10-BIT OFFSET
9-BIT GAIN, 9-BIT OFFSET
REGISTER OVERVIEW
MPU Port Map
Table II shows the MPU Port Map. The MPU Port Map is
accessed through pins A0, A1 and A2 of the AD9807/AD9805,
and provides the decoding scheme for the various registers of
the AD9807/AD9805. When writing or reading from any of the
registers, the appropriate bits must be applied to A0–A2.
Table II.MPU Port Map Format
Configuration Register/AD9807
The Configuration Register controls three functions: a color
pointer, gain and offset pin configurations, and digital gain
scaling. Figure 5 shows the AD9807 Configuration Register.
Bits 0–2 control the digital scaling function. Setting a bit makes
the corresponding condition true. Resetting Bits 0–2 disables
and bypasses the digital multiplier. Bits 3–5 control the gain
and offset pin distribution. Resetting Bits 3–5 disables and
bypasses the digital subtracter and sets the gain word width to
12. Setting any bit makes the corresponding condition true. For
example, if Bit 3 is set, the 2 LSBs of the gain word become the
2 MSBs of the offset word. If Bit 4 is set, the LSB of the gain
word becomes MSB of the offset word. Bits 6 and 7 direct
register data written to the MPU<7:0> bus to the appropriate
Figure 4.Block Diagram
CSB
RDB
WRB
VREFOFFSETGAIN
CDSCLK1CDSCLK2
VINR
VING
VINB
DOUT<11:0>/MPU<7:0>
STRTLNADCCLKOEB
AD9807/AD9805
Color Pointer
Both the AD9807 and the AD9805 use Bits 6 and 7 in the
Configuration Register to direct data to the corresponding
internal registers. Table III shows the mapping of Bits 6 and 7
to their corresponding color.
Table III. Color Pointer Map
Configuration Register 2
Configuration Register 2 controls several functions: color/black
and white selection, CDS enabling, A/D Reference Control
and Input Clamp Mode. Figure 7 shows the AD9807 and
AD9805 Configuration Register 2 format. Setting Bit 0 enables
the three internal CDS blocks of the AD9807/AD9805. Reset-
ting Bit 0 disables the internal CDS blocks, configuring the part
for SHA operation. Setting Bit 1 places the AD9807/AD9805 in
single-channel (black & white) mode. In this mode, only one of
the three input channels is used. The color bits in the configu-
ration register at the time of the last write indicate the particular
channel used. Resetting Bit 1 places the AD9807/AD9805 in
color mode and all three input channels are enabled. Bits 2-4
control the full-scale input span of the A/D. Setting Bit 2 results in
a 4 V p-p input span. Setting Bit 3 results in a 2 V p-p full-scale
input span. Setting Bit 4 results in a full-scale span set by an
external reference connected to the VREF pin of the AD9807/
AD9805 (Full Scale = 2 × VREF). Resetting Bits 2, 3 or 4
disables that particular mode. Bits 6 and 7 select the desired
clamp mode (see Figure 17). Table IV shows the truth table
for clamp mode functionality. Line clamp mode allows control
of the input switch (S1) via CDSCLK1 only while STRTLN is
reset. Pixel clamp mode allows control of the input switch (S1)
via CDSCLK1 regardless of the state of STRTLN. No clamp
mode disables the input switch (S1) regardless of the selected
mode of CDS operation.
Table IV.Clamp Mode Truth Table6543210
CDSEN
BLACK & WHITE
ADC FULL SCALE = 4V
ADC FULL SCALE = 2V
EXTERNAL REFERENCE
SET TO 0
Input Offset Registers
The Input Offset Registers control the amount of analog offset
applied to the analog inputs prior to the PGA portion of the
AD9807/AD9805; there is one Input Offset Register for each
color. Figure 8 shows the Input Offset Register format. The
offset range may be varied between –80 mV and 20 mV. The
data format for the Input Offset Registers is straight binary
coding. An all “zeros” data word corresponds to –80 mV. An
all “ones” data word corresponds to 20 mV. The offset is
variable in 256 steps. The contents of the color pointer in the
Configuration Register at the time an Input Offset Register is
written indicates the color for which that offset setting applies.6543210
ANALOG OFFSET (LSB)
ANALOG OFFSET
ANALOG OFFSET
ANALOG OFFSET
ANALOG OFFSET
ANALOG OFFSET
ANALOG OFFSET
ANALOG OFFSET (MSB)
Figure 8.Input Offset Registers Format
PGA Gain Registers
Bits 0–3 of the PGA Gain Registers control the amount of gain
applied to the analog inputs prior to the A/D conversion
portion of the AD9807/AD9805; there is one PGA Gain
Register for each channel. Figure 9 shows the PGA Gain Register
format. The gain range may be varied between 1 and 4. The
data format for the PGA Gain Registers is straight binary
coding. An all “zeros” data word corresponds to an analog
gain of 1. An all “ones” data word corresponds to an analog
gain of 4. The gain is variable in 16 steps (see Figure 16).
The contents of the color pointer in the Configuration
Register at the time a PGA Gain Register is written indicates
the color for which that gain setting applies. Bits 4–7 of the PGA
Gain Registers are reserved.6543210
PGA0
PGA1
PGA2
PGA3
RESERVED
RESERVED
RESERVED
RESERVED
Figure 9.PGA Gain Registers Format
Odd, Even Offset Registers
The Odd and Even Offset Registers provide a means of digitally
compensating the odd and even offset error (Register Imbal-
ance) typical of multiplexed CCD imagers; there is one Odd
