AD9803JST Fast Delivery |IC PHOENIX CO.,LIMITED

AD9803JST ,CCD Signal Processor For Electronic CamerasSPECIFICATIONS (T to T , ACVDD = ADVDD = DVDD = +2.8 V, f = 18 MHz unless otherwise noted)MIN MAX A ..
AD9804AJST ,Complete 10-Bit, 18 MHz CCD Signal ProcessorSPECIFICATIONS L CLKParameter Symbol Min Typ Max UnitSAMPLE CLOCKSDATACLK, SHP, SHD Clock Period t ..
AD9804JST ,Complete 10-Bit 18 MSPS CCD Signal ProcessorSPECIFICATIONSMIN MAX DATACLK SHP SHD Parameter Min Typ Max UnitTEMPERATURE RANGEOperating –20 +85 ..
AD9805JS ,Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal ProcessorsSPECIFICATIONSPGA Gain = 1 unless otherwise noted)Parameter Min Typ Max UnitsRESOLUTION 12 BitsCON ..
AD9806KST ,Complete 10-Bit 18 MSPS CCD Signal ProcessorSPECIFICATIONS (T to T , AVDD = DVDD = 3.0 V, f = 18 MHz, unless otherwise noted.)MIN MAX ADCCLKPar ..
AD9806KSTRL ,Complete 10-Bit 18 MSPS CCD Signal ProcessorSPECIFICATIONS(T to T , AVDD = DVDD = 3.0 V, f = f = f = 18 MHz, unless otherwise noted.)MIN MAX AD ..
ADS8517IPWR ,Low Power 16-Bit, 200kSPS, +/-10V Bipolar Input SAR ADC with S/P Interface 28-TSSOP -40 to 85.(1)(2)ABSOLUTE
ADS8519IB , 16-Bit, 250kSPS, Serial, CMOS, Sampling ANALOG-TO-DIGITAL CONVERTER
ADS8519IBDB ,16-Bit 250kHz CMOS Analog-to-Digital Converter w/Serial Interface 4.096V Internal Reference 28-SSOP -40 to 85This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated cir ..
ADS8519IBDBG4 ,16-Bit 250kHz CMOS Analog-to-Digital Converter w/Serial Interface 4.096V Internal Reference 28-SSOP -40 to 85FEATURES DESCRIPTION23• 0V to 8.192V, ±5V, and ±10V Input RangesThe ADS8519 is a complete 16-bit sa ..
ADS8519IDB ,16-Bit 250kHz CMOS Analog-to-Digital Converter w/Serial Interface 4.096V Internal Reference 28-SSOP -40 to 85MAXIMUM RATINGSOver operating free-air temperature range (unless otherwise noted).UNITR1 ±25VINR2 ± ..
ADS8519IDBG4 , 16-Bit, 250kSPS, Serial, CMOS, Sampling ANALOG-TO-DIGITAL CONVERTER

AD9803JST
CCD Signal Processor For Electronic Cameras
REV.0
CCD Signal Processor
for Electronic Cameras
FUNCTIONAL BLOCK DIAGRAM
PBLKPGACONT1-2CLPOB
3-W INTFADCINAUXINACLPSHPSHDADCCLK
DOUT
AUXCONT
VRT
VRB
CCDIN
DAC1
DAC2
CLPDM
FEATURES
3-Wire Serial I/F for Digital Control
18 MHz Correlated Double Sampler
Low Noise PGA with 0 dB–30 dB Range
Analog Pre-Blanking Function
AUX Input with Input Clamp and PGA
10-Bit 18 MSPS A/D Converter
Direct ADC Input with Input Clamp
Internal Voltage Reference
Two Auxiliary 8-Bit DACs
+3 V Single Supply Operation
Low Power: 150 mW at 2.7 V Supply
48-Lead LQFP Package
PRODUCT DESCRIPTION
The AD9803 is a complete CCD and video signal processor
developed for electronic cameras. It is well suited for video
camera and still-camera applications.
The 18 MHz CCD signal processing chain consists of a CDS,
low noise PGA, and 10-bit ADC. Required clamping circuitry
and a voltage reference are also provided. The AUX input
features a wideband PGA and input clamp, and can be used to
sample analog video signals.
The AD9803 nominally operates from a single 3 V power sup-
ply, typically dissipating 170 mW. The AD9803 is packaged in a
space-saving 48-lead LQFP and is specified over an operating
temperature range of –20°C to +70°C.
AD9803–SPECIFICATIONS
GENERAL SPECIFICATIONS
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
(TMIN to TMAX, ACVDD = ADVDD = DVDD = +2.8 V, fADCCLK = 18 MHz unless otherwise noted)
(TMIN to TMAX, DRVDD = +2.7 V, CL = 20 pF unless otherwise noted)
AD9803
CCD-MODE SPECIFICATIONS
PGA
BLACK-LEVEL CLAMP
TIMING SPECIFICATIONS
NOTESInput Signal Characteristics defined as shown:
650mV MAX
OPTICAL BLACK PIXEL
500mV TYP
RESET TRANSIENT
1V MAX
INPUT SIGNAL
RANGE
2V MAX
INPUT SIGNAL
W/PBLK
ENABLEDEven-Odd Offset is described under the Theory of Operation section. The Even-Odd Offset is measured with the Even-Off Offset correction enabled.SNR = 20 log10 (Full-Scale Voltage/RMS Output Noise).20 pF loading; timing shown in Figure 1.Internal aperture delay for actual sampling edge.
(TMIN to TMAX, ACVDD = ADVDD = DVDD = +2.8 V, fSHP = fSHD = fADCCLK = 18 MHz unless otherwise
noted)
AD9803–SPECIFICATIONS
AUX-MODE SPECIFICATIONS
ACTIVE CLAMP (CLAMP ON)
TIMING SPECIFICATIONS
NOTES20 pF loading; timing shown in Figure 2.
Specifications subject to change without notice.
ADC-MODE SPECIFICATIONS
Specifications subject to change without notice.
DAC SPECIFICATIONS (DAC1 and DAC2)
Specifications subject to change without notice.
(TMIN to TMAX, ACVDD = ADVDD = DVDD = +2.8 V, fADCCLK = 18 MHz unless otherwise noted)
(TMIN to TMAX, ACVDD = ADVDD = DVDD = +2.8 V, fADCCLK = 18 MHz unless otherwise noted)
TIMING SPECIFICATIONSN+2N+3N+4
ADCCLK RISING EDGE PLACEMENT
CCD
SHP
SHD
ADCCLK
D0–D9
NOTES:
1. SHP AND SHD SHOULD BE OPTIMALLY ALIGNED WITH THE CCD SIGNAL. SAMPLES ARE TAKEN AT THE RISING EDGES.
2. ADCCLK RISING EDGE MUST OCCUR AT LEAST 15ns AFTER THE RISING EDGE OF SHP (tINHIBIT).
3. RECOMMENDED PLACEMENT FOR ADCCLK RISING EDGE IS BETWEEN THE RISING EDGE OF SHD AND FALLING EDGE OF SHP.
4. OUTPUT LATENCY (7 CYCLES) SHOWN WITH EVEN-ODD OFFSET CORRECTION ENABLED.
5. ACTIVE LOW CLOCK PULSE MODE IS SHOWN.
Figure 1.CCD-MODE Timing
tHOLDN+1
N+2
N+3
N+4
N+5
VIDEO
INPUT
ADCCLK
D0–D9
NOTE:
EXAMPLE OF OUTPUT DATA LATCHED BY ADCCLK RISING EDGE.
Figure 2.AUX-MODE and ADC-MODE Timing
Figure 3.CCD-MODE Clamp Timing
AD9803
ORDERING GUIDE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9803 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TIMING SPECIFICATIONS (CONTINUED)
MANUAL CLAMPING
AUTOMATIC CLAMPING
VIDEO
SIGNAL
ACLP
Figure 4.AUX-MODE Clamp Timing
NOTE: ACLP can be used two different ways. To control the
exact time of the clamp, an active low pulse is used to specify
the clamp interval. Alternatively, ACLP may be tied to ground.
In this configuration, the clamp circuitry will sense the most
negative portion of the signal and use this level to set the clamp
voltage. For the video waveform in Figure 4, the SYNC level
will be clamped to the black level specified in the E-Register.
Active low clamp pulse mode is shown.
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device
at these or other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods
may affect device reliability.
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
DVDD
DVSSACLP
ADCCLK
STBY
(LSB) D0
(MSB) D9
DRVDD
PBLK
CLPOB
SHPSHD
ADCIN
AUXCONT
AUXIN
ACVDD
CLPBYP
ACVSS
PGACONT2
PGACONT1
CCDBYP1
PIN
DIN
CCDBYP2
VRTVRBSUBSTADVSSSDATAADVDDSCKSLDAC2DAC1VTRBYPCMLEVEL
CLPDM
DRVSS
NC = NO CONNECT
AD9803
EQUIVALENT INPUT CIRCUITS
DVDDDRVDD
DVSSDRVSS
Figure 5.Pins 2–11 (D0–D9)
DVDD
DVSS
DVSS
Figure 6.Pin 16, 21, 22 (ADCCLK, SHP, SHD)
Figure 7.Pins 25, 28 (CCDBYP)
ACVDD
SUBST
ACVSS
10pF
Figure 8.Pin 26 (DIN) and Pin 27 (PIN)
ACVDD
SUBST
PGACONT1
PGACONT2
Figure 9.Pin 29 (PGACONT1) and Pin 30 (PGACONT2)
ACVDD
SUBSTACVSS
Figure 10.Pin 32 (CLPBYP)
ACVDD
SUBST
ACVSS
Figure 11.Pin 34 (AUXIN) and Pin 36 (ADCIN)
ACVDD
SUBSTCMLEVEL
Figure 12.Pin 35 (AUXCONT)
Figure 13.Pin 37 (CMLEVEL)
Figure 14.Pin 39 (DAC1) and 40 (DAC2)
Figure 15.Pin 44 (SDATA)
Figure 16.Pin 47 (VRB) and Pin 48 (VRT)
AD9803
–Typical Performance Characteristics

SAMPLE RATE – MHz
POWER DISSIPATION – mV
120681012141618
Figure 17.CCD-MODE Power vs. Clock Rate
TITLE
TITLE
–0.61503004506007509001023
Figure 18.CCD-MODE DNL at 18 MHz

1503004506007509001023
Figure 19.CCD-MODE INL at 18 MHz

DIGITAL OUTPUT CODE – Decimal
NUMBER OF HITS
100000313233343536373839
Figure 20.CCD-MODE Grounded-Input Noise
(PGA Gain = MIN)
FREQUENCY – MHz3456789
–60
Figure 21.AUX-MODE THD at 18 MHz
(fIN = 3.54 MHz at –3 dB)
FREQUENCY – MHz3456789
–60
Figure 22.ADC-MODE at 18 MHz
(fIN = 3.54 MHz at –3 dB)

Partno	Mfg	Dc	Qty	Available	Descript
AD9803JST	ADI	N/a	450	avai	CCD Signal Processor For Electronic Cameras