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ADS850Y/250 ,14-Bit, 10 MSPS ADC SE/Diff Input, Int/Ext Ref., Self CalibratingSBAS154CPIN CONFIGURATIONTop View TQFP48 47 46 45 44 43 42 41 40 39 38 37+V 1 36 +VS S+V 2 35 GNDS+ ..
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AD9786BSV
16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2?4?8?Interpolation and Signal Processing
16-Bit, 200 MSPS/500 MSPS TxDAC+® with
2×/4×/8× Interpolation and Signal Processing
Rev. 0
FEATURES
16-bit resolution, 200 MSPS input data rate
IMD 90 dBc @10 MHz
Noise spectral density (NSD) −164 dBm/Hz @ 10 MHz
WCDMA ACLR = 80 dBc @ 40 MHz IF
DNL = ±0.3 LSB
INL = ±0.6 LSB
Selectable 2×/4×/8× interpolation filters
Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes
Single or dual channel signal processing
Selectable image rejection Hilbert transform
Flexible calibration engine
Direct IF transmission features
Serial control interface
Versatile clock and data interface
3.3 V compatible digital interface
On-chip 1.2 V reference
80-lead thermally enhanced TQFP package
APPLICATIONS
Base stations: Multicarrier WCDMA, GSM/EDGE, TD-SCDMA,
IS136, TETRA
Instrumentation: RF Signal Generators, Arbitrary Waveform
Generators
HDTV Transmitters
Broadband Wireless Systems
Digital Radio Links
Satellite Systems
PRODUCT DESCRIPTION The AD9786 is a 16-bit, high speed, CMOS DAC with 2×/4×/8×
interpolation and signal processing features tuned for com-
munications applications. It offers state-of-the-art distortion
and noise performance. The AD9786 was developed to meet the
demanding performance requirements of multicarrier and third
generation base stations. The selectable interpolation filters
simplify interfacing to a variety of input data rates while also
taking advantage of oversampling performance gains. The
modulation modes allow convenient bandwidth placement and
selectable sideband suppression.
The flexible clock interface accepts a variety of input types such
as 1 V p-p sine wave, CMOS, and LVPECL in single-ended or
differential mode. Internal dividers generate the required data
rate interface clocks.
The AD9786 provides a differential current output, supporting
single-ended or differential applications; it provides a nominal
full-scale current from 10 mA to 20 mA. The AD9786 is
manufactured on an advanced low cost 0.25 µm CMOS process.
FUNCTIONAL BLOCK DIAGRAM CLK+
CLK–
DATACLK
P2B[15:0]
P1B[15:0]
FSADJ
REFIO
IOUTA
IOUTB
SDIO
SDO
CSB
SCLK
RESETFigure 1.
TABLE OF CONTENTSProduct Highlights...........................................................................3
Specifications.....................................................................................4
DC Specifications.........................................................................4
Dynamic Specifications...............................................................5
Digital Specifications...................................................................6
Absolute Maximum Ratings.......................................................6
Thermal Characteristics..............................................................7
ESD Caution..................................................................................7
Pin Configuration and Function Descriptions.............................8
Clock..............................................................................................8
Analog............................................................................................9
Data................................................................................................9
Serial Interface............................................................................10
Definition of Specifications...........................................................11
Typical Performance Characteristics...........................................13
Serial Control Interface..................................................................19
General Operation of the Serial Interface...............................19
Serial Interface Port Pin Descriptions.....................................19
MSB/LSB Transfers.....................................................................20
Notes on Serial Port Operation................................................20
Mode Control (via SERIAL Port).................................................21
Digital Filter Specifications...........................................................25
Digital Interpolation Filter Coefficients..................................25
AD9786 Clock/Data Timing.....................................................26
Real and Complex Signals.........................................................33
Modulation Modes.....................................................................34
Power Dissipation......................................................................39
Hilbert Transform Implementation.........................................41
Operating the AD9786 Rev F Evaluation Board........................45
Power Supplies............................................................................45
PECL Clock Driver....................................................................45
Data Inputs..................................................................................46
Serial Port....................................................................................46
Analog Output............................................................................47
Outline Dimensions.......................................................................60
Ordering Guide..........................................................................61
REVISION HISTORY
7/04—Revision 0: Initial Version
PRODUCT HIGHLIGHTS 1. The AD9786 is a 16-bit high speed interpolating
TxDAC+.
2. 2×/4×/8× user selectable interpolating filter eases data
rate and output signal reconstruction filter requirements.
3. 200 MSPS input data rate.
4. Ultra high speed 500 MSPS DAC conversion rate.
5. Flexible clock with single-ended or differential input:
CMOS, 1 V p-p sine wave, and LVPECL capability.
6. Complete CMOS DAC function operates from a 3.1 V to
3.5 V single analog (AVDD) supply, 2.5 V (DVDD)
digital supply, and a 2.5 to 3.3V DRVDD supply. The
DAC full-scale current can be reduced for lower power
operation, and a sleep mode is provided for low power
idle periods.
7. On-chip voltage reference: The AD9786 includes a
1.20 V temperature-compensated band gap voltage
reference.
8. Multichip synchronization: Multiple AD9786 DACs can
be synchronized to a single master AD9786 to ease
timing design requirements and optimize image reject
transmit performance.
SPECIFICATIONS
DC SPECIFICATIONS TMIN to TMAX, AVDD1, AVDD2 = 3.3 V, ACVDD, ADVDD, CLKVDD, DVDD, DRVDD = 2.5 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1. 1 Measured at IOUTA driving a virtual ground. Nominal full-scale current, IOUTFS, is 32× the IREF current.
3 Use an external amplifier to drive any external load. Measured under the following conditions: fDATA = 125 MSPS, fDAC = 500 MSPS, 4× interpolation, fDAC/4 modulation, Hilbert Off.
DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD1, AVDD2 = 3.3 V, ACVDD, ADVDD, CLKVDD, DVDD, DRVDD = 2.5 V, IOUTFS = 20 mA, differential transformer
coupled output, 50 Ω doubly terminated, unless otherwise noted.
Table 2. Propagation delay is delay from CLK input to DAC update.
2 Measured doubly terminated into 50 Ω load.
