AD9774AS ,14-Bit, 32 MSPS TxDAC⑩ with 4x Interpolation FiltersSPECIFICATIONS (T to T , AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, I = 20 mA, unless otherwise noted ..
AD9775 ,14-Bit, 160 MSPS 2x/4x/8x Interpolating Dual TxDAC+?D/A Converterfeatures the ability to perform f /2, f /4, and f /8S S S2. Direct IF transmission capability for 7 ..
AD9775BSV ,14-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converterfeatures the ability to perform f /2, f /4, and f /8S S S2. Direct IF transmission capability for 7 ..
AD9776ABSVZ , Dual, 12-/14-/16-Bit,1 GSPS
AD9777BSV ,16-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converterfeatures the ability to perform f /2, f /4, and f /8S S S2. Direct IF transmission is possible for ..
AD9777BSVRL , 16-Bit, 160 MSPS 2x/4x/8x Interpolating Dual TxDAC D/A Converter
ADS8412IBPFBR ,16 Bit 2MSPS Parallel ADC W/Ref, Pseudo Bipolar Fully Differential InputFEATURES APPLICATIONS• DWDM• 2-MHz Sample Rate• Instrumentation• 16-Bit NMC Ensured Over Temperatur ..
ADS8412IBPFBT ,16 Bit 2MSPS Parallel ADC W/Ref, Pseudo Bipolar Fully Differential InputSLAS384A–JUNE 2003–REVISED DECEMBER 2004SPECIFICATIONST = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 ..
ADS8413IBRGZT ,16-bit, Unipolar Diff Input, 2MSPS Sampling rate, 4.75V to 5.25V ADC with LVDS Serial Interface 48-VQFN -40 to 85FEATURES APPLICATIONS• Medical Instrumentation• 2-MHz Sample Rate• HIgh-Speed Data Acquisiton Syste ..
ADS8413IRGZRG4 ,16-bit, Unipolar Diff Input, 2MSPS Sampling rate, 4.75V to 5.25V ADC with LVDS Serial Interface 48-VQFN -40 to 85SLAS490–OCTOBER 2005+ VA AGND + VBD BDGNDCore Supply I/O SupplySARCSTARTSYNC_O, CLK_O, SDOLVDS I/OS ..
ADS8413IRGZT ,16-bit, Unipolar Diff Input, 2MSPS Sampling rate, 4.75V to 5.25V ADC with LVDS Serial Interface 48-VQFN -40 to 85SLAS490–OCTOBER 2005SPECIFICATIONST = –40°C to 85°C, +VA = 5 V,+VBD = 5 V or 3.3 V, V = 4.096 V, f ..
ADS8422IPFBT ,16 Bit 4MSPS Parallel ADC W/Ref, Pseudo Bipolar, Fully Differential Input 48-TQFP -40 to 85FEATURES APPLICATIONS• DWDM• Fully Differential Input with Pseudo-BipolarInput Range -4 V to +4 V • ..
AD9774AS
14-Bit, 32 MSPS TxDAC⑩ with 4x Interpolation Filters
REV. B
14-Bit, 32 MSPS TxDAC+™
with 43 Interpolation Filters
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTIONThe AD9774 is a single supply, oversampling, 14-bit digital-to-
analog converter (DAC) optimized for waveform reconstruction
applications requiring exceptional dynamic range. Manufac-
tured on an advanced CMOS process, it integrates a complete,
low distortion 14-bit DAC with a 4· digital interpolation filter
and clock multiplier. The two-stage, 4· digital interpolation
filter provides more than a six-fold reduction in the complexity
of the analog reconstruction-filter. It does so by multiplying the
input data rate by a factor of four while simultaneously suppressing
the original inband images by more than 69 dB. The on-chip
clock multiplier provides all the necessary clocks. The AD9774
can reconstruct full-scale waveforms having bandwidths as high
as 13.5 MHz when operating at an input data rate of 32 MSPS
and a DAC output rate of 128 MSPS.
The 14-bit DAC provides differential current outputs to support
differential or single-ended applications. A segmented current
source architecture is combined with a proprietary switching tech-
nique to reduce spurious components and enhance dynamic per-
formance. Matching between the two current outputs ensures
enhanced dynamic performance in a differential output configura-
tion. The differential current outputs may be fed into a transformer
or tied directly to an output resistor to provide two complementary,
single-ended voltage outputs. A differential op amp topology can
also be used to obtain a single-ended output voltage. The output
voltage compliance range is nominally 1.25 V.
Edge-triggered input latches, a 4· clock multiplier, and a tem-
perature compensated bandgap reference have also been inte-
grated to provide a complete monolithic DAC solution. Flexible
supply options support +3 V and +5 V CMOS logic families.
TTL logic levels can also be accommodated by reducing the
AD9774 digital supply.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9774 can be driven
by the on-chip reference or by a variety of external reference
voltages. The full-scale current of the AD9774 can be adjusted
over a 2mA to 20 mA range, thus providing additional gain
ranging capabilities.
The AD9774 is available in a 44-lead MQFP package. It is
specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTSOn-Chip 4· interpolation filter eases analog reconstruction
filter requirements by suppressing the first three images by 69dB.Low glitch and fast settling time provide outstanding dynamic
performance for waveform reconstruction or digital synthesis
requirements, including communications.On-chip, edge-triggered input CMOS latches interface readily
to CMOS and TTL logic families. The AD9774 can support
input data rates up to 32 MSPS.A temperature compensated, 1.20 V bandgap reference is
included on-chip, providing a complete DAC solution. An
external reference may also be used.The current output(s) of the AD9774 can easily be configured
for various single-ended or differential circuit topologies.On-chip clock multiplier generates all the high-speed clocks
required by the internal interpolation filters. Both 2· and 4·
clocks are generated from the lower rate data clock supplied
by the user.
TxDAC+ is a trademark of Analog Devices, Inc.
FEATURES
Single 3 V or 5 V Supply
14-Bit DAC Resolution and Input Data Width
32 MSPS Input Data Rate at 5V
13.5 MHz Reconstruction Bandwidth
12 ENOBS @ 1 MHz
77 dBc SFDR @ 5 MHz
43 Interpolation Filter
69 dB Image Rejection
84% Passband to Nyquist Ratio
0.002dB Passband Ripple
23 3/4 Cycle Latency
Internal 43 Clock Multiplier
On-Chip 1.20V Reference
44-Lead MQFP Package
APPLICATIONS
Communication Transmit Channel:
Wireless Basestations
ADSL/HFC Modems
Direct Digital Synthesis (DDS)
AD9774–SPECIFICATIONS
DC SPECIFICATIONSTMIN to TMAX
Monotonicity (12-Bit)GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE
TEMPERATURE COEFFICIENTS
NOTESMeasured at IOUTA driving a virtual ground.Nominal full-scale current, IOUTFS, is 32 · the IREF current.Use an external amplifier to drive any external load.For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.
(TMIN to TMAX, AVDD = +5 V, PLLVDD = +5 V, DVDD = +5V, IOUTFS = 20 mA, unless otherwise noted)
AD9774
DYNAMIC SPECIFICATIONSNOTESPropagation delay is delay from data input to DAC update.Measured single-ended into 50W load.
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Differential Transformer
Coupled Output, 50 V Doubly Terminated, unless otherwise noted)
DIGITAL SPECIFICATIONS
(TMIN to TMAX, AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA unless otherwise noted)
AD9774–SPECIFICATIONS
DIGITAL FILTER SPECIFICATIONSIMPULSE RESPONSE DURATION
NOTESExcludes sinx/x characteristic of DAC.Defined as the number of data clock cycles between impulse input and peak of output response.
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = +2.7 V to +5.5 V, DVDD = +2.7 V to +5.5 V, IOUTFS = 20 mA unless
otherwise noted)
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE*S = Metric Quad Flatpack.
THERMAL CHARACTERISTIC
Thermal Resistance44-Lead MQFPJA = 53.2°C/WJC = 19°C/W
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Table I.Integer Filter Coefficients for First Stage Interpola-
tion Filter (55-Tap Halfband FIR Filter)
Table II.Integer Filter Coefficients for Second Stage Inter-
polation Filter (23-Tap Halfband FIR Filter)
FREQUENCY – DC TO 23 fCLOCK
OUTPUT – dBFS
1.01.52.0Figure 2a.FIR Filter Frequency Response
Figure 2b.FIR Filter Impulse Response
AD9774
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
REFCOMP
FSADJ
REFIO
REFLO
UNUSED
PLLENABLE
PLLCOM
DCOM
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
PLLVDD
LPF
VCO IN/EXT
PLLDIVIDE
IOUTB
ACOM
DCOMSNOOZEDVDDIOUTAAVDDDCOMSLEEPICOMPNC
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)Linearity error is defined as the maximum deviation of the actual
analog output from the ideal output, determined by a straight
line drawn from zero to full scale.
Differential Nonlinearity (or DNL)DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
MonotonicityA D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset ErrorThe deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain ErrorThe difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s, minus the output when all inputs are set to 0s.
Output Compliance RangeThe range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature DriftTemperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is re-
ported in ppm per degree C.
Power Supply RejectionThe maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling TimeThe time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch ImpulseAsymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified the net area of the glitch in pV-s.
Spurious-Free Dynamic RangeThe difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic DistortionTHD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Signal-to-Noise Ratio (SNR)S/N is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
PassbandFrequency band in which any input applied therein passes
unattenuated to the DAC output.
Stopband RejectionThe amount of attenuation of a frequency outside the passband
applied to the DAC, relative to a full-scale signal applied at the
DAC input within the passband.
Group DelayNumber of input clocks between an impulse applied at the
device input and peak DAC output current.
Impulse ResponseResponse of the device to an impulse applied to the input.
50V
20pF
+3VD
+3VD
+5VA
10dB – DIV
“INBAND”
MHz Figure 4.Single Tone Spectral Plot
@ 32 MSPS w/fOUT = 12.8 MHz (DC to
4 · CLKIN)
10dB – DIV
“INBAND”
MHz Figure 7.Single Tone Spectral Plot
@ 16 MSPS w/fOUT = 6.4 MHz (DC to
4 · CLKIN)
10dB – DIV
MHz Figure 10.Single Tone Spectral Plot
AD9774
Typical AC Characterization Curves
(AVDD = +5 V, PLLVDD = +3 V, DVDD = +3 V, IOUTFS = 20 mA, 50 V Doubly Terminated Load, Differential Output, TA = +258C, unless otherwise
noted. Note: PLLVDD = +5 V and DVDD = +5 V for Figures 4, 5 and 6.)
fOUT – MHz
SFDR – dBc02144681012Figure 5.“Inband” SFDR vs. fOUT
@ 32 MSPS (DC to CLKIN/2)
fOUT – MHz
SFDR – dBc01723456 Figure 8.“Inband” SFDR vs. fOUT
@ 16 MSPS (DC to CLKIN/2)
fOUT – MHz
SFDR – dBc00.53.511.522.53 Figure 11.“Inband” SFDR vs. fOUT
fOUT – MHz
SFDR – dBc02144681012Figure 6.“Out-of-Band” SFDR vs. fOUT
@ 32 MSPS (CLKIN/2 to 3 1/2 CLKIN)
fOUT – MHz
SFDR – dBc01723456Figure 9.“Out-of-Band” SFDR vs.
fOUT @ 16 MSPS (CLKIN/2 to 3 1/2
CLKIN)
fOUT – MHz
SFDR – dBc00.53.511.522.53Figure 12.“Out-of-Band” SFDR vs.
10dB – DIV
MHzFigure 13.Single Tone Spectral Plot
@ 2 MSPS w/fOUT = 800 kHz (DC to
4 · CLKIN)
AIN – dBFS
SFDR – dBc
–18–160–14–12–10–6–4–2–8Figure 16.“In-Band” Single Tone
SFDR vs. AIN @ fOUT = fCLOCK/7
(DC to CLKIN/2)
AOUT – dBFS
SFDR – dBc
–18–160–14–12–10–6–4–2–8Figure 19.“In-Band” Two Tone
SFDR vs. AOUT @ fOUT = fCLOCK/2.7
(DC to CLKIN/2)
fOUT – MHz
SFDR – dBc
0.10.20.80.30.40.50.60.7 Figure 14.“Inband” SFDR vs. fOUT
@ 2 MSPS (DC to CLKIN/2)
AIN – dBFS
SFDR – dBc
–18–160–14–12–10–6–4–2–8Figure 17.Out-of-Band Single Tone
SFDR vs. AIN @ fOUT = fCLOCK/7
(DC to 3 1/2 CLKIN)
AOUT – dBFS
SFDR – dBc
–18–160–14–12–10–6–4–2–8Figure 20. “Out-of-Band” Two Tone
SFDR vs. AOUT @ fOUT = fCLOCK/2.7
(DC to 3 1/2 CLKIN)
fOUT – MHz
SFDR – dBc00.20.80.30.40.50.60.7 Figure 15.“Out-of-Band” SFDR
vs. fOUT @ 2 MSPS (CLKIN/2 to
3 1/2 CLKIN)
fCLK – MSPS
SNR – dB102030Figure 18.SNR vs. fCLKIN @ fOUT =
2 MHz (DC to CLKIN/2)
10dB – DIV
–40Figure 21.Multitone Spectral Plot
@ 32MSPS (DC to 4 · CLKIN)
AD9774
FUNCTIONAL DESCRIPTIONFigure 22 shows a simplified block diagram of the AD9774. The
AD9774 is a complete, 4· oversampling, 14-bit DAC that in-
cludes two cascaded 2· interpolation filters, a phase-locked loop
(PLL) clock multiplier, and a 1.20 Volt bandgap voltage refer-
ence. The 14-bit DAC provides two complementary current
outputs whose full-scale current is determined by an external
resistor. Input data that is latched into the edge-triggered input
latches is first interpolated by a factor of four by the interpolation
filters before updating the 14-bit DAC. A PLL clock multiplier
produces the necessary internally synchronized 1·, 2· and 4·
clocks from an external reference. The AD9774 can support
input data rates as high as 32 MSPS, corresponding to a DAC
update rate of 128 MSPS.
The analog and digital sections of the AD9774 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
over a 2.7 V to 5.5 V range. A separate supply input (i.e.,
PLLVDD) having a similar operating range is also provided for
the PLL clock multiplier. To maintain optimum noise and dis-
tortion performance, PLLVDD should be maintained at the
same voltage level as DVDD.
VCO
IN/EXT
PLL
DIVIDE
PLLCOM
REFIOSNOOZE
IOUTA
FSADJ
SLEEP
DCOMDVDDICOMPACOMAVDD
PLL
ENABLEPLLLOCKCLK43IN
PLLVDD
LPF
IOUTB
DATAINPUTS
(DB13–DB0)
CLK IN/OUT
REFCOMPREFLOFigure 22.Functional Block Diagram
Preceding the 14-bit DAC are two cascaded 2· digital interpola-
tion filter stages based on a 55- and 23-tap halfband symmetric
FIR topology. Edge triggered latches are used to latch the input
data on the rising edge of CLK IN/OUT. The composite fre-
quency and impulse response of both filters are shown in Fig-
ures 2a and 2b. Table I and Table II list the idealized filter
coefficients for each of the filter stages. The interpolation filters
essentially multiply the input data rate to the DAC by a factor of
four relative to its original input data rate while simultaneously
reducing the magnitude of the images associated with the origi-
nal input data rate.
The benefits of an interpolation filter are clearly seen in Figure
23, which shows an example of the frequency and time domain
representation of a discrete time sine wave signal before and
after it is applied to a digital interpolation filter. Images of the
sine wave signal appear around multiples of the DAC’s input
data rate as predicted by sampling theory. These undesirable
images will also appear at the output of a reconstruction DAC,
although modified by the DAC’s sin(x)/(x) roll-off response.
In many bandlimited applications, these images must be sup-
pressed by an analog filter following the DAC. The complexity
of this analog filter is typically determined by the proximity of
the desired fundamental to the first image and the required
amount of image suppression. Adding to the complexity of this
analog filter may be the requirement of compensating for the
DAC’s sin(x)/x response.
Referring to Figure 23, the “new” first image associated with the
DAC’s higher data rate after interpolation is “pushed” out fur-
ther relative to the input signal. The “old” first image associated
with the lower DAC data rate before interpolation is suppressed
by the digital filter. As a result, the transition band for the ana-
log reconstruction filter is increased, thus reducing the complex-
ity of the analog filter. Furthermore, the sin(x)/x roll-off over the
effective passband (i.e., dc to fCLOCK/2) is significantly reduced.
The AD9774 includes a PLL clock multiplier that produces the
necessary internally synchronized 1·, 2· and 4· clocks for the
edge triggered latches, interpolation filters and DACs. The
PLL clock multiplier typically accepts an input data clock,
CLK IN/OUT, as its reference source. Alternatively, it can also
be configured using an external 4· clock via CLK4·IN. The
PLLDIVIDE, VCO IN/EXT, PLLENABLE, and PLLLOCK
are control inputs/outputs used in the PLL clock generator.
Refer to the PLL CLOCK MULTIPLIER OPERATION sec-
tion for a detailed discussion on its operation.
The digital section of the AD9774 also includes several other
control inputs and outputs. The SLEEP and SNOOZE inputs
provide different power-saving modes as discussed in the
SLEEP and SNOOZE section.
FUNDAMENTAL
4fCLOCK2fCLOCK
FREQUENCY DOMAIN
4fCLOCK
2fCLOCK
FUNDAMENTAL
SUPPRESSED
"OLD"
1ST IMAGE
4fCLOCK2fCLOCK
fCLOCK
TIME DOMAIN
1ST IMAGE
PLL CLOCK MULTIPLIER OPERATIONThe Phase Lock Loop (PLL) Clock Multiplier is intrinsic to the
operation of the AD9774 in that it produces the necessary inter-
nally synchronized 1·, 2· and 4· clocks for the edge triggered
latches, interpolation filters and DACs. Figure 24 shows a func-
tional block diagram of the PLL Clock Multiplier, which con-
sists of a phase detector, a charge pump, a voltage controlled
oscillator (VCO), a divide-by-N circuit and some control inputs/
outputs. It produces the required internal clocks for the AD9774
by using one of two possible externally applied reference clock
sources applied to either CLKIN or CLK4·IN. PLLENABLE
and VCO IN/EXT are active HIGH control inputs used to
enable the charge pump and VCO respectively.
To maintain optimum noise and distortion performance,
PLLVDD and DVDD should be set to similar voltage levels. If
a separate supply cannot be provided for PLLVDD, PLLVDD
can be tied to DVDD using an LC filter network similar to that
shown in Figure 41.
Many applications will select a reference clock operating at the
data input rate as shown in Figure 24. In this case, the external
clock source is applied to CLKIN and the PLL Clock Multiplier
is fully enabled by tying PLLENABLE and VCO IN/EXT to
PLLVDD. Note, CLKIN must adhere to the timing require-
ments shown in Figure 1. A 1.5 kW resistor and 0.01 mF ceramic
capacitor connected in series from LPF to PLLVDD are re-
quired to optimize the phase noise vs. settling/acquisition time
characteristics of the PLL. PLLLOCK is a control output, ac-
tive HIGH, which may be monitored upon system power-up to
indicate that the PLL is successfully “locked” to CLKIN. Note,
applications employing multiple AD9774 devices will benefit
from the PLL Clock Multiplier’s ability to ensure precise simul-
taneous updating/phase synchronization of these devices when
driven by the same input clock source.
PLLDIVIDE is used to preset the “lock-in” range of the PLL. It
should be tied to PLLCOM if CLKIN is greater than 10 MHz
and to PLLVDD if CLKIN is between 5.5 MHz and 10 MHz.
For operation below 5.5 MHz (i.e., input data rates less than
5.5 MSPS), the internal charge pump and VCO should be
disabled by tying PLLENABLE and VCO IN/EXT LOW. In
this case, the user MUST supply a system clock operating at 4·
the input data rate as discussed below.
CONNECT TO
PLLCOM
CONNECT TOThere are two cases in which a user may consider or be required
to disable the internal PLL Clock Multiplier and supply the
AD9774 with an external 4· system clock. Applications already
containing a system clock operating at four (i.e., 4·) the input
data rate may consider using it as the master clock source. Ap-
plications with input data rates less than 5.5 MSPS must use a
master 4· clock.
In any of these cases, the clock source is applied to CLK4·IN
and the PLL is partially disabled by typing PLLENABLE and
VCO IN/EXT to PLLCOM as shown in Figure 25. LPF may
remain open since this portion of the PLL circuitry is disabled.
The divide-by-N circuit still remains enabled providing a 1· or internal clock at CLOCK IN/OUT depending on the state of
PLLDIVIDE. Since the digital input data is latched into the
AD9774 on the rising edge of the 1· clock, PLLDIVIDE should
be tied to PLLCOM such that the 1· clock appears as an output
at CLOCK IN/OUT. The input data should be stable 5 ns (i.e.,
data set-up) before the rising edge of the 1· clock appearing at
CLOCK IN/OUT and remain stable for 1 ns after the rising
edge (i.e., data hold) to ensure proper latching. Note, the rising
edge of the 1· clock occurs approximately 9 ns to 15 ns relative
to the falling edge of the CLK4· input. If a data timing issue
exists between the AD9774 and its external driver device, the
CLK4· input can be inverted via an external gate to ensure
proper set-up and hold time.
LPF
+2.7 TO +5.5 VD
PLL
COM
+2.7 TO +5.5 VDFigure 25.Clock Divider with PLL Disabled
DAC OPERATIONThe 14-bit DAC along with the 1.2 V reference and reference
control amplifier is shown in Figure 26. The DAC consists of a
large PMOS current source array capable of providing up tomA of full-scale current, IOUTFS. The array is divided into 31
equal currents which make up the five most significant bits
(MSBs). The next four bits or middle bits consist of 15 equal
current sources whose values are 1/16th of an MSB current
source. The remaining LSBs are binary weighted fractions of the
middle-bits current sources. All of these current sources are
switched to one or the other of two output nodes (i.e., IOUTA
or IOUTB) via PMOS differential current switches. Implement-
ing the middle and lower bits with current sources, instead of an
AD9774Figure 26. Block Diagram of Internal DAC, 1.2 V Reference,
and Reference Control Circuits
The full-scale output current is regulated by the reference con-
trol amplifier and can be set from 2 mA to 20 mA via an exter-
nal resistor, RSET. The external resistor,␣ in combination with
both the reference control amplifier and voltage reference,
REFIO, sets the reference current, IREF, which is mirrored over
to the segmented current sources with the proper scaling factor.
The full-scale current, IOUTFS, is exactly thirty-two times the
value of IREF.
DAC TRANSFER FUNCTIONThe AD9774 provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current out-
put, IOUTFS, when all bits are high (i.e., DAC CODE = 16383)
while IOUTB, the complementary output, provides no current.
The current output appearing at IOUTA and IOUTB is a func-
tion of both the input code and IOUTFS and can be expressed as:
IOUTA = (DAC CODE/16384) · IOUTFS(1)
IOUTB = (16383 – DAC CODE)/16384 · IOUTFS(2)
where DAC CODE = 0 to 16383 (i.e., Decimal Representation).
As previously mentioned, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage
VREFIO and external resistor RSET. It can be expressed as:
IOUTFS = 32 · IREF(3)
where IREF = VREFIO/RSET(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, that are tied to analog common, ACOM. Note
that RLOAD may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminatedW or 75W cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply:
VOUTA = IOUTA · RLOAD(5)
VOUTB = IOUTB · RLOAD(6)
Note that the full-scale value of VOUTA and VOUTB should not
exceed the specified output compliance range to maintain speci-
fied distortion and linearity performance.
The differential voltage, VDIFF, appearing across IOUTA and
IOUTB is:
Substituting the values of IOUTA, IOUTB and IREF; VDIFF can
be expressed as:
VDIFF = {(2 DAC CODE – 16383)/16384} ·
VDIFF = {(32 RLOAD/RSET) · VREFIO(8)
These last two equations highlight some of the advantages of
operating the AD9774 differentially. First, the differential
operation will help cancel common-mode error sources associ-
ated with IOUTA and IOUTB such as noise, distortion and dc
offsets. Second, the differential code-dependent current and
subsequent voltage, VDIFF, is twice the value of the single-ended
voltage output (i.e., VOUTA or VOUTB), thus providing twice the
signal power to the load.
Note that the gain drift temperature performance for a single-
ended (VOUTA and VOUTB) or differential output (VDIFF) of
the AD9774 can be enhanced by selecting temperature tracking
resistors for RLOAD and RSET due to their ratiometric relation-
ship as shown in Equation 8.
REFERENCE OPERATIONThe AD9774 contains an internal 1.20 V bandgap reference
that can be easily disabled and overridden by an external
reference. REFIO serves as either an input or output, depending
on whether the internal or external reference is selected. If
REFLO is tied to ACOM, as shown in Figure 27, the internal
reference is activated, and REFIO provides a 1.20V output. In
this case, the internal reference must be compensated externally
with a ceramic chip capacitor of 0.1mF or greater from REFIO
to REFLO. If any additional loading is required, REFIO should
be buffered with an external amplifier having an input bias cur-
rent less than 100nA.
Figure 27.Internal Reference Configuration
The internal reference can be disabled by connecting REFLO to
AVDD. In this case, an external reference may then be applied
to REFIO as shown in Figure 28. The external reference may
provide either a fixed reference voltage to enhance accuracy and
drift performance or a varying reference voltage for gain control.
Note that the 0.1mF compensation capacitor is not required
since the internal reference is disabled, and the high input im-
pedance (i.e., 1 MW) of REFIO minimizes any loading of the
external reference.
