AD9773BSV ,12-Bit, 160 MSPS 2x/4x/8x Interpolating Dual TxDAC+® D/A ConverterCharacteristics ....... 13 Modulation, Interpolation = 2× .. 35 Mode Control (Via SPI Port) ....... ..
AD9773BSV ,12-Bit, 160 MSPS 2x/4x/8x Interpolating Dual TxDAC+® D/A Converterfeatures a serial port interface (SPI) that provides a high level of WCDMA ACPR −69 dB @ IF = 19.2 ..
AD9773BSVZ , 12-Bit, 160 MSPS, 2x/4x/8x Interpolating Dual TxDAC D/A Converter
AD9773BSVZ , 12-Bit, 160 MSPS, 2x/4x/8x Interpolating Dual TxDAC D/A Converter
AD9774AS ,14-Bit, 32 MSPS TxDAC⑩ with 4x Interpolation FiltersSPECIFICATIONS (T to T , AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, I = 20 mA, unless otherwise noted ..
AD9775 ,14-Bit, 160 MSPS 2x/4x/8x Interpolating Dual TxDAC+?D/A Converterfeatures the ability to perform f /2, f /4, and f /8S S S2. Direct IF transmission capability for 7 ..
ADS8410IRGZT ,16-Bit, Unipolar Pseudo Diff Input, 2MSPS Sampling rate, 4.75V to 5.25V ADC with LVDS Serial Interf 48-VQFN -40 to 85 SLAS493A –OCTOBER 2005–REVISED MAY 2013SPECIFICATIONST = –40°C to 85°C, +VA = 5 V,+VBD = 5 V or 3. ..
ADS8411IBPFBR ,16-BIT/ 2 MSPS/ UNIPOLAR INPUT/ MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCESLAS369B–APRIL 2002–REVISED DECEMBER 2004SPECIFICATIONST = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or ..
ADS8411IBPFBT ,16-BIT/ 2 MSPS/ UNIPOLAR INPUT/ MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCEFEATURES APPLICATIONS• DWDM• 2-MHz Sample Rate• Instrumentation• 16-Bit NMC Ensured Over Temperatur ..
ADS8412IBPFBR ,16 Bit 2MSPS Parallel ADC W/Ref, Pseudo Bipolar Fully Differential InputFEATURES APPLICATIONS• DWDM• 2-MHz Sample Rate• Instrumentation• 16-Bit NMC Ensured Over Temperatur ..
ADS8412IBPFBT ,16 Bit 2MSPS Parallel ADC W/Ref, Pseudo Bipolar Fully Differential InputSLAS384A–JUNE 2003–REVISED DECEMBER 2004SPECIFICATIONST = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 ..
ADS8413IBRGZT ,16-bit, Unipolar Diff Input, 2MSPS Sampling rate, 4.75V to 5.25V ADC with LVDS Serial Interface 48-VQFN -40 to 85FEATURES APPLICATIONS• Medical Instrumentation• 2-MHz Sample Rate• HIgh-Speed Data Acquisiton Syste ..
AD9773BSV
12-Bit, 160 MSPS 2x/4x/8x Interpolating Dual TxDAC+® D/A Converter
12-Bit, 160 MSPS, 2×/4×/8×Interpolating Dual TxDAC+® D/A Converter
Rev. B
FEATURES
12-bit resolution, 160 MSPS/400 MSPS
input/output data rate
Selectable 2×/4×/8× interpolating filter
Programmable channel gain and offset adjustment
fS/4, fS/8 digital quadrature modulation capability
Direct IF transmission mode for 70 MHz + IFs
Enables image rejection architecture
Fully compatible SPI® port
Excellent AC performance
SFDR −69 dBc @ 2 MHz to 35 MHz
WCDMA ACPR −69 dB @ IF = 19.2 MHz
Internal PLL clock multiplier
Selectable internal clock divider
Versatile clock input
Differential/single-ended sine wave or
TTL/CMOS/LVPECL compatible
Versatile input data interface
Twos complement/straight binary data coding
Dual-port or single-port interleaved input data
Single 3.3 V supply operation
Power dissipation: typical 1.2 W @ 3.3 V
On-chip 1.2 V reference
80-lead thermally enhanced TQFP package
APPLICATIONS
Communications
Analog quadrature modulation architecture
3G, multicarrier GSM, TDMA, CDMA systems
Broadband wireless, point-to-point microwave radios
Instrumentation/ATE
GENERAL DESCRIPTION The AD97731 is the 12-bit member of the AD977x pin
compatible, high performance, programmable
2×/4×/8× interpolating TxDAC+ family. The AD977x family
features a serial port interface (SPI) that provides a high level of
programmability, thus allowing for enhanced system-level
options. These options include selectable 2×/4×/8×
interpolation filters; fS/2, fS/4, or fS/8 digital quadrature
modulation with image rejection; a direct IF mode;
programmable channel gain and offset control; programmable
internal clock divider; straight binary or twos complement data
interface; and a single-port or dual-port data interface.
(continued on Page 4)
. Patent Numbers 5,568,145; 5,689,257; and 5,703,519. Other
patents pending.
FUNCTIONAL BLOCK DIAGRAM 02857-B-001
Figure 1.
TABLE OF CONTENTS General Description.........................................................................4
Product Highlights.......................................................................4
Specifications.....................................................................................5
Absolute Maximum Ratings............................................................9
Thermal Characteristics..............................................................9
ESD Caution..................................................................................9
Pin Configuration and Function Descriptions...........................10
Terminology....................................................................................12
Typical Performance Characteristics...........................................13
Mode Control (Via SPI Port)....................................................18
Register Description...................................................................20
Functional Description..............................................................22
Serial Interface for Register Control........................................22
General Operation of the Serial Interface...............................22
Instruction Byte..........................................................................23
Serial Interface Port Pin Descriptions.....................................23
MSB/LSB Transfers.....................................................................23
Notes on Serial Port Operation................................................25
DAC Operation...........................................................................25
1R/2R Mode................................................................................26
Clock Input Configurations......................................................26
Programmable PLL....................................................................27
Power Dissipation.......................................................................29
Sleep/Power-Down Modes........................................................29
Two-Port Data Input Mode.......................................................29
One-/Two-Port Input Modes....................................................30
PLL Enabled, Two-Port Mode..................................................30
DATACLK Inversion..................................................................30
DATACLK Driver Strength.......................................................31
PLL Enabled, One-Port Mode..................................................31
ONEPORTCLK Inversion.........................................................31
IQ Pairing....................................................................................31
PLL Disabled, Two-Port Mode.................................................32
PLL Disabled, One-Port Mode.................................................32
Digital Filter Modes...................................................................32
Amplitude Modulation..............................................................33
Modulation, No Interpolation..................................................34
Modulation, Interpolation = 2×...............................................35
Modulation, Interpolation = 4×...............................................36
Modulation, Interpolation = 8×...............................................37
Zero Stuffing...............................................................................38
Interpolating (Complex Mix Mode)........................................38
Operations on Complex Signals...............................................38
Complex Modulation and Image Rejection of Baseband
Signals..........................................................................................39
Image Rejection and Sideband Suppression of Modulated
Carriers........................................................................................41
Applying the AD9773 Output Configurations.......................46
Unbuffered Differential Output, Equivalent Circuit.............46
Differential Coupling Using a Transformer............................46
Differential Coupling Using an Op Amp................................47
Interfacing the AD9773 with the AD8345 Quadrature
Modulator....................................................................................47
Evaluation Board........................................................................48
Outline Dimensions.......................................................................58
Ordering Guide..........................................................................58
REVISION HISTORY
4/04—Data Sheet Changed from Rev. A to Rev. B. Update Layout....................................................................Universal
Changes to DC Specifications.......................................................5
Changes to Absolute Maximum Ratings......................................9
Changes to DAC Operation Section...........................................25
Inserted Figure 38..........................................................................25
Changes to Figure 40....................................................................26
Changes to Table 11......................................................................28
Changes to Programmable PLL Section.....................................29
Changes to Power Dissipation Section.......................................29
Changes to Figures 49, 50, and 51...............................................29
Changes to PLL Enabled, One-Port Mode Section...................31
Changes to PLL Disabled, One-Port Mode Section..................32
Changes to Figure 102..................................................................49
Changes to Figure 104..................................................................50
Updated Ordering Guide.............................................................58
Updated Outline Dimensions......................................................58
3/03—Data Sheet Changed from Rev. 0 to Rev. A. Edits to Features...............................................................................1
Edits to DC Specifications..............................................................3
Edits to Dynamic Specifications....................................................4
Edits to Pin Function Descriptions...............................................7
Edits to Table I...............................................................................14
Edits to Register Description—Address 02h Section...............15
Edits to Register Description—Address 03h Section...............16
Edits to Register Description—Address 07h, 0Bh Section......16
Edits to Equation 1........................................................................16
Edits to MSB/LSB Transfers Section...........................................18
Changes to Figure 8......................................................................20
Edits to Programmable PLL Section...........................................21
Added new Figure 14....................................................................22
Renumbered Figures 15 through 69...........................................22
Add Two-Port Data Input Mode Section...................................23
Edits to PLL Enabled, Two-Port Mode Section.........................24
Edits to Figure 19..........................................................................24
Edits to Figure 21..........................................................................25
Edits to PLL Disabled, Two-Port Mode Section.......................25
Edits to Figure 22..........................................................................25
Edits to Figure 23..........................................................................26
Edits to Figure 26a........................................................................27
Edits to Complex Modulation and Image Rejection of Baseband
Signals Section...............................................................................31
Changes to Figures 53 and 54......................................................38
Edits to Evaluation Board Section..............................................39
Changes to Figures 56 through 59..............................................40
Replaced Figures Figures 60 through 69....................................42
Updated Outline Dimensions......................................................49
GENERAL DESCRIPTION(continued from Page 1)
The selectable 2×/4×/8× interpolation filters simplify the
requirements of the reconstruction filters while simultaneously
enhancing the TxDAC+ family’s pass-band noise/distortion
performance. The independent channel gain and offset adjust
registers allow the user to calibrate LO feedthrough and
sideband suppression errors associated with analog quadrature
modulators. The 6 dB of gain adjustment range can also be used
to control the output power level of each DAC.
The AD9773 features the ability to perform fS/2, fS/4, and fS/8
digital modulation and image rejection when combined with an
analog quadrature modulator. In this mode, the AD9773 accepts
I and Q complex data (representing a single or multicarrier
waveform), generates a quadrature modulated IF signal along
with its orthogonal representation via its dual DACs, and
presents these two reconstructed orthogonal IF carriers to an
analog quadrature modulator to complete the image rejection
upconversion process. Another digital modulation mode (i.e.,
the direct IF mode) allows the original baseband signal
representation to be frequency translated such that pairs of
images fall at multiples of one-half the DAC update rate.
The AD977x family includes a flexible clock interface accepting
differential or single-ended sine wave or digital logic inputs. An
internal PLL clock multiplier is included and generates the
necessary on-chip high frequency clocks. It can also be disabled
to allow the use of a higher performance external clock source.
An internal programmable divider simplifies clock generation
in the converter when using an external clock source. A flexible
data input interface allows for straight binary or twos
complement formats and supports single-port interleaved or
dual-port data.
Dual high performance DAC outputs provide a differential
current output programmable over a 2 mA to 20 mA range. The
AD9773 is manufactured on an advanced 0.35 micron CMOS
process, operates from a single supply of 3.1 V to 3.5 V, and
consumes 1.2 W of power.
Targeted at a wide dynamic range, multicarrier, and
multistandard systems, the superb baseband performance of the
AD9773 is ideal for wide band CDMA, multicarrier CDMA,
multicarrier TDMA, multicarrier GSM, and high performance
systems employing high order QAM modulation schemes. The
image rejection feature simplifies and can help to reduce the
number of signal band filters needed in a transmit signal chain.
The direct IF mode helps to eliminate a costly mixer stage for a
variety of communications systems.
PRODUCT HIGHLIGHTS 1. The AD9773 is the 12-bit member of the AD977x pin
compatible, high performance, programmable 2×/4×/8×
interpolating TxDAC+ family.
2. Direct IF transmission is possible for 70 MHz + IFs
through a novel digital mixing process.
3. fS/2, fS/4, and fS/8 digital quadrature modulation and user
selectable image rejection simplify/remove cascaded SAW
filter stages.
4. A 2×/4×/8× user selectable interpolating filter eases data
rate and output signal reconstruction filter requirements.
5. User selectable twos complement/straight binary
data coding.
6. User programmable channel gain control over 1 dB range
in 0.01 dB increments.
7. User programmable channel offset control ±10% over
the FSR.
8. Ultrahigh speed 400 MSPS DAC conversion rate.
9. Internal clock divider provides data rate clock for
easy interfacing.
10. Flexible clock input with single-ended or differential input,
CMOS, or 1 V p-p LO sine wave input capability.
11. Low power: Complete CMOS DAC operates on 1.2 W from
a 3.1 V to 3.5 V single supply. The 20 mA full-scale current
can be reduced for lower power operation, and several
sleep functions reduce power during idle periods.
12. On-chip voltage reference: The AD9773 includes a 1.20 V
temperature compensated band gap voltage reference.
13. 80-lead thermally enhanced TQFP.
SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1. DC Specifications 1 Measured at IOUTA driving a virtual ground.
2 Nominal full-scale current, IOUTFS, is 32× the IREF current.
