AD9772AAST ,14-Bit, 160 MSPS TxDAC+ with 2x Interpolation FilterSPECIFICATIONS differential transformer coupled output, 50 doubly terminated, unless otherwise no ..
AD9773BSV ,12-Bit, 160 MSPS 2x/4x/8x Interpolating Dual TxDAC+® D/A ConverterCharacteristics ....... 13 Modulation, Interpolation = 2× .. 35 Mode Control (Via SPI Port) ....... ..
AD9773BSV ,12-Bit, 160 MSPS 2x/4x/8x Interpolating Dual TxDAC+® D/A Converterfeatures a serial port interface (SPI) that provides a high level of WCDMA ACPR −69 dB @ IF = 19.2 ..
AD9773BSVZ , 12-Bit, 160 MSPS, 2x/4x/8x Interpolating Dual TxDAC D/A Converter
AD9773BSVZ , 12-Bit, 160 MSPS, 2x/4x/8x Interpolating Dual TxDAC D/A Converter
AD9774AS ,14-Bit, 32 MSPS TxDAC⑩ with 4x Interpolation FiltersSPECIFICATIONS (T to T , AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, I = 20 mA, unless otherwise noted ..
ADS8406IPFBTG4 ,16-Bit 1.25 MSPS, Pseudo Bipolar, Fully Differential Input Micro Power Sampling ADC 48-TQFP -40 to 85SLAS426A–AUGUST 2004–REVISED DECEMBER 2004SPECIFICATIONST = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or ..
ADS8410IBRGZT ,16-Bit, Unipolar Pseudo Diff Input, 2MSPS Sampling rate, 4.75V to 5.25V ADC with LVDS Serial Interf 48-VQFN -40 to 85FEATURES APPLICATIONS• 2-MHz Sample Rate • Medical Instrumentation• 16-Bit Resolution • HIgh-Speed ..
ADS8410IRGZT ,16-Bit, Unipolar Pseudo Diff Input, 2MSPS Sampling rate, 4.75V to 5.25V ADC with LVDS Serial Interf 48-VQFN -40 to 85 SLAS493A –OCTOBER 2005–REVISED MAY 2013SPECIFICATIONST = –40°C to 85°C, +VA = 5 V,+VBD = 5 V or 3. ..
ADS8411IBPFBR ,16-BIT/ 2 MSPS/ UNIPOLAR INPUT/ MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCESLAS369B–APRIL 2002–REVISED DECEMBER 2004SPECIFICATIONST = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or ..
ADS8411IBPFBT ,16-BIT/ 2 MSPS/ UNIPOLAR INPUT/ MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCEFEATURES APPLICATIONS• DWDM• 2-MHz Sample Rate• Instrumentation• 16-Bit NMC Ensured Over Temperatur ..
ADS8412IBPFBR ,16 Bit 2MSPS Parallel ADC W/Ref, Pseudo Bipolar Fully Differential InputFEATURES APPLICATIONS• DWDM• 2-MHz Sample Rate• Instrumentation• 16-Bit NMC Ensured Over Temperatur ..
AD9772AAST
14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter
REV.A
14-Bit, 160 MSPS TxDAC+®
with 2� Interpolation Filter
FUNCTIONAL BLOCK DIAGRAM
CLKCOMCLKVDDMOD0MOD1RESETPLLLOCKDIV0DIV1
CLK+
CLK–
DATA
INPUTS
(DB13...
DB0)
SLEEP
DCOMDVDDACOMAVDDREFLO
PLLCOM
LPF
PLLVDD
IOUTA
IOUTB
REFIO
FSADJ
FEATURES
Single 3.0 V to 3.6 V Supply
14-Bit DAC Resolution and Input Data Width
160 MSPS Input Data Rate
67.5 MHz Reconstruction Passband @ 160 MSPS
74 dBc SFDR @ 25 MHz
2� Interpolation Filter with High- or Low-Pass Response
73 dB Image Rejection with 0.005dB Passband Ripple
“Zero-Stuffing” Option for Enhanced Direct IF
Performance
Internal 2�/4� Clock Multiplier
250 mW Power Dissipation; 13 mW with Power-Down
Mode
48-Lead LQFP Package
APPLICATIONS
Communication Transmit Channel
W-CDMA Base Stations, Multicarrier Base Stations,
Direct IF Synthesis, Wideband Cable Systems
Instrumentation
PRODUCT DESCRIPTIONThe AD9772A is a single-supply, oversampling, 14-bit digital-
to-analog converter (DAC) optimized for baseband or IF
waveform reconstruction applications requiring exceptional
dynamic range. Manufactured on an advanced CMOS process,
it integrates a complete, low distortion 14-bit DAC with a 2�
digital interpolation filter and clock multiplier. The on-chip
PLL clock multiplier provides all the necessary clocks for the
digital filter and the 14-bit DAC. A flexible differential clock
input allows for a single-ended or differential clock driver for
optimum jitter performance.
For baseband applications, the 2� digital interpolation filter
provides a low-pass response, hence providing up to a threefold
reduction in the complexity of the analog reconstruction filter. It
does so by multiplying the input data rate by a factor of two
while simultaneously suppressing the original upper in-band
image by more than 73 dB. For direct IF applications, the 2�
digital interpolation filter response can be reconfigured to select
the upper in-band image (i.e., high-pass response) while suppress-
ing the original baseband image. To increase the signal level of
the higher IF images and their passband flatness in direct IF
applications, the AD9772A also features a “zero stuffing” option
in which the data following the 2� interpolation filter is upsampled
by a factor of two by inserting midscale data samples.
The AD9772A can reconstruct full-scale waveforms with band-
widths as high as 67.5 MHz while operating at an input data rate of
160 MSPS. The 14-bit DAC provides differential current outputs
to support differential or single-ended applications. A segmented
current source architecture is combined with a proprietary
switching technique to reduce spurious components and enhance
dynamic performance. Matching between the two current outputs
ensures enhanced dynamic performance in a differential output
configuration. The differential current outputs may be fed into a
transformer or a differential op amp topology to obtain a single-
ended output voltage using an appropriate resistive load.
The on-chip bandgap reference and control amplifier are config-
ured for maximum accuracy and flexibility. The AD9772A can
be driven by the on-chip reference or by a variety of external
reference voltages. The full-scale current of the AD9772A can
be adjusted over a 2mA to 20 mA range, thus providing addi-
tional gain ranging capabilities.
The AD9772A is available in a 48-lead LQFP package and
specified for operation over the industrial temperature range
of –40°C to +85°C.
PRODUCT HIGHLIGHTSA flexible, low power 2� interpolation filter supporting
reconstruction bandwidths of up to 67.5 MHz can be config-
ured for a low- or high-pass response with 73dB of image
rejection for traditional baseband or direct IF applications.A “zero-stuffing” option enhances direct IF applications.A low glitch, fast settling 14-bit DAC provides exceptional
dynamic range for both baseband and direct IF waveform
reconstruction applications.The AD9772A digital interface, consisting of edge-
triggered latches and a flexible differential or single-ended
clock input, can support input data rates up to 160 MSPS.On-chip PLL clock multiplier generates all of the inter-
nal high-speed clocks required by the interpolation filter
and DAC.The current output(s) of the AD9772A can easily be config-
ured for various single-ended or differential circuit topologies.
TxDAC+ is a registered trademark of Analog Devices, Inc.
AD9772A–SPECIFICATIONS
DC SPECIFICATIONSNOTESMeasured at IOUTA driving a virtual ground.Nominal full-scale current, IOUTFS, is 32�the IREF current.Use an external amplifier to drive any external load.Measured at fDATA = 100 MSPS and fOUT = 1 MHz, DIV1, DIV0 = 0 V.Measured with PLL enabled at fDATA = 50 MSPS and fOUT = 1 MHz.Measured over a 3.0 V to 3.6 V range.
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.)
AD9772A
DYNAMIC SPECIFICATIONSAC LINEARITY—IF MODE
NOTESPropagation delay is delay from CLK input to DAC update.Measured single-ended into 50 Ω load.
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, IOUTFS = 20 mA,
differential transformer coupled output, 50 � doubly terminated, unless otherwise noted.)
AD9772A–SPECIFICATIONS
DIGITAL SPECIFICATIONS*MOD0, MOD1, DIV0, DIV1, SLEEP, RESET have typical input currents of 15 µA.
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3V, IOUTFS = 20 mA, unless
otherwise noted.)Figure 1a.Timing Diagram—PLL Clock Multiplier Enabled
Figure 1b.Timing Diagram—PLL Clock Multiplier Disabled
AD9772A
(TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20mA,
differential transformer coupled output, 50 � doubly terminated, unless otherwise noted.)DIGITAL FILTER SPECIFICATIONSIMPULSE RESPONSE DURATION
NOTESExcludes sin(x)/x characteristic of DAC.Defined as the number of data clock cycles between impulse input and peak of output response.
Specifications subject to change without notice.
Figure 2a.FIR Filter Frequency Response—Baseband Mode
Table I.Integer Filter Coefficients for Interpolation Filter
(43-Tap Half-Band FIR Filter)
AD9772A
ABSOLUTE MAXIMUM RATINGS*AVDD, DVDD1-2, CLKVDD, PLLVDD
ACOM, DCOM1-2, CLKCOM, PLLCOM
REFIO, REFLO, FSADJ, SLEEP
IOUTA, IOUTB
DB0–DB13, MOD0, MOD1, PLLLOCK
CLK+, CLK–
DIV0, DIV1, RESET
LPF
Junction Temperature
Storage Temperature
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.
ORDERING GUIDE*ST = Thin Plastic Quad Flatpack.
THERMAL CHARACTERISTIC
Thermal Resistance48-Lead LQFP
θJA = 91°C/W
θJC = 28°C/W
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9772A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
SLEEP
LPF
PLLVDD
PLLCOM
CLKVDD
CLKCOM
CLK–
DCOM
DCOM
(MSB) DB13
DB12
DB11
DB10
DB9
NC = NO CONNECT
DB8
DB7
DB6
DB5
CLK+
DIV0
DIV1
RESET
DB4PLLLOCK
DVDDDVDDAVDDAVDDACOMI
OUTA
OUTB
ACOMFSADJREFIOREFLOACOM
DB3DB2DB1
(LSB) DB0
MOD0MOD1
DCOMDCOM
DVDDDVDDNC
AD9772A
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)Linearity error is defined as the maximum deviation of the actual
analog output from the ideal output, determined by a straight
line drawn from zero to full scale.
Differential Nonlinearity (or DNL)DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
MonotonicityA D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset ErrorThe deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when the
inputs are all 0s. For IOUTB, 0 mA output is expected when all
inputs are set to 1s.
Gain ErrorThe difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s, minus the output when all inputs are set to 0s.
Output Compliance RangeThe range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature DriftTemperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per °C. For reference drift, the drift is reported in
ppm per °C.
Power Supply RejectionThe maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.
Settling TimeThe time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch ImpulseAsymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic RangeThe difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic DistortionTHD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels (dB).
Signal-to-Noise Ratio (SNR)S/N is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
PassbandFrequency band in which any input applied therein passes
unattenuated to the DAC output.
Stopband RejectionThe amount of attenuation of a frequency outside the passband
applied to the DAC, relative to a full-scale signal applied at the
DAC input within the passband.
Group DelayNumber of input clocks between an impulse applied at the
device input and peak DAC output current.
Impulse ResponseResponse of the device to an impulse applied to the input.
Adjacent Channel Power Ratio (or ACPR)A ratio in dBc between the measured power within a channel
relative to its adjacent channel.
fOUT – MHz
AMPLITUDE
dBm
–20TPC 1.Single-Tone Spectral Plot @
fDATA = 65 MSPS with fOUT = fDATA/3
FREQUENCY – MHz
AMPLITUDE
dBm
–20TPC 4.Single-Tone Spectral Plot @
fDATA = 78 MSPS with fOUT = fDATA/3
TPC 7.Single-Tone Spectral Plot
TPC 2.In-Band SFDR vs. fOUT
@ fDATA = 65 MSPS
TPC 5.In-Band SFDR vs. fOUT
@ fDATA = 78 MSPS
TPC 8.In-Band SFDR vs. fOUT
Typical AC Characterization Curves
(AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3V, IOUTFS = 20 mA,
PLL Disabled.)TPC 3. Out-of-Band SFDR vs.
fOUT @ fDATA = 65 MSPS
TPC 6.Out-of-Band SFDR vs.
fOUT @ fDATA = 78 MSPS
TPC 9.Out-of-Band SFDR vs.
AD9772ATPC 10.Third Order IMD Products
vs. fOUT @ fDATA = 65 MSPS
TPC 13.Third Order IMD Products
vs. AOUT @ fOUT = fDAC/11
TPC 16.Third Order IMD Products
vs. AVDD @ fOUT = 10 MHz, fDAC =
320 MSPS
TPC 11.Third Order IMD Products
vs. fOUT @ fDATA = 78 MSPS
TPC 14.Third Order IMD Products
vs. AOUT @ fOUT = fDAC/5
TPC 17.SNR vs. fDAC @ fOUT = 10 MHz
TPC 12.Third Order IMD Products
vs. fOUT @ fDATA = 160 MSPS
TPC 15.SFDR vs. AVDD @ fOUT =
10 MHz, fDAC = 320 MSPS
TPC 18.In-Band SFDR vs. Tempera-
ture @ fOUT = fDATA/11
FUNCTIONAL DESCRIPTIONFigure 4 shows a simplified block diagram of the AD9772A.
The AD9772A is a complete, 2� oversampling, 14-bit DAC that
includes a 2� interpolation filter, a phase-locked loop (PLL)
clock multiplier and a 1.20 V bandgap voltage reference. While
the AD9772A’s digital interface can support input data rates as
high as 160 MSPS, its internal DAC can operate up to 400 MSPS,
thus providing direct IF conversion capabilities. The 14-bit DAC
provides two complementary current outputs whose full-scale
current is determined by an external resistor. The AD9772A
features a flexible, low jitter, differential clock input providing
excellent noise rejection while accepting a sine wave input. An
on-chip PLL clock multiplier produces all of the necessary
synchronized clocks from an external reference clock source.
Separate supply inputs are provided for each functional block to
ensure optimum noise and distortion performance. A SLEEP
mode is also included for power savings.
CLKCOMCLKVDDMOD0MOD1RESETPLLLOCKDIV0DIV1
CLK+
CLK–
DATA
INPUTS
(DB13...
DB0)
SLEEP
DCOMDVDDACOMAVDDREFLO
PLLCOM
LPF
PLLVDD
IOUTA
IOUTB
REFIO
FSADJFigure 4.Functional Block Diagram
Preceding the 14-bit DAC is a 2� digital interpolation filter that
can be configured for a low-pass (i.e., baseband mode) or high-
pass (i.e., direct IF mode) response. The input data is latched
into the edge-triggered input latches on the rising edge of the
differential input clock as shown in Figure 1a and then interpo-
lated by a factor of two by the digital filter. For traditional baseband
applications, the 2� interpolation filter has a low-pass response.
For direct IF applications, the filter’s response can be converted
into a high-pass response to extract the higher image. The output
data of the 2� interpolation filter can update the 14-bit DAC
directly or undergo a “zero-stuffing” process to increase the DAC
update rate by another factor of two. This action enhances the
relative signal level and passband flatness of the higher images.
DIGITAL MODES OF OPERATIONThe AD9772A features four different digital modes of operation
controlled by the digital inputs, MOD0 and MOD1. MOD0
controls the 2� digital filter’s response (i.e., low-pass or high-
pass), while MOD1 controls the “zero-stuffing” option. The
selected mode as shown in Table II will depend on whether the
application requires the reconstruction of a baseband or IF signal.
Table II.Digital ModesApplications requiring the highest dynamic range over a wide
bandwidth should consider operating the AD9772A in a baseband
mode. Note, the “zero-stuffing” option can also be used in this
mode although the ratio of signal to image power will be reduced.
Applications requiring the synthesis of IF signals should con-
sider operating the AD9772A in a Direct IF mode. In this case,
the “zero-stuffing” option should be considered when synthesiz-
ing and selecting IFs beyond the input data rate, fDATA. If the
reconstructed IF falls below fDATA, the “zero-stuffing” option
may or may not be beneficial. Note, the dynamic range (i.e.,
SNR/SFDR) is also optimized by disabling the PLL Clock Mul-
tiplier (i.e., PLLVDD to PLLCOM) and using an external low
jitter clock source operating at the DAC update rate, fDAC.
2� Interpolation Filter DescriptionThe 2� interpolation filter is based on a 43-tap half-band sym-
metric FIR topology that can be configured for a low- or
high-pass response, depending on the state of the MOD0
control input. The low-pass response is selected with MOD0
LOW while the high-pass response is selected with MOD0
HIGH. The low-pass frequency and impulse response of the
half-band interpolation filter are shown in Figures 2a and 2b,
while Table I lists the idealized filter coefficients. Note, a FIR
filter’s impulse response is also represented by its idealized
filter coefficients.
The 2× interpolation filter essentially multiplies the input data
rate to the DAC by a factor of two, relative to its original input
data rate, while simultaneously reducing the magnitude of the
first image associated with the original input data rate occurring
at fDATA – fFUNDAMENTAL. Note, as a result of the 2� interpola-
tion, the digital filter’s frequency response is uniquely defined
over its Nyquist zone of dc to fDATA, with mirror images occur-
ring in adjacent Nyquist zones.
The benefits of an interpolation filter are clearly seen in Fig-
ure5, which shows an example of the frequency and time
domain representation of a discrete time sine wave signal before
and after it is applied to the 2� digital interpolation filter in a
low-pass configuration. Images of the sine wave signal appear
around multiples of the DAC’s input data rate (i.e., fDATA) as
predicted by sampling theory. These undesirable images will
also appear at the output of a reconstruction DAC, although
attenuated by the DAC’s sin(x)/x roll-off response.
In many bandlimited applications, the images from the recon-
struction process must be suppressed by an analog filter following
the DAC. The complexity of this analog filter is typically deter-
mined by the proximity of the desired fundamental to the first
image and the required amount of image suppression. Adding to
the complexity of this analog filter may be the requirement of
AD9772AReferring to Figure 5, the “new” first image associated with the
DAC’s higher data rate after interpolation is “pushed” out fur-
ther relative to the input signal, since it now occurs at 2�
fDATA– fFUNDAMENTAL. The “old” first image associated with the
lower DAC data rate before interpolation is suppressed by the
digital filter. As a result, the transition band for the analog
reconstruction filter is increased, thus reducing the complexity of the
analog filter. Furthermore, the sin(x)/x roll-off over the original
input data passband (i.e., dc to fDATA/2) is significantly reduced.
As previously mentioned, the 2� interpolation filter can be
converted into a high-pass response, thus suppressing the “fun-
damental” while passing the “original” first image occurring at
fDATA– fFUNDAMENTAL. Figure 6 shows the time and frequency
representation for a high-pass response of a discrete time sine
wave. This action can also be modeled as a “1/2 wave” digital
mixing process in which the impulse response of the low-pass
filter is digitally mixed with a square wave having a frequency
of exactly fDATA/2. Since the even coefficients have a zero value
(refer to Table I), this process simplifies into inverting the cen-
ter coefficient of the low-pass filter (i.e., invert H(18)). Note
that this also corresponds to inverting the peak of the impulse
response shown in Figure 2a. The resulting high-pass frequency
response becomes the frequency inverted mirror image of the
low-pass filter response shown in Figure 2b.
It is worth noting that the “new” first image now occurs at fDATA+
fFUNDAMENTAL. A reduced transition region of 2� fFUNDAMENTAL
exists for image selection, thus mandating that the fFUNDAMENTAL
be placed sufficiently high for practical filtering purposes in direct
IF applications. Also, the “lower sideband images” occurring at
fDATA – fFUNDAMENTAL and its multiples (i.e., N� fDATA –
fFUNDAMENTAL) experience a frequency inversion while the “upper
sideband images” occurring at fDATA + fFUNDAMENTAL and its mul-
tiples (i.e., N� fDATA + fFUNDAMENTAL) do not.
Figure 5.Time and Frequency Domain Example of Low-Pass 2� Digital Interpolation Filter
Figure 6.Time and Frequency Domain Example of High-Pass 2� Digital Interpolation Filter
“Zero Stuffing” Option DescriptionAs shown in Figure 7, a “zero” or null in the frequency responses
(after interpolation and DAC reconstruction) occurs at the final
DAC update rate (i.e., 2� fDATA) due to the DAC’s inherent
sin(x)/x roll-off response. In baseband applications, this roll-off
in the frequency response may not be as problematic since much
of the desired signal energy remains below fDATA/2 and the
amplitude variation is not as severe. However, in direct IF
applications interested in extracting an image above fDATA/2,
this roll-off may be problematic due to the increased passband
amplitude variation as well as the reduced signal level of the
higher images.
Figure 7.Effects of “Zero-Stuffing” on DAC’s
Sin(x)/x Response
For instance, if the digital data into the AD9772A represented a
baseband signal centered around fDATA/4 with a passband of
fDATA/10, the reconstructed baseband signal out of the AD9772A
would experience only a 0.18 dB amplitude variation over its
passband with the “first image” occurring at 7/4 fDATA with 17dB
of attenuation relative to the fundamental. However, if the high-
pass filter response was selected, the AD9772A would now
produce pairs of images at [(2N + 1)� fDATA] ± fDATA/4 where N
= 0, 1.... Note, due to the DAC’s sin(x)/x response, only the
lower or upper sideband images centered around fDATA may
be useful although they would be attenuated by –2.1 dB and
–6.54 dB respectively, as well as experience a passband amplitude
roll-off of 0.6 dB and 1.3 dB.
To improve upon the passband flatness of the desired image
and/or to extract higher images (i.e., 3� fDATA ± fFUNDAMENTAL)
the “zero-stuffing” option should be employed by bringing the
MOD1 pin HIGH. This option increases the effective DAC
update rate by another factor of two since a “midscale” sample
(i.e., 10 0000 0000 0000) is inserted after every data sample
originating from the 2� interpolation filter. A digital multiplexer
switching at a rate of 4� fDATA between the interpolation filter’s
output and a data register containing the “midscale” data sample is
used to implement this option as shown in Figure 6. Hence, the
DAC output is now forced to return to its differential midscale
current value (i.e., IOUTA–IOUTB ≅ 0 mA) after reconstructing
in Figure 7. Note that if the 2� interpolation filter’s high-pass
response is also selected, this action can be modeled as a “1/4
wave” digital mixing process since this is equivalent to digitally
mixing the impulse response of the low-pass filter with a square
wave having a frequency of exactly fDATA (i.e., fDAC/4).
It is important to realize that the “zero stuffing” option by itself
does not change the location of the images but rather their signal
level, amplitude flatness and relative weighting. For instance, in
the previous example, the passband amplitude flatness of the
lower and upper sideband images centered around fDATA are
improved to 0.14 dB and 0.24 dB respectively, while the signal
level has changed to –6.5 dBFS and –7.5 dBFS. The lower or
upper sideband image centered around 3� fDATA will exhibit an
amplitude flatness of 0.77 dB and 1.29 dB with signal levels of
approximately –14.3 dBFS and –19.2 dBFS.
PLL CLOCK MULTIPLIER OPERATIONThe Phase Lock Loop (PLL) clock multiplier circuitry along
with the clock distribution circuitry can produce the necessary
internally synchronized 1�, 2�, and 4� clocks for the edge
triggered latches, 2� interpolation filter, “zero stuffing” multi-
plier, and DAC. Figure 8 shows a functional block diagram of
the PLL clock multiplier, which consists of a phase detector, a
charge pump, a voltage controlled oscillator (VCO), a prescaler,
and digital control inputs/outputs. The clock distribution
circuitry generates all the internal clocks for a given mode of
operation. The charge pump and VCO are powered from
PLLVDD while the differential clock input buffer, phase detector,
prescaler and clock distribution circuitry are powered from
CLKVDD. To ensure optimum phase noise performance from
the PLL clock multiplier and clock distribution circuitry,
PLLVDD and CLKVDD must originate from the same clean
analog supply.
Figure 8.Clock Multiplier with PLL Clock
Multiplier Enabled
The PLL clock multiplier has two modes of operation. It can be
enabled for less demanding applications providing a reference
clock meeting the minimum specified input data rate of 6MSPS.
It can be disabled for applications below this data rate or for
applications requiring higher phase noise performance. In this
AD9772Acan be synchronized in either mode if driven by the same
reference clock, since the PLL clock multiplier when enabled
ensures synchronization. RESET can be used for synchroniza-
tion if the PLL clock multiplier is disabled.
Figure 8 shows the proper configuration used to enable the PLL
clock multiplier. In this case, the external clock source is applied
to CLK+ (and/or CLK–) and the PLL clock multiplier is fully
enabled by connecting PLLVDD to CLKVDD.
The settling/acquisition time characteristics of the PLL are also
dependent on the divide-by-N ratio as well as the input data rate.
In general, the acquisition time increases with increasing data rate
(for fixed divide-by-N ratio) or increasing divide-by-N ratio (for
fixed input data rate).
Since the VCO can operate over a 96 MHz–400 MHz range,
the prescaler divide-by-ratio following the VCO must be set
according to Table III for a given input data rate (i.e., fDATA)
to ensure optimum phase noise and successful “locking.” In
general, the best phase noise performance for any prescaler
setting is achieved with the VCO operating near its maximum
output frequency of 400MHz. Note, the divide-by-N ratio also
depends on whether the “zero stuffing” option is enabled since
this option requires the DAC to operate at four times the input
data rate. The divide-by-N ratio is set by DIV1 and DIV0.
With the PLL clock multiplier enabled, PLLLOCK serves as an
active HIGH control output which may be monitored upon sys-
tem power-up to indicate that the PLL is successfully “locked” to
the input clock. Note, when the PLL clock multiplier is NOT
locked, PLLLOCK will toggle between logic HIGH and LOW
in an asynchronous manner until locking is finally achieved.
As a result, it is recommended that PLLLOCK, if monitored,
be sampled several times to detect proper locking 100ms
upon power-up.
Table III.Recommended Prescaler Divide-by-N Ratio SettingsAs stated earlier, applications requiring input data rates belowMSPS must disable the PLL clock multiplier and provide an
external reference clock. However, applications already contain-
ing a low phase noise (i.e., jitter) reference clock that is twice
(or four times) the input data rate should consider disabling the
PLL clock multiplier to achieve the best SNR performance from
the AD9772A. Note that the SFDR performance and wideband
noise performance of the AD9772A remains unaffected with or
without the PLL clock multiplier enabled.
The effects of phase noise on the AD9772A’s SNR performance
becomes more noticeable at higher reconstructed output fre-
quencies and signal levels. Figure 9 compares the phase noise
of a full-scale sine wave at exactly fDATA/4 at different data rates
(hence carrier frequency) with the optimum DIV1, DIV0 setting.
The effects of phase noise, and its effect on a signal’s CNR
performance, becomes even more evident at higher IF fre-
quencies as shown in Figure10. In both instances, it is the
“narrowband” phase noise that limits the CNR performance.
Figure 9.Phase Noise of PLL Clock Multiplier at Exactly
fOUT= fDATA/4 at Different fDATA Settings with Optimum
DIV0/DIV1 Settings Using R & S FSEA30, RBW = 30kHz
Figure 10.Direct IF Mode Reveals Phase Noise Degrada-
tion with and without PLL Clock Multiplier (IF = 125MHz
and fDATA = 100MSPS)
To disable the PLL Clock Multiplier, connect PLLVDD to
PLLCOM as shown in Figure 11. LPF may remain open since
this portion of the PLL circuitry is now disabled. The differen-
tial clock input should be driven with a reference clock twice the
data input rate in baseband applications and four times the data
input rate in direct IF applications in which the “1/4 wave”
mixing option is employed (i.e., MOD1 and MOD0 active
HIGH). The clock distribution circuitry remains enabled pro-
viding a 1� internal clock at PLLLOCK. Digital input data is
latched into the AD9772 on every other rising edge of the differ-
ential clock input. The rising edge that corresponds to the input
latch immediately precedes the rising edge of the 1� clock at
PLLLOCK. Adequate setup and hold time for the input data as
shown in Figure 1b should be allowed. Note that enough delay
is present between CLK+/CLK– and the data input latch to
cause the minimum setup time for input data to be negative.
This is noted in the Digital Specifications section. PLLLOCK
contains a relatively weak driver output, with its output delay
(tOD) sensitive to output capacitance loading. Thus PLLLOCK
should be buffered for fanouts greater than one, and/or load
capacitance greater than 10pF. If a data timing issue exists
between the AD9772A and its external driver device, the 1�
clock appearing at PLLLOCK can be inverted via an external
gate to ensure proper setup and hold time.
Figure 11.Clock Multiplier with PLL Clock Multiplier
Disabled
SYNCHRONIZATION OF CLK/DATA USING RESET WITH
PLL DISABLEDThe relationship between the internal and external clocks in this
mode is shown in Figure 12. A clock at the output update data
rate (2� the input data rate) must be applied to the CLK in-
puts. Internal dividers create the internal 1� clock necessary for
the input latches. With the PLL disabled, a delayed version of the
1� clock is present at the PLLLOCK pin. The DAC latch is
updated on the particular rising edge of the external 2� clock
which corresponds to the rising edge of the 1� clock. Updates
to the input data should be synchronized to this specific rising
edge as shown in Figure 12. To ensure this synchronization, a
Logic1 should be momentarily applied to the RESET pin on
power up, before CLK is applied. Applying a momentary Logic 1
to RESET brings the 1� clock at PLLLOCK to a Logic 1. On
the next rising edge of the 2� clock, the 1� clock will go to
Logic 0. The following rising edge of the 2� clock will cause
the 1� clock to Logic 1 again, as well as update the data in
both of the input latches.
Figure 12.Internal Timing of AD9772A with PLL Disabled
Figure 13 illustrates the details of the RESET function timing.
RESET going from a high to a low logic level enables the 1�
clock output, generated by the PLLLOCK pin. If RESET goes
low at a time well before the rising edge of the 2� clock, then
PLLLOCK will go high on the following edge of the 2� clock. If
RESET goes from a high to a low logic level 600 ps or later
following the rising edge of the 2× clock, there will be a delay of
one 2� clock cycle before PLLLOCK goes high. In either case,
as long as RESET remains low, PLLLOCK will change state on
every rising edge of the 2� clock. As stated before, it is the rising
edge of the 2� clock which immediately precedes the rising edge
of PLLLOCK that latches data into the AD9772A input latches.
Figure 13.RESET Timing of AD9772A with PLL Disabled
AD9772A
DAC OPERATIONThe 14-bit DAC along with the 1.2 V reference and reference
control amplifier is shown in Figure 14. The DAC consists of a
large PMOS current source array capable of providing up tomA of full-scale current, IOUTFS. The array is divided into
thirty-one equal currents that make up the five most significant
bits (MSBs). The next four bits, or middle bits, consist of 15
equal current sources whose values are 1/16th of an MSB
current source. The remaining LSBs are binary weighted frac-
tions of the middle-bits’ current sources. All of these current
sources are switched to one or the other of two output nodes
(i.e., IOUTA or IOUTB) via PMOS differential current switches.
Implementing the middle and lower bits with current sources,
instead of an R-2R ladder, enhances its dynamic performance
for multitone or low amplitude signals and helps maintain the
DAC’s high output impedance.
Figure 14.Block Diagram of Internal DAC, 1.2 V
Reference, and Reference Control Circuits
The full-scale output current is regulated by the reference control
amplifier and can be set from 2 mA to 20 mA via an external
resistor, RSET, as shown in Figure 14. RSET, in combination
with both the reference control amplifier and voltage reference,
REFIO, sets the reference current, IREF, which is mirrored to
the segmented current sources with the proper scaling factor.
The full-scale current, IOUTFS, is exactly thirty-two times the
value of IREF.
DAC TRANSFER FUNCTIONThe AD9772A provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current output,
IOUTFS, when all bits are high (i.e., DAC CODE = 16383) while
IOUTB, the complementary output, provides no current. The
current output appearing at IOUTA and IOUTB is a function of
both the input code and IOUTFS and can be expressed as:
IOUTA = (DAC CODE/16384) × IOUTFS(1)
IOUTB = (16383 – DAC CODE)/16384 × IOUTFS(2)
where DAC CODE = 0 to 16383 (i.e., Decimal Representation).
As previously mentioned, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage
VREFIO, and external resistor, RSET. It can be expressed as:
IOUTFS = 32 × IREF(3)
where
IREF = VREFIO/RSET(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, that are tied to analog common, ACOM. Note
that RLOAD may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated 50 Ω
or 75 Ω cable. The single-ended voltage output appearing at the
IOUTA and IOUTB nodes is simply:
VOUTA = IOUTA × RLOAD(5)
VOUTB = IOUTB × RLOAD(6)
Note that the full-scale value of VOUTA and VOUTB should not
exceed the specified output compliance range of 1.25V to pre-
vent signal compression. To maintain optimum distortion and
linearity performance, the maximum voltages at VOUTA and
VOUTB should not exceed ±500mV p-p.
The differential voltage, VDIFF, appearing across IOUTA and
IOUTB, is:
VDIFF = (IOUTA – IOUTB) × RLOAD(7)
Substituting the values of IOUTA, IOUTB and IREF; VDIFF can be
expressed as:
VDIFF = [(2 DAC CODE – 16383)/16384] ×
(32 RLOAD/RSET) × VREFIO(8)
The last two equations highlight some of the advantages of
operating the AD9772A differentially. First, the differential
operation will help cancel common-mode error sources such as
noise, distortion and dc offsets associated with IOUTA and IOUTB.
Second, the differential code-dependent current and subsequent
voltage, VDIFF, is twice the value of the single-ended voltage
output (i.e., VOUTA or VOUTB), thus providing twice the signal
power to the load.
Note that the gain drift temperature performance for a single-
ended (VOUTA and VOUTB) or differential output (VDIFF) of the
AD9772A can be enhanced by selecting temperature tracking
resistors for RLOAD and RSET due to their ratiometric relation-
ship as shown in Equation 8.
REFERENCE OPERATIONThe AD9772A contains an internal 1.20 V bandgap reference
that can easily be disabled and overridden by an external
reference. REFIO serves as either an output or input, depending
on whether the internal or external reference is selected. If
REFLO is tied to ACOM, as shown in Figure 15, the internal
reference is activated, and REFIO provides a 1.20V output. In
this case, the internal reference must be compensated externally
with a ceramic chip capacitor of 0.1µF or greater from REFIO
to REFLO. If any additional loading is required, REFIO should
be buffered with an external amplifier having an input bias cur-
