AD977-AD977A Fast Delivery |IC PHOENIX CO.,LIMITED

AD977A ,16-Bit, 200 kSPS, Serial I/O A/D ConverterSPECIFICATIONS (–40C to +85C, F = 100 kHz, V = V = 5 V, unless otherwise noted)S DIG ANA ..
AD977AAN ,16-Bit, 100 kSPS/200 kSPS BiCMOS A/D ConverterSPECIFICATIONS (–408C to +858C, F = 200 kHz, V = V = +5 V, unless otherwise noted)S DIG ANA ..
AD977AAR ,16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converterspecifications of offset, gain– 3.3 V, and unipolar ranges of 0 V to 10 V, 0 V to 5 V andand linear ..
AD977AARS ,16-Bit, 100 kSPS/200 kSPS BiCMOS A/D ConverterFEATURES FUNCTIONAL BLOCK DIAGRAMFast 16-Bit ADC100 kSPS Throughput Rate—AD977 VREFANA AGND1200 kSP ..
AD977ABN ,16-Bit, 100 kSPS/200 kSPS BiCMOS A/D ConverterSPECIFICATIONS (–408C to +858C, F = 100 kHz, V = V = +5 V, unless otherwise noted)S DIG ANA ..
AD977ABR ,16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converterspecifications in dB are referred to a full scale – 10 V input.8Full-Power Bandwidth is defined as ..
ADS8505IDB ,16-Bit 250kHz CMOS Analog-to-Digital Converter w/Parallel Interface 2.5V Internal Reference 28-SSOP -40 to 85SLAS180B–SEPTEMBER 2005–REVISED JUNE 2007
ADS8505IDBG4 , 16-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER
ADS8505IDW ,16-Bit 250kHz CMOS Analog-to-Digital Converter w/Parallel Interface 2.5V Internal Reference 28-SOIC -40 to 85SLAS180B–SEPTEMBER 2005–REVISED JUNE 2007These devices have limited built-in ESD protection. The le ..
ADS8505IDW ,16-Bit 250kHz CMOS Analog-to-Digital Converter w/Parallel Interface 2.5V Internal Reference 28-SOIC -40 to 85ELECTRICAL CHARACTERISTICST = –40°C to 85°C, f = 250 kHz, V = V = 5 V, using internal reference (un ..
ADS8505IDWG4 ,16-Bit 250kHz CMOS Analog-to-Digital Converter w/Parallel Interface 2.5V Internal Reference 28-SOIC -40 to 85MAXIMUM RATINGS(2)over operating free-air temperature range (unless otherwise noted)UNITV ±25VINAna ..
ADS8506IBDW ,12-Bit 40KSPS Analog-to-Digital Converter w/Serial Interface and Reference Parallel 28-SOIC -40 to 85SLAS484B–SEPTEMBER 2007–REVISED DECEMBER 2007These devices have limited built-in ESD protection. Th ..

AD977-AD977A
16-Bit, 100 kSPS, Serial I/O A/D Converter
REV.D
16-Bit, 100 kSPS/200 kSPS
BiCMOS A/D Converter
FUNCTIONAL BLOCK DIAGRAM
PWRD
SYNC
DATACLK
DATA
R1IN
R2IN
R3IN
REFVANA
DGNDTAGR/CCS
VDIG
AGND2
CAP
AGND1
BUSY
SB/BTCEXT/INT
FEATURES
Fast 16-Bit ADC
100 kSPS Throughput Rate—AD977
200 kSPS Throughput Rate—AD977A
Single 5 V Supply Operation
Power Dissipation 100 mW Max
Power-Down Mode 50 �W
Input Ranges:
Unipolar; 0 V–10 V, 0 V–5 V and 0 V–4 V
Bipolar; �10 V, �5 V and �3.3 V
Choice of External or Internal 2.5 V Reference
High Speed Serial Interface
On-Chip Clock
20-Lead Skinny DIP or SOIC Package
28-Lead Skinny SSOP Package
GENERAL DESCRIPTION
The AD977/AD977A is a high speed, low power 16-bit A/D
converter that operates from a single 5 V supply. The AD977A
has a throughput rate of 200 kSPS whereas the AD977 has a
throughput rate of 100 kSPS. Each part contains a successive
approximation, switched capacitor ADC, an internal 2.5 V
reference, and a high speed serial interface. The ADC is factory
calibrated to minimize all linearity errors. The AD977/AD977A is
specified for full scale bipolar input ranges of ±10 V, ±5 V and3.3 V, and unipolar ranges of 0 V to 10 V, 0 V to 5 V and
0 V to 4 V.
The AD977/AD977A is comprehensively tested for ac param-
eters such as SNR and THD, as well as the more traditional dc
parameters of offset, gain and linearity.
PRODUCT HIGHLIGHTSFast Throughput
The AD977/AD977A is a high speed, 16-bit ADC based on
a factory calibrated switched capacitor architecture.Single-Supply Operation
The AD977/AD977A operates from a single 5 V supply and
dissipates only 100 mW max.Comprehensive DC and AC Specifications
In addition to the traditional specifications of offset, gain
and linearity, the AD977/AD977A is fully tested for SNR
and THD.
AD977/AD977A
NOTESLSB means Least Significant Bit. With a ±10 V input, one LSB is 305 µV.Typical rms noise at worst case transitions and temperatures.Measured with fixed resistors as shown in Figures 11, 12 and 13. Adjustable to zero. Tested at room temperature.Full-Scale Error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full scale transition voltage, and includes the effect of offset
error. For bipolar input ranges, the Full-Scale Error is the worst case of either the –Full Scale or +Full Scale code transition voltage errors. For unipolar input ranges, Full-Scale
Error is with respect to the +Full-Scale code transition voltage.
AD977–SPECIFICATIONS(–40�C to +85�C, FS = 100 kHz, VDIG = VANA = 5 V, unless otherwise noted)
AD977/AD977A
NOTESLSB means Least Significant Bit. With a ±10 V input, one LSB is 305 µV.Typical rms noise at worst case transitions and temperatures.Measured with fixed resistors as shown in Figures 11, 12 and 13. Adjustable to zero. Tested at room temperature.Full-Scale Error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full scale transition voltage, and includes the effect of offset
error. For bipolar input ranges, the Full-Scale Error is the worst case of either the –Full Scale or +Full Scale code transition voltage errors. For unipolar input ranges, Full-Scale
Error is with respect to the +Full-Scale code transition voltage.
AD977A–SPECIFICATIONS(–40�C to +85�C, FS = 200 kHz, VDIG = VANA = 5 V, unless otherwise noted)
AD977/AD977A–SPECIFICATIONS (Both Specs)
Specifications subject to change without notice.
TIMING SPECIFICATIONS
(AD977A: FS = 200 kHz, AD977: FS = 100 kHz, VDIG = VANA = 5 V, –40�C to +85�C)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
ABSOLUTE MAXIMUM RATINGS1
Analog Inputs
R1IN, R2IN , R3IN . . . . . . . . . . . . . . . . . . . . . . . . . . . .±25 V
CAP . . . . . . . . . . . . . . . . .+VANA + 0.3 V to AGND2 – 0.3 V
REF . . . . . . . . . . . . . . . . . . . . . Indefinite Short to AGND2,
. . . . . . . . . . . . . . . . . . . . . . . . .Momentary Short to VANA
Ground Voltage Differences
DGND, AGND1, AGND2 . . . . . . . . . . . . . . . . . . .±0.3 V
SupplyVoltages
VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 V
VDIG to VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±7 V
VDIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 V
Digital Inputs . . . . . . . . . . . . . . . . . . .–0.3 V to VDIG + 0.3 V
InternalPowerDissipation2
PDIP (N), SOIC (R), SSOP (RS) . . . . . . . . . . . . .700 mW
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150°C
Storage Temperature Range N, R . . . . . . . .–65°C to +150°C
Lead Temperature Range
(Soldering10sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Specification is for device in free air:
20-Lead PDIP: θJA = 100°C/W, θJC = 31°C/W,
20-Lead SOIC: θJA = 75°C/W, θJC = 24°C/W,
28-Lead SSOP: θJA = 109°C/W, θJC = 39°C/W.
PIN CONFIGURATIONS
SOIC and DIP SSOP
Figure 1.Load Circuit for Digital Interface Timing
ORDERING GUIDE
AD977AAN
AD977ABN
AD977ACN
AD977AR
AD977BR
AD977CR
AD977AAR
AD977ABR
AD977ACR
AD977ARS
AD977BRS
AD977CRS
AD977AARS
AD977ABRS
*N = 20-lead 300 mil plastic DIP; R = 20-lead SOIC; RS = 28-lead SSOP.
AD977/AD977A
PIN FUNCTION DESCRIPTIONS
DEFINITION OF SPECIFICATIONS
INTEGRAL NONLINEARITY ERROR (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as “negative full scale” occurs 1/2 LSB
before the first code transition. “Positive full scale” is defined as
a level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY ERROR (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
FULL-SCALE ERROR
The last + transition (from 011...10 to 011...11 for two’s
complement format) should occur for an analog voltage 1 1/2 LSB
below the nominal full scale (9.9995422 V for a ±10 V range).
The full-scale error is the deviation of the actual level of the last
transition from the ideal level.
BIPOLAR ZERO ERROR
Bipolar zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the
midscale output code.
UNIPOLAR ZERO ERROR
In unipolar mode, the first transition should occur at a level
1/2 LSB above analog ground. Unipolar zero error is the devia-
tion of the actual transition from that point.
SPURIOUS FREE DYNAMIC RANGE
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of a full-scale input signal and is
expressed in decibels.
SIGNAL TO (NOISE AND DISTORTION) (S/[N+D]) RATIO
S/(N+D) is the ratio of the rms value of the measured input
signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
FULL POWER BANDWIDTH
The full power bandwidth is defined as the full-scale input fre-
quency at which the S/(N+D) degrades to 60 dB, 10 bits of
accuracy.
APERTURE DELAY
Aperture delay is a measure of the acquisition performance, and
is measured from the falling edge of the R/C input to when the
input signal is held for a conversion.
TRANSIENT RESPONSE
The time required for the AD977/AD977A to achieve its rated
accuracy after a full-scale step function is applied to its input.
OVERVOLTAGE RECOVERY
The time required for the ADC to recover to full accuracy after
an analog input signal 150% of full-scale is reduced to 50% of
the full-scale value.
AD977/AD977A
CONVERSION CONTROL
The AD977/AD977A is controlled by two signals: R/C and CS.
When R/C is brought low, with CS low, for a minimum of 50 ns,
the input signal will be held on the internal capacitor array and
a conversion “n” will begin. Once the conversion process does
begin, the BUSY signal will go low until the conversion is com-
plete. Internally, the signals R/C and CS are OR’d together and
there is no requirement on which signal is taken low first when
initiating a conversion. The only requirement is that there be at
least 10 ns of delay between the two signals being taken low.
After the conversion is complete the BUSY signal will return
high and the AD977/AD977A will again resume tracking the
input signal. Under certain conditions the CS pin can be tied
Low and R/C will be used to determine whether you are initiat-
ing a conversion or reading data. On the first conversion, after
the AD977/AD977A is powered up, the DATA output will be
indeterminate.
Conversion results can be clocked serially out of the AD977/
AD977A using either an internal clock, generated by the
AD977/AD977A, or by using an external clock. The AD977/
AD977A is configured for the internal data clock mode by pull-
ing the EXT/INT pin low. It is configured for the external clock
mode by pulling the EXT/INT pin high.
INTERNAL DATA CLOCK MODE
The AD977/AD977A is configured to generate and provide the
data clock when the EXT/INT pin is held low. Typically CS will
be tied low and R/C will be used to initiate a conversion “n.”
During the conversion the AD977/AD977A will output 16 bits of
data, MSB first, from conversion “n-1” on the DATA pin. This
data will be synchronized with 16 clock pulses provided on the
DATACLK pin. The output data will be valid on both the
rising and falling edge of the data clock as shown in Figure 3.
After the LSB has been presented, the DATA pin will assume
whatever state the TAG input was at during the start of con-
version, and the DATACLK pin will stay low until another
conversion is initiated.
EXTERNAL DATA CLOCK MODE
The AD977/AD977A is configured to accept an externally sup-
plied data clock when the EXT/INT pin is held high. This mode
of operation provides several methods by which conversion
results can be read from the AD977/AD977A. The output data
from conversion “n-1” can be read during conversion “n,” or the
output data from conversion “n” can be read after the conver-
sion is complete. The external clock can be either a continuous
or discontinuous clock. A discontinuous clock can be either
Figure 2.Basic Conversion Timing
Figure 3.Serial Data Timing for Reading Previous Conversion Results with Internal Clock (CS, EXT/INT and TAG Set to
Logic Low)
normally low or normally high when inactive. In the case of the
discontinuous clock, the AD977/AD977A can be configured to
either generate or not generate a SYNC output (with a continu-
ous clock a SYNC output will always be produced).
Each of the methods will be described in the following sections
and are illustrated in Figures 4 through 9. It should be noted
that all timing diagrams assume that the receiving device is
latching data on the rising edge of the external clock. If the
falling edge of DATACLK is used then, in the case of a discon-
tinuous clock, one less clock pulse is required than shown in
Figures 4 through 7 to latch in a 16-bit word. Note that data is
valid on the falling edge of a clock pulse (for t13 greater than t18)
and the rising edge of the next clock pulse.
The AD977 provides error correction circuitry that can correct
for an improper bit decision made during the first half of the
conversion cycle. Normally the occurrence of an incorrect bit
decision during a conversion cycle is irreversible. This error
occurs as a result of noise during the time of the decision or due
to insufficient settling time. As the AD977/AD977A is perform-
ing a conversion it is important that transitions not occur on
digital input/output pins or degradation of the conversion result
could occur. This is particularly important during the second
half of the conversion process. For this reason it is recommended
that when an external clock is being provided it be a discontinu-
ous clock that is not toggling during the time that BUSY is low
or, more importantly, that it does not transition during the latter
half of BUSY low.
EXTERNAL DISCONTINUOUS CLOCK DATA READ
AFTER CONVERSION NO SYNC OUTPUT GENERATED
Figure 4 illustrates the method by which data from conversion
“n” can be read after the conversion is complete using a discon-
tinuous external clock without the generation of a SYNC
output. After a conversion is complete, indicated by BUSY
returning high, the result of that conversion can be read while
CS is Low and R/C is high. In this mode CS can be tied low.
The MSB will be valid on the first falling edge and the second
rising edge of DATACLK. The LSB will be valid on the 16th
falling edge and the 17th rising edge of DATACLK. A mini-
mum of 16 clock pulses are required for DATACLK if the
receiving device will be latching data on the falling edge of
DATACLK. A minimum of 17 clock pulses are required for
DATACLK if the receiving device will be latching data on the
rising edge of DATACLK. Approximately 40 ns after the 17th
rising edge of DATACLK (if provided) the DATA output pin
will reflect the state of the TAG input pin during the first rising
edge of DATACLK.
The advantage of this method of reading data is that it is not
being clocked out during a conversion and therefore conversion
performance is not degraded.
When reading data after the conversion is complete, with the
highest frequency permitted for DATACLK (15.15 MHz), and
with the AD977A, the maximum possible throughput is approxi-
mately 195 kHz and not the rated 200 kHz.
For details on use of the TAG input with this mode see the Use
of the Tag Feature section.
Figure 4.Conversion and Read Timing Using an External Discontinuous Data Clock (EXT/INT Set to Logic High, CS Set
to Logic Low)
AD977/AD977A
EXTERNAL DISCONTINUOUS CLOCK DATA READ
DURING CONVERSION NO SYNC OUTPUT
GENERATED
Figure 5 illustrates the method by which data from conversion
“n-1” can be read during conversion “n” while using a discon-
tinuous external clock, without the generation of a SYNC out-
put. After a conversion is initiated, indicated by BUSY going
low, the result of the previous conversion can be read while CS
is low and R/C is high. In this mode CS can be tied low. The
MSB will be valid on the 1st falling edge and the 2nd rising
edge of DATACLK. The LSB will be valid on the 16th falling
edge and the 17th rising edge of DATACLK. A minimum of 16
clock pulses are required for DATACLK if the receiving device
will be latching data on the falling edge of DATACLK. A mini-
mum of 17 clock pulses are required for DATACLK if the
receiving device will be latching data on the rising edge of
DATACLK. Approximately 40 ns after the 17th rising edge of
DATACLK (if provided) the DATA output pin will reflect the
state of the TAG input pin during the first rising edge of
DATACLK.
For both the AD977 and the AD977A the data should be
clocked out during the first half of BUSY so not to degrade
conversion performance. For the AD977 this requires use of a
4.8 MHz DATACLK or greater with data being read out as
soon as the conversion process begins. For the AD977A it
requires use of a 10 MHz DATACLK or greater.
It is not recommended that data be shifted through the TAG
input in this mode as it will certainly result in clocking of data
during the second half of the conversion.
EXTERNAL DISCONTINUOUS CLOCK DATA READ
AFTER CONVERSION WITH SYNC OUTPUT GENERATED
Figure 6 illustrates the method by which data from conversion
“n” can be read after the conversion is complete using a discon-
tinuous external clock, with the generation of a SYNC output.
What permits the generation of a SYNC output is a transition of
DATACLK while either CS is high or while both CS and R/C
are low. After a conversion is complete, indicated by BUSY
returning high, the result of that conversion can be read while
CS is Low and R/C is high. In this mode CS can be tied low. In
Figure 6 clock pulse #0 is used to enable the generation of a
SYNC pulse. The SYNC pulse is actually clocked out approxi-
mately 40 ns after the rising edge of clock pulse #1. The SYNC
pulse will be valid on the falling edge of clock pulse #1 and the
rising edge of clock pulse #2. The MSB will be valid on the
falling edge of clock pulse #2 and the rising edge of clock pulse
#3. The LSB will be valid on the falling edge of clock pulse #17
and the rising edge of clock pulse #18. Approximately 40 ns
after the rising edge of clock pulse #18 the DATA output pin
will reflect the state of the TAG input pin during the rising edge
of clock pulse #2. The advantage of this method of reading data
is that it is not being clocked out during a conversion and there-
fore conversion performance is not degraded.
When reading data after the conversion is complete, with the
highest frequency permitted for DATACLK (15.15 MHz),
and with the AD977A, the maximum possible throughput is
approximately 195 kHz and not the rated 200 kHz.
For details on use of the TAG input with this mode see the Use
of the TAG Input section.
R/C
BUSY
EXT
DATACLK
DATA
SYNC
Figure 5.Conversion and Read Timing for Reading Previous Conversion Results During A Conversion Using External
Discontinuous Data Clock (EXT/INT Set to Logic High, CS Set to Logic Low)
EXTERNAL DISCONTINUOUS CLOCK DATA READ
DURING CONVERSION WITH SYNC OUTPUT
GENERATED
Figure 7 illustrates the method by which data from conversion
“n-1” can be read during conversion “n” while using a discon-
tinuous external clock, with the generation of a SYNC output.
What permits the generation of a SYNC output is a transition of
DATACLK while either CS is High or while both CS and R/C
are low. In Figure 7 a conversion is initiated by taking R/C low
with CS tied low. While this condition exists a transition of
DATACLK, clock pulse #0, will enable the generation of a
SYNC pulse. Less then 83 ns after R/C is taken low the BUSY
output will go low to indicate that the conversion process has
began. Figure 7 shows R/C then going high and after a delay of
greater than 15 ns (t15) clock pulse #1 can be taken high to
request the SYNC output. The SYNC output will appear
approximately 40 ns after this rising edge and will be valid on
the falling edge of clock pulse #1 and the rising edge of clock
pulse #2. The MSB will be valid approximately 40 ns after the
rising edge of clock pulse #2 and can be latched off either the
falling edge of clock pulse #2 or the rising edge of clock pulse
#3. The LSB will be valid on the falling edge of clock pulse #17
and the rising edge of clock pulse #18. Approximately 40 ns
after the rising edge of clock pulse #18, the DATA output
pin will reflect the state of the TAG input pin during the
rising edge of clock pulse #2.
Figure 6.Conversion and Read Timing Using An External Discontinuous Data Clock (EXT/INT Set to Logic High, CS Set
to Logic Low)
BUSY
R/C
EXT
DATACLK
DATA
SYNC
AD977/AD977A
For both the AD977 and the AD977A the data should be
clocked out during the first half of BUSY so not to degrade
conversion performance. For the AD977 this requires use of a
4.8 MHz DATACLK or greater, with data being read out as
soon as the conversion process begins. For the AD977A it
requires use of a 10 MHz DATACLK or greater.
It is not recommended that data be shifted through the TAG
input in this mode as it will certainly result in clocking of data
during the second half of the conversion.
EXTERNAL CONTINUOUS CLOCK DATA READ AFTER
CONVERSION WITH SYNC OUTPUT GENERATED
Figure 8 illustrates the method by which data from conversion
“n” can be read after the conversion is complete using a con-
tinuous external clock, with the generation of a SYNC output.
What permits the generation of a SYNC output is a transition of
DATACLK while either CS is high or while both CS and R/C are
low.
With a continuous clock the CS pin cannot be tied low as it
could be with a discontinuous clock. Use of a continuous clock,
while a conversion is occurring, can increase the DNL and
Transition Noise of the AD977/AD977A.
After a conversion is complete, indicated by BUSY returning
high, the result of that conversion can be read while CS is low
and R/C is high. In Figure 8 clock pulse #0 is used to enable the
generation of a SYNC pulse. The SYNC pulse is actually clocked
out approximately 40 ns after the rising edge of clock pulse #1.
The SYNC pulse will be valid on the falling edge of clock pulse
#1 and the rising edge of clock pulse #2. The MSB will be valid
on the falling edge of clock pulse #2 and the rising edge of clock
pulse #3. The LSB will be valid on the falling edge of clock
pulse #17 and the rising edge of clock pulse #18. Approximately
50 ns after the rising edge of clock pulse #18 the DATA output
pin will reflect the state of the TAG input pin during the rising
edge of clock pulse #2.
When reading data after the conversion is complete, with the
highest frequency permitted for DATACLK (15.15 MHz) and,
with the AD977A, the maximum possible throughput is approxi-
mately 195 kHz and not the rated 200 kHz.
For details on use of the TAG input with this mode see the Use
of the TAG Input section.
Figure 8.Conversion and Read Timing Using an External Continuous Data Clock (EXT/INT Set to Logic High)

Partno	Mfg	Dc	Qty	Available	Descript
AD977	AD	N/a	6	avai	16-Bit, 100 kSPS, Serial I/O A/D Converter
AD977A	AD	N/a	11	avai	16-Bit, 200 kSPS, Serial I/O A/D Converter