AD976AAN ,16-Bit, 100 kSPS/200 kSPS BiCMOS A/D ConvertersSPECIFICATIONS V = V = +5 V unless otherwise noted)DIG ANA AD976A AD976B A ..
AD976AAN ,16-Bit, 100 kSPS/200 kSPS BiCMOS A/D ConvertersSpecifications.parameters of offset, gain and linearity.The AD976/AD976A is factory calibrated and ..
AD976AANZ , 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters
AD976AANZ , 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters
AD976AANZ , 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters
AD976AAR ,16-Bit, 100 kSPS/200 kSPS BiCMOS A/D ConvertersSpecifications.parameters of offset, gain and linearity.The AD976/AD976A is factory calibrated and ..
ADS8365IPAGRG4 ,Brown Corporation - 16-Bit, 250kSPS, 6-Channel, Simultaneous Sampling SAR ANALOG-TO-DIGITAL CONVERTERS
ADS8365IPAGRG4 ,Brown Corporation - 16-Bit, 250kSPS, 6-Channel, Simultaneous Sampling SAR ANALOG-TO-DIGITAL CONVERTERS
ADS8370IBRHPR ,16-Bit 600KSPS Serial ADC with Ref and Unipolar Pseudo Diff Input 28-VQFN -40 to 85SLAS450–JUNE 2005These devices have limited built-in ESD protection. The leads should be shorted to ..
ADS8370IBRHPRG4 ,16-Bit 600KSPS Serial ADC with Ref and Unipolar Pseudo Diff Input 28-VQFN -40 to 85MAXIMUM RATINGS(1)over operating free-air temperature range unless otherwise notedUNIT+IN to AGND – ..
ADS8370IBRHPT ,16-Bit 600KSPS Serial ADC with Ref and Unipolar Pseudo Diff Input 28-VQFN -40 to 85maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
ADS8370IRHPT ,16-Bit 600KSPS Serial ADC with Ref and Unipolar Pseudo Diff Input 28-VQFN -40 to 85SLAS450–JUNE 2005SPECIFICATIONSAt –40°C to 85°C, +VA = +5 V, +VBD = +5 V or +VBD = +2.7 V, using in ..
AD976AAN-AD976AAR-AD976AARS-AD976ABN-AD976ABR-AD976ABRS-AD976ACN-AD976ACR-AD976ACRS-AD976AN-AD976AR-AD976ARS-AD976BN-AD976BR-AD976BRS-AD976CN
16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters
REV. C
16-Bit, 100 kSPS/200 kSPS
BiCMOS A/D Converters
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Fast 16-Bit ADC
200 kSPS Throughput – AD976A
100 kSPS Throughput – AD976
Single 5 V Supply Operation
Input Range: 610V
100 mW Max Power Dissipation
Choice of External or Internal 2.5 V Reference
High Speed Parallel Interface
On-Chip Clock
28-Lead Skinny DIP, SSOP or SOIC Packages
GENERAL DESCRIPTIONThe AD976/AD976A is a high speed, low power 16-bit A/D
converter that operates from a single 5V supply. The part con-
tains a successive approximation, switched capacitor ADC, an
internal 2.5V reference and a high speed parallel interface. The
ADC is factory calibrated to minimize all linearity errors. The
analog full-scale input is the standard industrial range of –10 V.
The AD976/AD976A is comprehensively tested for ac param-
eters such as SNR and THD, as well as the more traditional
parameters of offset, gain and linearity.
The AD976/AD976A is fabricated on Analog Devices’ propri-
etary BiCMOS process, which has high performance bipolar
devices along with CMOS transistors.
The AD976/AD976A is available in skinny 28-lead DIP, SSOP
and SOIC packages.
PRODUCT HIGHLIGHTSFast Throughput.
The AD976/AD976A is a high speed (100 kSPS/200kSPS
throughput rates respectively), 16-bit ADC based on a
switched capacitor architecture.Single-Supply Operation.
The AD976/AD976A operates from a single 5 V supply and
dissipates only 100 mW max.Comprehensive DC and AC Specifications.
The AD976/AD976A is factory calibrated and fully tested for
SNR and THD as well as the traditional specifications of
offset, gain and linearity.Complete A/D Solution.
The AD976/AD976A offers a highly integrated solution
containing an accurate ADC, reference and on-chip clock.
AD976/AD976A
AD976A–SPECIFICATIONSNOTESLSB means least significant bit. With a –10 V input, one LSB is 305 mV.Typical rms noise at worst case transitions and temperatures.Measured with fixed resistors as shown in Figure 5 (AD976) and Figure 6 (AD976A). Adjustable to zero as shown in Figure 7.Full-scale error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full-scale transition voltage and includes the effect
of offset error. The full-scale error is the worst case of either the –full-scale or +full-scale code transition voltage errors.fIN = 20 kHz (AD976) and fIN = 45 kHz (AD976A), 0.5 dB down, unless otherwise noted.All specifications in dB are referred to a full scale –10 V input.Full-power bandwidth is defined as full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB or 10 bits of accuracy.
(–408C to +858C, FS = 200 kHz, Ref = Internal Reference, VDIG = VANA = +5V unless
otherwise noted)
AD976/AD976A
AD976–SPECIFICATIONSAC ACCURACY
DIGITAL INPUTS
NOTESLSB means least significant bit. With a –10 V input, one LSB is 305 mV.Typical rms noise at worst case transitions and temperatures.Measured with fixed resistors as shown in Figure 5 (AD976) and Figure 6 (AD976A). Adjustable to zero as shown in Figure 7.Full-scale error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full-scale transition voltage and includes the effect
of offset error. The full-scale error is the worst case of either the –full-scale or +full-scale code transition voltage errors.fIN = 20 kHz (AD976) and fIN = 45 kHz (AD976A), 0.5 dB down, unless otherwise noted.All specifications in dB are referred to a full scale –10 V input.Full-power bandwidth is defined as full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB or 10 bits of accuracy.
(–408C to +858C, FS = 100 kHz, Ref = Internal Reference,
VDIG = VANA = +5V unless otherwise noted)
AD976/AD976APOWER SUPPLIES
TEMPERATURE RANGE
Specifications subject to change without notice.
TIMING SPECIFICATIONS(AD976A: FS = 200kHz; AD976: FS = 100kHz; –408C to +858C, VDIG = VANA = +5 V unless otherwise noted)Data Valid Delay after R/C Low (AD976A/AD976)
BUSY Low (AD976A/AD976)
Aperture Delay
Conversion Time (AD976A/AD976)
Bus Relinquish Time
BUSY Delay after Data Valid (AD976A/AD976)
Previous Data Valid after R/C Low (AD976A/AD976)
Time Between Conversions (AD976A/AD976)
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1Analog Inputs
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 V
CAP . . . . . . . . . . . . . . . . +VANA + 0.3 V to AGND2 – 0.3 V
REF . . . . . . . . . . . . . . . . . . . . . Indefinite Short to AGND2
Ground Voltage Differences
DGND, AGND1, AGND2 . . . . . . . . . . . . . . . . . . . . –0.3 V
SupplyVoltages
VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VDIG to VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V
VDIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Digital Inputs . . . . . . . . . . . . . . . . . . . –0.3 V to VDIG + 0.3 V
InternalPowerDissipation2
PDIP (N), SOIC (R), SSOP (RS) . . . . . . . . . . . . . 700 mW
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature Range (N, R, RS) . . . –65°C to +150°C
Lead Temperature Range
(Soldering10sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air:
28-Lead PDIP: qJA = 74°C/W; qJC = 24°C/W,
28-Lead SOIC: qJA = 72°C/W; qJC = 23°C/W,
28-Lead SSOP: qJA = 109°C/W; qJC = 39°C/W.
ORDERING GUIDE
PIN CONFIGURATION
DIP, SOIC and SSOP Packages
VIN
BUSY
VANA
VDIG
AGND1
REF
CAP
D0 (LSB)
BYTE
R/CAGND2
D15 (MSB)
D14
D13
D12
D11D3
D10
DGND
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
1.6mA
OUTPUT
PIN
500mA
+2.1VFigure 1.Load Circuit for Digital Interface Timing
AD976/AD976A
PIN FUNCTION DESCRIPTIONS
DEFINITION OF SPECIFICATIONS
INTEGRAL NONLINEARITY ERROR (INL)Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” to “positive full
scale.” The point used as negative full scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY ERROR (DNL)In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
6 FULL-SCALE ERROR
The last + transition (from 011. . .10 to 011. . .11) should
occur for an analog voltage 1 1/2 LSB below the nominal full
scale (9.9995422 V for a –10 V range). The full-scale error is
the deviation of the actual level of the last transition from the
BIPOLAR ZERO ERRORBipolar zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the midscale
output code.
INPUT BANDWIDTHThe input bandwidth is that frequency at which the amplitude
of the reconstructed fundamental is reduced by 3 dB for a full-
scale input.
FULL-POWER BANDWIDTHFull-power bandwidth is defined as the full-scale input fre-
quency at which signal to (Noise + Distortion) degrades todB, as 10 bits of accuracy.
APERTURE DELAYAperture delay is a measure of the Sample-and-Hold Amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for a conversion.
APERTURE JITTERAperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
TRANSIENT RESPONSEThe time required for the AD976/AD976A to achieve its rated
accuracy after a full-scale step function is applied to its input.
OVERVOLTAGE RECOVERYThe time required for the ADC to recover to full accuracy after
an analog input signal 150% of full-scale is reduced to 50% of
the full-scale value.
Signal-to-(Noise Plus Distortion Ratio) (S/[N+D])S/(N+D) is the measured signal-to-noise plus distortion ratio at
the output of the ADC. The signal is the rms magnitude of the
fundamental. Noise plus distortion is the rms sum of all of the
nonfundamental signals and harmonics to half the sampling rate
excluding dc. The S/(N+D) is dependent upon the number of
quantization levels. The more levels, the lower the quantization
noise. The theoretical S/(N+D) for a sine wave input signal can
be calculated using the following:
S/(N+D) = (6.02N + 1.76) dB(1)
where N is the number of bits.
Thus, for an ideal 16 bit converter, S/(N+D) = 98 dB.
The output spectrum from the ADC is evaluated by applying a
low noise, low distortion sine wave signal to the VIN pin and
sampling at a 200kHz throughput rate. By generating a Fast
Fourier Transform (FFT) plot, the S/(N+D) data can then be
obtained. Figure 10 shows a typical 2048-point FFT plot with
an input signal of 45kHz and a sampling rate of 200kHz. The
S/(N+D) obtained from this graph is 86.23 dB.
Since the measured S/(N+D) is less than the theoretical value, it
is possible to get a measure of performance expressed in effective
number of bits (ENOB).
ENOB = ((S/(N+D) – 1.76) / 6.02)
Thus for an input signal of 45kHz, the typical ENOB is 14.
TOTAL HARMONIC DISTORTION (THD)THD is the ratio of the rms sum of the harmonics to the rms
value of the fundamental. For the AD976/AD976A, THD is
defined as:
where V1 is the rms amplitude of the fundamental, and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through
sixth harmonics. The THD is also derived from the FFT plot of
the ADC output spectrum shown in Figure 10 and is seen there
as –105.33 dB.
Spurious Free Dynamic Range (SPFD)The spurious free dynamic range is defined as the difference, in
dB, between the peak spurious or harmonic component in the
ADC output spectrum (up to FS/2 and excluding dc) and the rms
value of the fundamental. Normally, the value of this specification
will be determined by the largest harmonic in the spectrum. The
typical SPFD for the AD976/AD976A is –100 dB and can be
seen in Figure 10.
FUNCTIONAL DESCRIPTIONThe AD976/AD976A is a high speed, low power, 16-bit sam-
pling, analog-to-digital converter that can operate from a single
+5 volt power supply. The AD976/AD976A uses laser trimmed
scaling input resistors to provide an industry standard –10 volt
input range. With a 100/200kSPS throughput rate and a paral-
lel interface, the AD976/AD976A is capable of connecting di-
rectly to digital signal processors and microcontrollers.
The AD976/AD976A employs a successive-approximation
technique to determine the value of the analog input voltage.
Instead of using the traditional laser-trimmed resistor-ladder
approach, however, this device uses a capacitor array charge
distribution technique. Binary weighted capacitors subdivide the
input sample to perform the actual analog-to-digital conversion.
The capacitor array eliminates variation in the linearity of the
device due to temperature-induced mismatches of resistor val-
ues. As a result of having an on-chip capacitor array, there is no
need for additional external circuitry to perform the sample/hold
function.
Initial errors in capacitor matching are eliminated at the time of
manufacturing. Calibration coefficients are calculated that cor-
rect for capacitor mismatches and are stored in on-chip thin-film
resistors that act as ROM. As a conversion is occurring, the appro-
priate calibration coefficients are read out of ROM. The accumu-
lated coefficients are then used to adjust and improve conversion
accuracy. Any initial offset error is also trimmed out during
factory calibration. With the addition of an onboard reference
the AD976/AD976A provides a complete 16-bit A/D solution.
AD976/AD976A
DATA
BUS
BUSY
R/CFigure 2.Conversion Timing with Outputs Enabled After Conversion (CS Tied Low)
BUSY
R/C
DATA
BUSFigure 3.Using CS to Control Conversion and Read Timing
CONVERSION CONTROLThe AD976/AD976A is controlled by two signals: R/C and CS,
as shown in Figures 2 and 3. To initiate a conversion and place
the sample/hold circuit into the hold state, both the R/C and CS
signals must be brought low for no less than 50 ns. Once the
conversion process begins, the BUSY signal will go Low until
the conversion is complete. At the end of a conversion, BUSY
will return High, and the resulting valid data will be available on
the data bus. On the first conversion after the AD976/AD976A
is powered up, the DATA output will be indeterminate.
The AD976/AD976A exhibits two modes of conversion. In the
mode demonstrated in Figure 2, conversion timing is controlled
by a negative-going R/C signal, at least 50 ns wide. In this mode
the CS pin is always tied low, and the only limit placed on how
long the R/C signal can remain low is the desired sampling rate.
Less than 83 ns after the initiation of a conversion, the BUSY
signal will be brought low and remain low until the conversion is
complete and the output shift registers have been updated with
the new Binary Twos Complement data.
Figure 3 demonstrates the AD976/AD976A conversion timing,
using CS to control both the conversion process and the reading
of output data. To operate in this mode, the R/C signal should
be brought low no less than 10ns before the falling edge of a CS
pulse (50 ns wide) is applied to the ADC. Once these two pulses
are applied, BUSY will go low and remain low until a conver-
sion is complete. After a maximum of 4 ms (AD976A only),
BUSY will again return high, and parallel data will be valid on
the ADC outputs. To achieve the maximum 100kHz/200kHz
throughput rate of the part, the negative going R/C and CS
control signals should be applied every 5ms (AD976A). It should
also be noted that although all R/C and CS commands will be
ignored once a conversion has begun, these inputs can be
asserted during a conversion; i.e., a read during conversion can
be performed. Voltage transients on these inputs could feed
through to the analog circuitry and affect conversion results.
