AD9767AST Fast Delivery |IC PHOENIX CO.,LIMITED

AD9767AST ,14-Bit, 125 MSPS Dual TxDAC+ D/A ConverterSPECIFICATIONSMIN MAX OUTFSParameter Min Typ Max UnitsRESOLUTION 14 Bits1DC ACCURACYIntegral Linear ..
AD9768JD ,Ultrahigh Speed IC D/A ConverterSPECIFICATIONSinput levels; nominal power supplies; R = 50 V; R = 220 V; V = 0 V)L SET RETParameter ..
AD9768SD ,Ultrahigh Speed IC D/A ConverterGENERAL DESCRIPTIONThe Analog Devices AD9768SD D/A converter is a monolithiccurrent-output converte ..
AD976A ,16-Bit, 200 kSPS, Parallel I/O A/D ConverterSPECIFICATIONS V = V = +5 V unless otherwise noted)DIG ANA AD976A AD976B A ..
AD976AAN ,16-Bit, 100 kSPS/200 kSPS BiCMOS A/D ConvertersSPECIFICATIONS V = V = +5 V unless otherwise noted)DIG ANA AD976A AD976B A ..
AD976AAN ,16-Bit, 100 kSPS/200 kSPS BiCMOS A/D ConvertersSpecifications.parameters of offset, gain and linearity.The AD976/AD976A is factory calibrated and ..
ADS8364Y/250 ,16-Bit 250 kSPS 6 ADCs, Parallel Out, W/6 x FIFO W/6 Ch.MAXIMUM RATINGSELECTROSTATICAbsolute
ADS8364Y/250G4 ,6-Channel Simultaneous Sampling SAR ADC, 16-bits with 250kSPS for Motor and Power Control 64-TQFP -40 to 85ELECTRICAL CHARACTERISTICS (Cont.)Over recommended operating free-air temperature range at –40°C to ..
ADS8364Y/250G4 ,6-Channel Simultaneous Sampling SAR ADC, 16-bits with 250kSPS for Motor and Power Control 64-TQFP -40 to 85Maximum Ratings over operating free-air temperature (unless(1)otherwise noted) DISCHARGE SENSITIVIT ..
ADS8364Y/2K ,16-Bit 250 kSPS 6 ADCs, Parallel Out, W/6 x FIFO W/6 Ch..PACKAGE DISSIPATION RATING TABLEDERATINGFACTOR T ≤ +25°CT = +70°CT = +85°CA A AABOVE POWER POWER P ..
ADS8365IPAG ,16-Bit 250kSPS 6-Ch Simultaneous Sampling SAR ADC 64-TQFP -40 to 85ELECTRICAL CHARACTERISTICS: 100kSPSOver recommended operating free-air temperature range at –40°C t ..
ADS8365IPAGR ,16-Bit 250kSPS 6-Ch Simultaneous Sampling SAR ADC 64-TQFP -40 to 85This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated cir ..

AD9767AST
14-Bit, 125 MSPS Dual TxDAC+ D/A Converter
REV. B
14-Bit, 125 MSPS
Dual TxDAC+® D/A Converter
FUNCTIONAL BLOCK DIAGRAM
FEATURES
14-Bit Dual Transmit DAC
125 MSPS Update Rate
Excellent SFDR and IMD: 82 dBc
Excellent Gain and Offset Matching: 0.1%
Fully Independent or Single Resistor Gain Control
Dual Port or Interleaved Data
On-Chip 1.2 V Reference
Single 5 V or 3 V Supply Operation
Power Dissipation: 380mW @ 5 V
Power-Down Mode: 50 mW @ 5 V
48-Lead LQFP
APPLICATIONS
Communications
Base Stations
Digital Synthesis
Quadrature Modulation
PRODUCT DESCRIPTION
The AD9767 is a dual port, high speed, two channel, 14-bit
CMOS DAC. It integrates two high quality 14-bit TxDAC+
cores, a voltage reference and digital interface circuitry into a small
48-lead LQFP package. The AD9767 offers exceptional ac and
dc performance while supporting update rates up to 125 MSPS.
The AD9767 has been optimized for processing I and Q data in
communications applications. The digital interface consists of
two double-buffered latches as well as control logic. Separate
write inputs allow data to be written to the two DAC ports
independent of one another. Separate clocks control the update
rate of the DACs.
A mode control pin allows the AD9767 to interface to two sep-
arate data ports, or to a single interleaved high speed data port.
In interleaving mode the input data stream is demuxed into its
original I and Q data and then latched. The I and Q data is then
converted by the two DACs and updated at half the input data
rate.
The GAINCTRL pin allows two modes for setting the full-scale
current (IOUTFS) of the two DACs. IOUTFS for each DAC can be
set independently using two external resistors, or IOUTFS for both
DACs can be set by using a single external resistor.**
The DACs utilize a segmented current source architecture com-
bined with a proprietary switching technique to reduce glitch
energy and to maximize dynamic accuracy. Each DAC provides
differential current output thus supporting single-ended or
differential applications. Both DACs can be simultaneously
updated and provide a nominal full-scale current of 20 mA. The
full-scale currents between each DAC are matched to within
0.1%.
The AD9767 is manufactured on an advanced low cost CMOS
process. It operates from a single supply of 3.0 V to 5.0 V and
consumes 380 mW of power.
PRODUCT HIGHLIGHTSThe AD9767 is a member of a pin-compatible family of dual
TxDACs providing 8-, 10-, 12- and 14-bit resolution.Dual 14-Bit, 125 MSPS DACs:A pair of high performance
DACs optimized for low distortion performance provide for
flexible transmission of I and Q information.Matching:Gain matching is typically 0.1% of full scale, and
offset error is better than 0.02%.Low Power: Complete CMOS Dual DAC function operates
on 380 mW from a 3.0 V to 5.0 V single supply. The DAC
full-scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.On-Chip Voltage Reference: The AD9767 includes a 1.20 V
temperature-compensated bandgap voltage reference.Dual 14-Bit Inputs: The AD9767 features a flexible dual-
port interface allowing dual or interleaved input data.
TxDAC+ is a registered trademark of Analog Devices, Inc.
**Patent pending.
**Please see GAINCTRL Mode section, for important date code information on
this feature.
AD9767–SPECIFICATIONS
DC SPECIFICATIONS(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted.)
NOTESMeasured at IOUTA, driving a virtual ground.Nominal full-scale current, IOUTFS, is 32 times the IREF current.An external buffer amplifier with input bias current <100 nA should be used to drive any external load.Measured at fCLOCK = 25 MSPS and fOUT = 1.0 MHz.Measured at fCLOCK = 100 MSPS and fOUT = 1 MHz.Measured as unbuffered voltage output with IOUTFS = 20 mA and 50 Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz.±10% Power supply variation.
AD9767
DYNAMIC SPECIFICATIONS(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Differential Transformer Coupled
Output, 50 � Doubly Terminated, unless otherwise noted)
NOTESMeasured single-ended into 50 Ω load.
Specifications subject to change without notice.
AD9767–SPECIFICATIONS
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9767 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
DIGITAL SPECIFICATIONS
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
REFIO, FSADJ1, FSADJ2
GAINCTRL, SLEEP
Junction Temperature
Storage Temperature
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Figure 1.Timing Diagram for Dual and Interleaved Modes
See Dynamic and Digital sections for timing specifications.
(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted.)
ORDERING GUIDE
*ST = Thin Plastic Quad Flatpack.
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP
θJA = 91°C/W
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
DB0-P2
DB1-P2
DB2-P2
DB3-P2
DB4-P2
DB5-P2
DB6-P2
DB7-P2
DB8-P2
DB9-P2
DB10-P2
DB11-P2
DB13-P1 (MSB)
DB12-P1
DB11-P1
DB10-P1
DB9-P1
DB8-P1
DB7-P1
DB6-P1
DB5-P1
DB4-P1
DB3-P1
DB2-P1
MODEAVDDI
OUTA1
OUTB1
FSADJ1REFIOGAINCTRLFSADJ2I
OUTB2
OUTA2
ACOMSLEEP
DB1-P1DB0-P1DCOM1
DVDD1
WRT1/
IQWRT
CLK1/
IQCLK
CLK2/
IQRESET
WRT2/
IQSEL
DCOM2
DVDD2
DB13-P2DB12-P2
AD9767
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when the
inputs are all 0s. For IOUTB, 0 mA output is expected when all
inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C (ppm/°C).
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Figure 2.Basic AC Characterization Test Setup for AD9767, Testing Port 1 in Dual Port Mode, Using Independent
GAINCTRL Resistors on FSADJ1 and FSADJ2
Typical Characterization Curves
(AVDD = +5 V, DVDD = +3.3 V, IOUTFS = 20 mA, 50 � Doubly Terminated Load, Differential Output, TA = +25�C, SFDR up to Nyquist, unless
otherwise noted.)
fOUT – MHz
SFDR
dBc
100110
Figure 3.SFDR vs. fOUT @ 0 dBFS
fOUT – MHz
SFDR
dBc2510152035
Figure 6.SFDR vs. fOUT @ 65 MSPS
Figure 9.Single-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/11
fOUT – MHz
SFDR
dBc
0.002.500.501.001.502.00
Figure 4.SFDR vs. fOUT @ 5 MSPS
fOUT – MHz
SFDR
dBc
0105020304070
Figure 7.SFDR vs. fOUT @ 125 MSPS
Figure 10.Single-Tone SFDR vs.
AOUT @ fOUT = fCLOCK/5
fOUT – MHz
SFDR
dBc21246810
Figure 5.SFDR vs. fOUT @ 25 MSPS
fOUT – MHz
SFDR
dBc102030
5152535
Figure 8.SFDR vs. fOUT and IOUTFS
@ 65 MSPS and 0 dBFS
Figure 11.Dual-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/7
AD9767
fCLOCK – MSPS
SINAD
dBc140406080100120
Figure 12.SINAD vs. fCLOCK and IOUTFS
@ fOUT = 5 MHz and 0 dBFS
TEMPERATURE – �C
SFDR
dBc
–40–20806020045100–60
Figure 15.SFDR vs. Temperature @
125 MSPS, 0 dBFS
FREQUENCY – MHz
dBm200–90
–1030
Figure 18.Dual-Tone SFDR
@ fCLK = 125 MSPS
CODE
INL
LSBs
2.5
Figure 13.Typical INL
Figure 16.Reference Voltage Drift
vs. Temperature
FREQUENCY – MHz
dBm200–90
–1030
Figure 19.Four-Tone SFDR
@ fCLK = 125 MSPS
Figure 14.Typical DNL
FREQUENCY – MHz
dBm200–90
–1030
Figure 17.Single-Tone SFDR
@ fCLK = 125 MSPS
FUNCTIONAL DESCRIPTION
Figure 20 shows a simplified block diagram of the AD9767.
The AD9767 consists of two DACs, each with its own indepen-
dent digital control logic and full-scale output current control.
Each DAC contains a PMOS current source array capable of
providing up to 20 mA of full-scale current (IOUTFS). The array
is divided into 31 equal currents that make up the five most
significant bits (MSBs). The next four bits, or middle bits,
consist of 15 equal current sources whose value is 1/16th of an
MSB current source. The remaining LSB is a binary weighted
fraction of the middle bit current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances the dynamic performance for multitone or low
amplitude signals and helps maintain the DAC’s high output
impedance (i.e., >100 kΩ).
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS differen-
tial current switches. The switches are based on a new architec-
ture that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the dif-
ferential current switches.
The analog and digital sections of the AD9767 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 3 V to 5.5 V range. The digital section,
which is capable of operating up to a 125 MSPS clock rate,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current sources,
the associated differential switches, a 1.20 V bandgap voltage
reference and two reference control amplifiers.
The full-scale output current of each DAC is regulated by sepa-
rate reference control amplifiers and can be set from 2 mA to
20 mA via an external resistor, RSET, connected to the Full
Scale Adjust (FSADJ) pin. The external resistor, in combination
with both the reference control amplifier and voltage reference
VREFIO, sets the reference current IREF, which is replicated to the
segmented current sources with the proper scaling factor. The
full-scale current, IOUTFS, is 32 × IREF.
WRT1/
IQWRT
DIGITAL DATA INPUTS
IREF1
IREF2
RL1A
50�
WRT2/
IQSEL
DB0 – DB13DB0 – DB13
Figure 20.Simplified Block Diagram
REFERENCE OPERATION
The AD9767 contains an internal 1.20 V bandgap reference.
This can easily be overridden by an external reference with no
effect on performance. REFIO serves as either an input or out-
put, depending on whether the internal or an external reference
is used. To use the internal reference, simply decouple the
REFIO pin to ACOM with a 0.1 µF capacitor. The internal
reference voltage will be present at REFIO. If the voltage at
REFIO is to be used elsewhere in the circuit, an external buffer
amplifier with an input bias current of less than 100 nA should
be used. An example of the use of the internal reference is
shown in Figure 21.
Figure 21.Internal Reference Configuration
An external reference can be applied to REFIO as shown in
Figure 22. The external reference may provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1µF
compensation capacitor is not required since the internal refer-
ence is overridden, and the relatively high input impedance of
REFIO minimizes any loading of the external reference.
AD9767
GAINCTRL MODE
The AD9767 allows the gain of each channel to be indepen-
dently set by connecting one RSET resistor to FSADJ1 and an-
other RSET resistor to FSADJ2. To add flexibility and reduce
system cost, a single RSET resistor can be used to set the gain of
both channels simultaneously.
When GAINCTRL is low (i.e., connected to AGND), the inde-
pendent channel gain control mode using two resistors is enabled.
In this mode, individual RSET resistors should be connected to
FSADJ1 and FSADJ2. When GAINCTRL is high (i.e., con-
nected to AVDD), the master/slave channel gain control mode
using one resistor is enabled. In this mode, a single RSET resistor
is connected to FSADJ1 and the resistor on FSADJ2 must be
removed.
NOTE: Only parts with date code of 9930 or later have the
Master/Slave GAINCTRL function. For parts with a date code
before 9930, Pin 42 must be connected to AGND, and the part
will operate in the two resistor, independent gain control mode.
REFERENCE CONTROL AMPLIFIER
Both of the DACs in the AD9767 contain a control amplifier
that is used to regulate the full-scale output current, IOUTFS.
The control amplifier is configured as a V-I converter as shown
in Figure 21, so that its current output, IREF, is determined
by the ratio of the VREFIO and an external resistor, RSET, as
stated in Equation 4. IREF is copied to the segmented current
sources with the proper scale factor to set IOUTFS as stated in
Equation 3.
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS from 2mA to 20 mA by setting IREF between 62.5µA
and 625µA. The wide adjustment range of IOUTFS provides
several benefits. The first relates directly to the power dissipa-
tion of the AD9767, which is proportional to IOUTFS (refer to
the Power Dissipation section). The second relates to the 20dB
adjustment, which is useful for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency,
small signal multiplying applications.
DAC TRANSFER FUNCTION
Both DACs in the AD9767 provide complementary current
outputs, IOUTA and IOUTB. IOUTA will provide a near full-scale
current output, IOUTFS, when all bits are high (i.e., DAC CODE
= 16383) while IOUTB, the complementary output, provides no
current. The current output appearing at IOUTA and IOUTB is
a function of both the input code and IOUTFS and can be
expressed as:
IOUTA = (DAC CODE /16384) × IOUTFS(1)
IOUTB = (16383 – DAC CODE)/16384) × IOUTFS(2)
where DAC CODE = 0 to 16383 (i.e., Decimal Representation).
As previously mentioned, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage,
VREFIO and external resistor RSET. It can be expressed as:
IOUTFS = 32 × IREF(3)
The two current outputs will typically drive a resistive load di-
rectly or via a transformer. If dc coupling is required, IOUTA and
IOUTB should be directly connected to matching resistive loads,
RLOAD, that are tied to analog common, ACOM. Note, RLOAD
may represent the equivalent load resistance seen by IOUTA or
IOUTB as would be the case in a doubly terminated 50 Ω or
75 Ω cable. The single-ended voltage output appearing at the
IOUTA and IOUTB nodes is simply:
VOUTA = IOUTA × RLOAD(5)
VOUTB = IOUTB × RLOAD(6)
Note the full-scale value of VOUTA and VOUTB should not exceed
the specified output compliance range to maintain specified
distortion and linearity performance.
VDIFF = (IOUTA – IOUTB) × RLOAD(7)
Substituting the values of IOUTA, IOUTB and IREF; VDIFF can be
expressed as:
VDIFF = {(2 × DAC CODE – 16383)/16384} ×
(32 × RLOAD/RSET) × VREFIO(8)
These last two equations highlight some of the advantages of
operating the AD9767 differentially. First, the differential opera-
tion will help cancel common-mode error sources associated
with IOUTA and IOUTB such as noise, distortion and dc offsets.
Second, the differential code dependent current and subsequent
voltage, VDIFF, is twice the value of the single-ended voltage
output (i.e., VOUTA or VOUTB), thus providing twice the signal
power to the load.
Note, the gain drift temperature performance for a single-ended
(VOUTA and VOUTB) or differential output (VDIFF) of the AD9767
can be enhanced by selecting temperature tracking resistors for
RLOAD and RSET due to their ratiometric relationship as shown in
Equation 8.
ANALOG OUTPUTS
The complementary current outputs in each DAC, IOUTA and
IOUTB, may be configured for single-ended or differential opera-
tion. IOUTA and IOUTB can be converted into complementary
single-ended voltage outputs, VOUTA and VOUTB, via a load resis-
tor, RLOAD, as described in the DAC Transfer Function section
by Equations 5 through 8. The differential voltage, VDIFF,
existing between VOUTA and VOUTB can also be converted to a
single-ended voltage via a transformer or differential amplifier
configuration. The ac performance of the AD9767 is optimum
and specified using a differential transformer coupled output in
which the voltage swing at IOUTA and IOUTB is limited to ±0.5V.
If a single-ended unipolar output is desirable, IOUTA should be
selected.
The distortion and noise performance of the AD9767 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can be
significantly reduced by the common-mode rejection of a trans-
former or differential amplifier. These common-mode error
sources include even-order distortion products and noise. The
enhancement in distortion performance becomes more signifi-
cant as the frequency content of the reconstructed waveform
increases. This is due to the first order cancellation of various
Performing a differential-to-single-ended conversion via a trans-
former also provides the ability to deliver twice the reconstructed
signal power to the load (i.e., assuming no source termination).
Since the output currents of IOUTA and IOUTB are complemen-
tary, they become additive when processed differentially. A
properly selected transformer will allow the AD9767 to provide
the required power and voltage levels to different loads.
The output impedance of IOUTA and IOUTB is determined by the
equivalent parallel combination of the PMOS switches associ-
ated with the current sources and is typically 100kΩ in parallel
with 5 pF. It is also slightly dependent on the output voltage
(i.e., VOUTA and VOUTB) due to the nature of a PMOS device.
As a result, maintaining IOUTA and/or IOUTB at a virtual ground
via an I-V op amp configuration will result in the optimum dc
linearity. Note the INL/DNL specifications for the AD9767
are measured with IOUTA maintained at a virtual ground via an
op amp.
IOUTA and IOUTB also have a negative and positive voltage com-
pliance range that must be adhered to in order to achieve opti-
mum performance. The negative output compliance range of
–1.0V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a break-
down of the output stage and affect the reliability of the AD9767.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from
its nominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an
IOUTFS = 2 mA. The optimum distortion performance for a
single-ended or differential output is achieved when the maxi-
mum full-scale signal at IOUTA and IOUTB does not exceed 0.5 V.
Applications requiring the AD9767’s output (i.e., VOUTA and/or
VOUTB) to extend its output compliance range should size RLOAD
accordingly. Operation beyond this compliance range will ad-
versely affect the AD9767’s linearity performance and subse-
quently degrade its distortion performance.
DIGITAL INPUTS
The AD9767’s digital inputs consist of two channels. For the
dual port mode, each DAC has its own dedicated 14-bit data
port, WRT line and CLK line. In the interleaved timing mode,
the function of the digital control pins changes as described in
the Interleaved Mode Timing section. The 14-bit parallel data
inputs follow straight binary coding where DB13 is the Most
Significant Bit (MSB) and DB0 is the Least Significant Bit
(LSB). IOUTA produces a full-scale output current when all data
bits are at Logic 1. IOUTB produces a complementary output
with the full-scale current split between the two outputs as a
function of the input code.
The digital interface is implemented using an edge-triggered
master slave latch. The DAC outputs are updated following
either the rising edge, or every other rising edge of the clock,
depending on whether dual or interleaved mode is being used.
The DAC outputs are designed to support a clock rate as high
as 125 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulsewidth. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transi-
DAC TIMING
The AD9767 can operate in two timing modes, dual and inter-
leaved, which are described below. The block diagram in Figure
25 represents the latch architecture in the interleaved timing mode.
DUAL PORT MODE TIMING
For the following section, refer to Figure 2.
When the mode pin is at Logic 1, the AD9767 operates in dual
port mode. The AD9767 functions as two distinct DACs. Each
DAC has its own completely independent digital input and
control lines.
The AD9767 features a double buffered data path. Data enters
the device through the channel input latches. This data is then
transferred to the DAC latch in each signal path. Once the data
is loaded into the DAC latch, the analog output will settle to its
new value.
For general consideration, the WRT lines control the channel
input latches and the CLK lines control the DAC latches. Both
sets of latches are updated on the rising edge of their respective
control signals.
The rising edge of CLK should occur before or simultaneously
with the rising edge of WRT. Should the rising edge of CLK
occur after the rising edge of WRT, a 2ns minimum delay should
be maintained from the rising edge of WRT to the rising edge of
CLK.
Timing speciﬁcations for dual port mode are given in Figures 23
and 24.
Figure 23.Dual Mode Timing
Figure 24.Dual Mode Timing
AD9767
INTERLEAVED MODE TIMING
For the following section, refer to Figure 25.
When the mode pin is at Logic 0, the AD9767 operates in inter-
leaved mode. WRT1 now functions as IQWRT and CLK1
functions as IQCLK. WRT2 functions as IQSEL and CLK2
functions as IQRESET.
Data enters the device on the rising edge of IQWRT. The logic
level of IQSEL will steer the data to either Channel Latch 1
(IQSEL = 1) or to Channel Latch 2 (IQSEL = 0).
When IQRESET is high, IQCLK is disabled. When IQRESET
goes low, the following rising edge on IQCLK will update both
DAC latches with the data present at their inputs. In the inter-
leaved mode IQCLK is divided by 2 internally. Following this
first rising edge, the DAC latches will only be updated on every
other rising edge of IQCLK. In this way, IQRESET can be used
to synchronize the routing of the data to the DACs.
As with the dual port mode, IQCLK should occur before or
simultaneously with IQWRT.
Figure 25.Latch Structure Interleaved Mode
Timing specifications for interleaved mode are given in Figures
26 and 27.
Figure 26.Interleaved Mode Timing
The digital inputs are CMOS-compatible with logic thresholds,
VTHRESHOLD, set to approximately half the digital positive supply
(DVDD) or
VTHRESHOLD = DVDD/2 (±20%)
The internal digital circuitry of the AD9767 is capable of oper-
ating over a digital supply range of 3 V to 5.5 V. As a result, the
digital inputs can also accommodate TTL levels when DVDD is
set to accommodate the maximum high level voltage of the TTL
drivers VOH(MAX). A DVDD of 3 V to 3.3 V will typically
ensure proper compatibility with most TTL logic families. Fig-
ure 28 shows the equivalent digital input circuit for the data and
clock inputs. The sleep mode input is similar with the exception
that it contains an active pull-down circuit, thus ensuring that
the AD9767 remains enabled if this input is left disconnected.
Since the AD9767 is capable of being updated up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. Operating the AD9767
with reduced logic swings and a corresponding digital supply
(DVDD) will result in the lowest data feedthrough and on-chip
digital noise. The drivers of the digital data interface circuitry
should be specified to meet the minimum setup and hold times
of the AD9767 as well as its required min/max input logic level
thresholds.
Digital signal paths should be kept short and run lengths matched
to avoid propagation delay mismatch. The insertion of a low
value resistor network (i.e., 20 Ω to 100 Ω) between the AD9767
digital inputs and driver outputs may be helpful in reducing any
overshooting and ringing at the digital inputs that contribute to
digital feedthrough. For longer board traces and high data up-
date rates, stripline techniques with proper impedance and
termination resistors should be considered to maintain “clean”
digital inputs.
The external clock driver circuitry should provide the AD9767
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a recon-
structed waveform. Thus, the clock input should be driven by
the fastest logic family suitable for the application.
Note that the clock input could also be driven via a sine wave,
which is centered around the digital threshold (i.e., DVDD/2)
and meets the min/max logic threshold. This will typically result
in a slight degradation in the phase noise, which becomes more
noticeable at higher sampling rates and output frequencies.
Also, at higher sampling rates, the 20% tolerance of the digital
logic threshold should be considered since it will affect the effec-
tive clock duty cycle and, subsequently, cut into the required
data setup and hold times.
INPUT CLOCK AND DATA TIMING RELATIONSHIP
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9767 is rising edge triggered, and so
exhibits SNR sensitivity when the data transition is close to this
edge. In general, the goal when applying the AD9767 is to make
the data transition close to the falling clock edge. This becomes
more important as the sample rate increases. Figure 29 shows
the relationship of SNR to clock placement with different
sample rates. Note that at the lower sample rates, much more
tolerance is allowed in clock placement, while much more care
must be taken at higher rates.
TIME OF DATA CHANGE RELATIVE TO
RISING CLOCK EDGE – ns
SNR
dBc–4–2023–3–141
Figure 29.SNR vs. Clock Placement @ fOUT = 20 MHz and
fCLK = 125 MSPS
SLEEP MODE OPERATION
The AD9767 has a power-down function that turns off the
output current and reduces the supply current to less than 8.5mA
over the specified supply range of 3.0 V to 5.5 V and tempera-
ture range. This mode can be activated by applying a Logic
Level “1” to the SLEEP pin. The SLEEP pin logic threshold is
equal to 0.5 × AVDD. This digital input also contains an active
pull-down circuit that ensures the AD9767 remains enabled if
this input is left disconnected. The AD9767 takes less thanns to power down and approximately 5 µs to power back up.
POWER DISSIPATION
The power dissipation, PD, of the AD9767 is dependent on
several factors that include: (1) The power supply voltages
(AVDD and DVDD), (2) the full-scale current output IOUTFS,
(3) the update rate fCLOCK, (4) and the reconstructed digital
input waveform. The power dissipation is directly proportional
to the analog supply current, IAVDD, and the digital supply cur-
rent, IDVDD. IAVDD is directly proportional to IOUTFS as shown
in Figure 30 and is insensitive to fCLOCK.
IOUTFS10
IAVDD2025
Figure 30.IAVDD vs. IOUTFS
Conversely, IDVDD is dependent on both the digital input wave-
form, fCLOCK, and digital supply DVDD. Figures 31 and 32
show IDVDD as a function of full-scale sine wave output ratios
(fOUT/fCLOCK) for various update rates with DVDD = 5 V and
DVDD = 3 V, respectively. Note how IDVDD is reduced by more
than a factor of 2 when DVDD is reduced from 5 V to 3V.
Figure 31.IDVDD vs. Ratio @ DVDD = 5 V
Figure 32.IDVDD vs. Ratio @ DVDD = 3 V
AD9767
APPLYING THE AD9767
Output Configurations
The following sections illustrate some typical output configura-
tions for the AD9767. Unless otherwise noted, it is assumed
that IOUTFS is set to a nominal 20 mA. For applications requir-
ing the optimum dynamic performance, a differential output
configuration is suggested. A differential output configuration
may consist of either an RF transformer or a differential op amp
configuration. The transformer configuration provides the opti-
mum high frequency performance and is recommended for any
application allowing for ac coupling. The differential op amp
configuration is suitable for applications requiring dc coupling,
a bipolar output, signal gain and/or level-shifting, within the
bandwidth of the chosen op amp.
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if IOUTA and/or IOUTB is connected to an appropriately-
sized load resistor, RLOAD, referred to ACOM. This configuration
may be more suitable for a single-supply system requiring a
dc coupled, ground referred output voltage. Alternatively, an
amplifier could be configured as an I-V converter, thus convert-
ing IOUTA or IOUTB into a negative unipolar voltage. This con-
figuration provides the best dc linearity since IOUTA or IOUTB
is maintained at a virtual ground. Note that IOUTA provides
slightly better performance than IOUTB.
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-to-
single-ended signal conversion as shown in Figure 33. A dif-
ferentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral con-
tent lies within the transformer’s passband. An RF transformer
such as the Mini-Circuits T1-1T provides excellent rejection
of common-mode distortion (i.e., even-order harmonics) and
noise over a wide frequency range. It also provides electrical
isolation and the ability to deliver twice the power to the load.
Transformers with different impedance ratios may also be used
for impedance matching purposes. Note that the transformer
provides ac coupling only.
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages appear-
ing at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetri-
cally around ACOM and should be maintained with the specified
output compliance range of the AD9767. A differential resistor,
RDIFF, may be inserted in applications where the output of the
transformer is connected to the load, RLOAD, via a passive
reconstruction filter or cable. RDIFF is determined by the trans-
former’s impedance ratio and provides the proper source termi-
nation that results in a low VSWR. Note that approximately half
the signal power will be dissipated across RDIFF.
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used to perform a differential-to-single-
ended conversion as shown in Figure 34. The AD9767 is con-
figured with two equal load resistors, RLOAD, of 25 Ω. The
differential voltage developed across IOUTA and IOUTB is con-
verted to a single-ended signal via the differential op amp con-
figuration. An optional capacitor can be installed across IOUTA
and IOUTB, forming a real pole in a low-pass filter. The addition
of this capacitor also enhances the op amps distortion perfor-
mance by preventing the DACs high slewing output from over-
loading the op amp’s input.
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differ-
ential op amp circuit using the AD8047 is configured to provide
some additional signal gain. The op amp must operate from a
dual supply since its output is approximately ±1.0V. A high
speed amplifier capable of preserving the differential perfor-
mance of the AD9767, while meeting other system level
objectives (i.e., cost, power), should be selected. The op
amp’s differential gain, its gain setting resistor values, and
full-scale output swing capabilities should all be considered
when optimizing this circuit.
Figure 34.DC Differential Coupling Using an Op Amp
The differential circuit shown in Figure 35 provides the neces-
sary level-shifting required in a single supply system. In this case
AVDD, which is the positive analog supply for both the AD9767
and the op amp, is also used to level-shift the differential output
of the AD9767 to midsupply (i.e., AVDD/2). The AD8055 is a
suitable op amp for this application.
Figure 35.Single Supply DC Differential Coupled Circuit
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
Figure 36 shows the AD9767 configured to provide a unipolar
output range of approximately 0V to +0.5 V for a doubly termi-
nated 50Ω cable since the nominal full-scale current, IOUTFS, of
20 mA flows through the equivalent RLOAD of 25Ω. In this case,

Partno	Mfg	Dc	Qty	Available	Descript
AD9767AST	AD	N/a	900	avai	14-Bit, 125 MSPS Dual TxDAC+ D/A Converter