AD9761ARS ,Dual 10-Bit TxDAC+⑩ with 2x Interpolation FiltersSPECIFICATIONS MIN MAX OUTFSParameter Min Typ Max UnitsRESOLUTION 10 Bits1DC ACCURACYIntegral Linea ..
AD9761ARSRL ,10-Bit, Complete, 40 MSPS, dual Transmit D/A ConverterSPECIFICATIONSMIN Max OUTFSParameter Min Typ Max UnitRESOLUTION 10 Bits1DC ACCURACY Integral Nonl ..
AD9761ARSZ ,10-Bit, Complete, 40 MSPS, dual Transmit D/A ConverterSPECIFICATIONS50 Doubly Terminated, unless otherwise noted.)Parameter ..
AD9762AR ,12-Bit, 125 MSPS TxDAC D/A ConverterSPECIFICATIONSMIN MAX OUTFS Parameter Min Typ Max UnitsRESOLUTION 12 Bits1DC ACCURACYIntegral Linea ..
AD9763AST ,10-Bit, 125 MSPS Dual TxDAC+ D/A Converterapplications. The digital interface consists oftwo double-buffered latches as well as control logic ..
AD9763AST ,10-Bit, 125 MSPS Dual TxDAC+ D/A ConverterSPECIFICATIONSMIN MAX OUTFSParameter Min Typ Max UnitsRESOLUTION 10 Bits1DC ACCURACYIntegral Linear ..
ADS8344NB ,16-Bit/ 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTERMAXIMUM RATINGSELECTROSTATIC+V to GND –0.3V to +6VCC Analog Inputs to GND ........ –0.3V to +V + 0 ..
ADS8344NBG4 ,16-Bit, 8-Channel Serial Output Sampling Analog-to-Digital Converter 20-SSOP -40 to 85¤ADS8344¤ADS8344ADS8344SBAS139E – SEPTEMBER 2000 – REVISED SEPTEMBER 200616-Bit, 8-Channel Serial O ..
ADS8344NG4 ,16-Bit, 8-Channel Serial Output Sampling Analog-to-Digital Converter 20-SSOP -40 to 85Electrical CharacteristicsREFADS8344Table for ranges.CH5 6 15 DOUT12 +V Power Supply, 2.7V to 5VCC1 ..
ADS8345 ,16-Bit, 8-Channel Serial Output Sampling Analog-to-Digital ConverterSBAS177C
ADS8345E ,16-Bit, 8-Channel Serial Output Sampling Analog-to-Digital ConverterELECTRICAL CHARACTERISTICS: +2.7VAt T = –40°C to +85°C, +V = +2.7V, V = +1.25V, f = 100kHz, and f ..
ADS8345E/2K5 ,16-Bit, 8-Channel Serial Output Sampling Analog-to-Digital ConverterMaximum Ratings”tion to complete device failure. Precision integrated circuitsmay cause permanent d ..
AD9761ARS
Dual 10-Bit TxDAC+⑩ with 2x Interpolation Filters
REV.A
Dual 10-Bit TxDAC+™
with 23 Interpolation Filters
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Complete 10-Bit, 40 MSPS Dual Transmit DAC
Excellent Gain and Offset Matching
Differential Nonlinearity Error:0.5 LSB
Effective Number of Bits:9.5
Signal-to-Noise and Distortion Ratio:59 dB
Spurious-Free Dynamic Range:71 dB
23 Interpolation Filters
20 MSPS/Channel Data Rate
Single Supply:+2.7 V to +5.5 V
Low Power Dissipation:200 mW (+3 V Supply @MSPS)
On-Chip Reference
28-Lead SSOP
PRODUCT DESCRIPTIONThe AD9761 is a complete dual channel, high speed, 10-bit
CMOS DAC. The AD9761 has been developed specifically for
use in wide bandwidth communication applications (e.g., spread
spectrum) where digital I and Q information is being processed
during transmit operations. It integrates two 10-bit, 40 MSPS
DACs, dual 2· interpolation filters, a voltage reference, and
digital input interface circuitry. The AD9761 supports aMSPS per channel input data rate that is then interpolated
by 2· up to 40 MSPS before simultaneously updating each
DAC.
The interleaved I and Q input data stream is presented to the
digital interface circuitry, which consists of I and Q latches as well
as some additional control logic. The data is de-interleaved back
into its original I and Q data. An on-chip state machine ensures the
proper pairing of I and Q data. The data output from each latch is
then processed by a 2· digital interpolation filter that eases the
reconstruction filter requirements. The interpolated output of each
filter serves as the input of their respective 10-bit DAC.
The DACs utilize a segmented current source architecture com-
bined with a proprietary switching technique to reduce glitch
energy and to maximize dynamic accuracy. Each DAC provides
differential current output thus supporting single-ended or
differential applications. Both DACs are simultaneously up-
dated and provide a nominal full-scale current of 10 mA. Also,
the full-scale currents between each DAC are matched to within
0.07 dB (i.e., 0.75%), thus eliminating the need for additional
gain calibration circuitry.
The AD9761 is manufactured on an advanced low cost CMOS
process. It operates from a single supply of 2.7 V to 5.5 V and
consumes 200 mW of power. To make the AD9761 complete it
also offers an internal 1.20 V temperature-compensated bandgap
reference.
TxDAC+ is a trademark of Analog Devices, Inc.
PRODUCT HIGHLIGHTSDual 10-Bit, 40 MSPS DACs:A pair of high performance
40 MSPS DACs optimized for low distortion performance
provide for flexible transmission of I and Q information.2· Digital Interpolation Filters:Dual matching FIR interpo-
lation filters with 62.5 dB stop band rejection precede each
DAC input thus reducing the DACs’ reconstruction filter
requirements.Low Power:Complete CMOS Dual DAC function operates
on a low 200 mW on a single supply from 2.7 V to 5.5 V.
The DAC full-scale current can be reduced for lower power
operation, and a sleep mode is provided for power reduction
during idle periods.On-Chip Voltage Reference:The AD9761 includes a 1.20 V
temperature-compensated bandgap voltage reference.Single 10-Bit Digital Input Bus:The AD9761 features a
flexible digital interface allowing each DAC to be addressed
in a variety of ways including different update rates.Small Package:The AD9761 offers the complete integrated
function in a compact 28-lead SSOP package.Product Family:The AD9761 Dual Transmit DAC has a
pair of Dual Receive ADC companion products, the AD9281
(8 bits) and AD9201 (10 bits).
AD9761–SPECIFICATIONS
DC SPECIFICATIONSMonotonicity (10 Bit)GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE
NOTESMeasured at IOUTA and QOUTA, driving a virtual ground.Nominal full-scale current, IOUTFS, is 16· the IREF current.Use an external amplifier to drive any external load.Measured at fCLOCK = 40 MSPS and fOUT = 1 MHz.Measured as unbuffered voltage output into 50 W RLOAD at IOUTA, IOUTB, QOUTA, and QOUTB, fCLOCK = 40 MSPS and fOUT = 8 MHz.
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 10 mA, unless otherwise noted)
AD9761
DYNAMIC SPECIFICATIONSAC LINEARITY TO NYQUIST
DIGITAL SPECIFICATIONSNOTEStCINV is an invalid window of 4ns duration beginning 1ns AFTER the rising edge of WRITE in which the rising edge of CLOCK MUST NOT occur.
Specifications subject to change without notice.
DB9–DB0
DAC
INPUTS
SELECT
WRITE
CLOCKtH
NOTES: WRITE AND CLOCK CAN BE TIED
TOGETHER. FOR TYPICAL EXAMPLES, REFER
TO DIGITAL INPUTS AND INTERLEAVED INTERFACE
CONSIDERATION SECTION.
(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 10 mA, Differential Transformer Coupled Output,
50 V Doubly Terminated, unless otherwise noted)
(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 10 mA unless otherwise noted)
AD9761
DIGITAL FILTER SPECIFICATIONSDIGITAL FILTER CHARACTERISTICS
NOTESExcludes SINX/X characteristic of DAC.Defined as the number of data clock cycles between impulse input and peak of output response.55 input clock periods from input to I DAC, 56 to Q DAC. Propagation delay is delay from data input to DAC update.
(TMIN to TMAX, AVDD = +2.7V to 5.5 V, DVDD = +2.7 V to 5.5 V, IOUTFS = 10 mA unless
otherwise noted)
FREQUENCY RESPONSE – DC to fCLOCK/2
OUTPUT – dBFS
–100Figure 2a.FIR Filter Frequency Response
TIME – Samples
NORMALIZED OUTPUTFigure 2b.FIR Filter Impulse Response
Table I.Integer Filter Coefficients for 43-Tap Halfband
FIR Filter
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ABSOLUTE MAXIMUM RATINGS**This is a stress rating only; functional operation of the device at these or any other conditions above
those listed in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance28-Lead SSOPJA = 109°C/W
Figure 3.Basic AC Characterization Test Setup
100V20pF20pF
*AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK.
MINI-CIRCUITS
T1-1T
TO HP3589A
SPECTRUM/NETWORK
ANALYZER
50V INPUT
100V20pF20pF
MINI-CIRCUITS
T1-1T
TO HP3589A
SPECTRUM/NETWORK
ANALYZER
50V INPUT0.1mF
+2.7V TO
5.5V
+2.7V TO
5.5V
AD9761
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
(MSB) DB9
IOUTB
IOUTA
COMP1
RESET/SLEEP
DB8
DB7
DB6
COMP2
AVDD
ACOMDB5
DB4
DB3
DB2
DB1
(LSB) DB0REFLO
REFIO
FSADJ
CLOCK
WRITE
SELECT
DVDD
QOUTB
DCOM
COMP3
QOUTA
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.
MonotonicityA D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset ErrorThe deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain ErrorThe difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance RangeThe range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature DriftTemperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per °C. For reference drift, the drift is reported in
ppm per °C.
Power Supply RejectionThe maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling TimeThe time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch ImpulseAsymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified the net area of the glitch in pV-s.
Channel IsolationChannel Isolation is a measure of the level of crosstalk between
channels. It is measured by producing a full-scale 8 MHz signal
output for one channel and measuring the leakage into the other
channel.
Spurious-Free Dynamic RangeThe difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic DistortionTHD is the ratio of the sum of the rms value of the first six
harmonic components to the rms value of the measured output
signal. It is expressed as a percentage or in decibels (dB).
Signal-to-Noise and Distortion (S/N+D, SINAD) RatioS/N+D is the ratio of the rms value of the measured output
signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/N+D is expressed in decibels.
Effective Number of Bits (ENOB)For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N,
the effective number of bits.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
PassbandFrequency band in which any input applied therein passes
unattenuated to the DAC output.
Stopband RejectionThe amount of attenuation of a frequency outside the passband
applied to the DAC, relative to a full-scale signal applied at the
DAC input within the passband.
Group DelayNumber of input clocks between an impulse applied at the
device input and peak DAC output current.
Impulse ResponseResponse of the device to an impulse applied to the input.
AD9761
START: 0HzSTOP: 40MHz
10dB – Div
–100Figure 4.Single-Tone SFDR (DC to
2fDATA, fCLOCK = 2fDATA)
Figure 7.“Out-of-Band” SFDR vs. fOUT
(fDATA/2 to 3/2 fDATA)
fOUT – MHz810Figure 10.SINAD/SFDR vs. IOUTFS
(DC to fDATA/2, Differential Output)
Typical AC Characterization Curves @ +5 V Supplies
(AVDD = +5 V, DVDD = +5 V, 50 V Doubly Terminated Load, TA = +258C, fCLOCK = 40 MSPS, unless otherwise noted, worst of I or Q output
performance shown)
fOUT – MHz2.010.04.06.08.0
ENOBFigure 5.SINAD (ENOBs) vs. fOUT (DC
to fDATA/2)
Figure 8.SINAD vs. AOUT (DC to
fDATA/2, Differential Output)
fOUT – MHz810Figure 11.SINAD/SFDR vs. IOUTFS
(DC to fDATA/2, Single-Ended Output)
fOUT – MHz5.010.0Figure 6.SFDR vs. fOUT (DC to fDATA/2)
Figure 9.SINAD vs. AOUT (DC to
fDATA/2, Single-Ended Output)
START: 0HzSTOP: 20MHz
10dB – Div
–95Figure 12.Wideband Spread-
Spectrum Spectral Plot (DC to fDATA)
Typical AC Characterization Curves @ +3 V Supplies
(AVDD = +3 V, DVDD = +3 V, 50 V Doubly Terminated Load, TA = +258C, fCLOCK = 10 MSPS, unless otherwise noted, worst of I or Q output
performance shown)
START: 0HzSTOP: 10MHz
10dB – DivFigure 13.Single-Tone SFDR (DC to
2fDATA, fCLOCK = 2fDATA)
fOUT – MHz0.52.51.01.52.0Figure 16.“Out-of-Band” SFDR vs.
fOUT (fDATA/2 to 3/2fDATA)
fOUT – MHz810Figure 19.SINAD/SFDR vs. IOUTFS (DC
to fDATA/2, Differential Output)
fOUT – MHz0.52.51.01.52.0
ENOBFigure 14.SINAD (ENOBs) vs. fOUT
(DC to fDATA/2)
AOUT – dBFS
–30–25–5–20–15–10Figure 17.SINAD vs. AOUT (DC to
fDATA/2, Differential Output)
Figure 20.SINAD/SFDR vs. IOUTFS
(DC to fDATA/2, Single-Ended Output)
Figure 15.SFDR vs. fOUT (DC to fDATA/2)
Figure 18.SINAD vs. AOUT (DC to
fDATA/2, Single-Ended Output)
Figure 21.Narrowband Spread-
Spectrum Spectral Plot (DC to fDATA)
AD9761
FUNCTIONAL DESCRIPTIONFigure 22 shows a simplified block diagram of the AD9761. The
AD9761 is a complete dual channel, high speed, 10-bit CMOS
DAC capable of operating up to a 40 MHz clock rate. It has
been optimized for the transmit section of wideband communi-
cation systems employing I and Q modulation schemes. Excel-
lent matching characteristics between channels reduces the need
for any external calibration circuitry. Dual matching 2· interpo-
lation filters included in the I and Q data path simplify any post,
bandlimiting filter requirements. The AD9761 interfaces with a
single 10-bit digital input bus that supports interleaved I and Q
input data.
ACOM
REFLO
FSADJ
IOUTA
IOUTB
WRITE INPUT
SELECT INPUT
DCOMDVDDCLOCK
REFIO
COMP1
COMP2
COMP3
QOUTA
QOUTB
AVDD
DAC DATA
INPUTS
(10 BITS)
SLEEPFigure 22.Dual DAC Functional Block Diagram
Referring to Figure 22, the AD9761 consists of an analog sec-
tion and a digital section. The analog section includes matched
I and Q 10-bit DACs, a 1.20 V bandgap voltage reference and a
reference control amplifier. The digital section includes: two 2·
interpolation filters; segment decoding logic; and some addi-
tional digital input interface circuitry. The analog and digital
sections of the AD9761 have separate power supply inputs (i.e.,
AVDD and DVDD) that can operate over a 2.7V to 5.5V
range.
Each DAC consists of a large PMOS current source array ca-
pable of providing up to 10 mA of full-scale current, IOUTFS.
Each array is divided into 15 equal currents that make up the
four most significant bits (MSBs). The next four bits or middle
bits consist of 15 equal current sources whose value are 1/16th
of an MSB current source. The remaining LSBs are binary
weighted fractions of the middle-bits current sources. All of
these current sources are switched to one or the other of two
output nodes (i.e., IOUTA or IOUTB) via PMOS differential
current switches.
The full-scale output current, IOUTFS, of each DAC is regulated
from the same voltage reference and control amplifier, thus
ensuring excellent gain matching and drift characteristics be-
tween DACs. IOUTFS can be set from 1 mA to 10 mA via an
external resistor, RSET. The external resistor in combination
with both the reference control amplifier and voltage reference,
VREFIO, sets the reference current, IREF, which is mirrored over
to the segmented current sources with the proper scaling factor.
IOUTFS is exactly sixteen times the value of IREF.
The I and Q DACs are simultaneously updated on the rising
edge of CLOCK with digital data from their respective 2· digi-
tal interpolation filters. The 2· interpolation filters essentially
multiplies the input data rate of each DAC by a factor of two,
relative to its original input data rate while simultaneously re-
ducing the magnitude of first image associated with the DAC’s
original input data rate. Since the AD9761 supports a single
10-bit digital bus with interleaved I and Q input data, the origi-
nal I and Q input data rate before interpolation is one-half the
CLOCK rate. After interpolation, the data rate into each I and
Q DAC becomes equal to the CLOCK rate.
The benefits of an interpolation filter are clearly seen in Figure
23, which shows an example of the frequency and time domain
representation of a discrete time sine wave signal before and
after it is applied to a digital interpolation filter. Images of the
sine wave signal appear around multiples of the DAC’s input
data rate as predicted by the sampling theory. These undesirable
images will also appear at the output of a reconstruction DAC,
although modified by the DAC’s sin(x)/(x) response. In many
bandlimited applications, these images must be suppressed by
an analog filter following the DAC. The complexity of this ana-
log filter is typically determined by the proximity of the desired
fundamental to the first image and the required amount of im-
age suppression.
FUNDAMENTAL
FUNDAMENTALDIGITAL
SUPPRESSED
"OLD"
1ST IMAGE
fCLOCK
1ST IMAGE
fCLOCK
fCLOCKfCLOCK
fCLOCK
DACs"SINX"
TIME DOMAIN
FREQUENCY DOMAIN
fCLOCK
fCLOCK
Referring to Figure 23, the “new” first image associated with the
DAC’s higher data rate after interpolation is “pushed” out fur-
ther relative to the input signal. The “old” first image associated
with the lower DAC data rate before interpolation is suppressed
by the digital filter. As a result, the transition band for the ana-
log reconstruction filter is increased thus reducing the complex-
ity of the analog filter.
The digital interpolation filters for I and Q paths are identical
43 tap halfband symmetric FIR filters. Each filter receives de-
interleaved I or Q data from the digital input interface. The
input CLOCK signal is internally divided by two to generate the
filter clock. The filters are implemented with two parallel paths
running at the filter clock rate. The output from each path is
selected on opposite phases of the filter clock, thus producing
interpolated filtered output data at the input clock rate. The
frequency response and impulse response of these filters are
shown in Figures 2a and 2b. Table I lists the idealized filter
coefficients that correspond to the filter’s impulse response.
The digital section of the AD9761 also includes an input inter-
face section designed to support interleaved I and Q input data
from a single 10-bit bus. This section de-interleaves the I and Q
input data while ensuring its proper pairing for the 2· interpola-
tion filters. A SLEEP/RESET input serves a dual function by
providing a reset function for this section as well as providing
power down functionality. Refer to the DIGITAL INPUT AND
INTERFACE CONSIDERATIONS and SLEEP/RESET
sections for a more detailed discussion.
DAC TRANSFER FUNCTIONEach I and Q DAC provides complementary current output
pins: IOUT(A/B) and QOUT(A/B) respectively. Note, QOUTA
and QOUTB operate identically to IOUTA and IOUTB.
IOUTA will provide a near full-scale current output, IOUTFS,
when all bits are high (i.e., DAC CODE = 1023) while IOUTB,
the complementary output, provides no current. The current
output of IOUTA and IOUTB are a function of both the input
code and IOUTFS and can be expressed as:
IIOUTA = (DAC CODE/1024) · IOUTFS(1)
IIOUTB = (1023 – DAC CODE)/1024 · IOUTFS(2)
where:
DAC CODE = 0 to 1023 (i.e., Decimal Representation).
As previously mentioned, IOUTFS is a function of the reference
current, IREF, which is nominally set by a reference, VREFIO, and
external resistor, RSET. It can be expressed as:
IOUTFS = 16 · IREF(3)
where:
IREF = VREFIO/RSET(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, which are tied to analog common, ACOM. Note,
RLOAD represents the equivalent load resistance seen by IOUTA
or IOUTB. The single-ended voltage output appearing at IOUTA
Note, the full-scale value of VIOUTA and VIOUTB should not
exceed the specified output compliance range to maintain speci-
fied distortion and linearity performance.
The differential voltage, VIDIFF, appearing across IOUTA and
IOUTB is:
VIDIFF =(IIOUTA – IIOUTB) · RLOAD(7)
Substituting the values of IIOUTA, IIOUTB, and IREF; VIDIFF can be
expressed as:
VIDIFF ={(2 DAC CODE – 1023)/1024)} ·
(16 RLOAD/RSET) · VREFIO(8)
These last two equations highlight some of the advantages of
operating the AD9761 differentially. First, differential operation
will help cancel common-mode error sources associated with
IIOUTA and IIOUTB such as noise and distortion. Second, the
differential code dependent current and subsequent voltage,
VIDIFF, is twice the value of the single-ended voltage output (i.e.,
VIOUTA or VIOUTB) thus providing twice the signal power to the
load.
REFERENCE OPERATIONThe AD9761 contains an internal 1.20 V bandgap reference
which can be easily disabled and overridden by an external
reference. REFIO serves as either an input or output depending
on whether the internal or an external reference is selected. If
REFLO is tied to ACOM as shown in Figure 24, the internal
reference is activated and REFIO provides a 1.20 V output. In
this case, the internal reference must be filtered externally with a
ceramic chip capacitor of 0.1mF or greater from REFIO to
REFLO. Also, REFIO should be buffered with an external
amplifier having a low input bias current (i.e., <1 mA) if any
additional loading is required.
Figure 24.Internal Reference Configuration
The internal reference can also be disabled by connecting REFLO
to AVDD. In this case, an external reference may then be ap-
plied to REFIO as shown in Figure 25. The external reference
may provide either a fixed reference voltage to enhance accuracy
and drift performance or a varying reference voltage for gain
control. Note that the 0.1 mF compensation capacitor is not
required since the internal reference is disabled and the high
input impedance (i.e., 1 MW) of REFIO minimizes any loading
of the external reference.
AD9761Figure 25.External Reference Configuration
REFERENCE CONTROL AMPLIFIERThe AD9761 also contains an internal control amplifier which is
used to simultaneously regulate both DAC’s full-scale output
current, IOUTFS. Since the I and Q IOUTFS are derived from the
same voltage reference and control circuitry, excellent gain
matching is ensured. The control amplifier is configured as a
V-I converter as shown in Figure 25 such that its current out-
put, IREF, is determined by the ratio of the VREFIO and an exter-
nal resistor, RSET, as stated in Equation (4). IREF is copied over
to the segmented current sources with the proper scaling factor
to set IOUTFS as stated in Equation (3).
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS over a 1mA to 10 mA range by setting IREF between
62.5mA and 625 mA. The wide adjustment span of IOUTFS pro-
vides several application benefits. The first benefit relates di-
rectly to the power dissipation of the AD9761’s analog supply,
AVDD, which is proportional to IOUTFS (refer to the POWER
DISSIPATION section). The second benefit relates to thedB adjustment span which may be useful for system gain
control purposes.
Optimum noise and dynamic performance for the AD9761 is
obtained with a 0.1 mF external capacitor installed between
COMP2 and AVDD. The bandwidth of the reference control
amplifier is limited to approximately 5 kHz with a 0.1 mF ca-
pacitor installed. Since the –3 dB bandwidth corresponds to the
dominant pole and hence its dominant time constant, the set-
tling time of the control amplifier to a stepped reference input
response can be easily determined. Note, the output of the
control amplifier, COMP2, is internally compensated via apF capacitor thus ensuring its stability if no external capaci-
tor is added.
Depending on the requirements of the application, IREF can be
adjusted by varying either RSET, or in the external reference
mode, by varying the REFIO voltage. IREF can be varied for a
fixed RSET by disabling the internal reference and varying the
voltage of REFIO over its compliance range of 1.25 V to 0.10 V.
REFIO can be driven by a single-supply amplifier or DAC thus
allowing IREF to be varied for a fixed RSET. Since the input im-
pedance of REFIO is approximately 1 MW, a simple, low cost
R-2R ladder DAC configured in the voltage mode topology may
be used to control the gain. This circuit is shown in Figure 26
using the AD7524 and an external 1.2 V reference, the AD1580.
ANALOG OUTPUTSAs previously stated, both the I and Q DACs produce two
complementary current outputs which may be configured for
single-end or differential operation. IIOUTA and IIOUTB can be
converted into complementary single-ended voltage outputs,
VIOUTA and VIOUTB, via a load resistor, RLOAD, as described in
the DAC TRANSFER SECTION by Equations 5 through 8.
The differential voltage, VIDIFF, existing between VIOUTA and
VIOUTB can also be converted to a single-ended voltage via a
transformer or differential amplifier configuration.
Figure 27 shows an equivalent circuit of the AD9761’s I (or Q)
DAC output. It consists of a parallel array of PMOS current
sources in which each current source is switched to either
IOUTA or IOUTB via a differential PMOS switch. As a result,
the equivalent output impedance of IOUTA and IOUTB re-
mains quite high (i.e., >100 kW and 5 pF).
RLOADRLOADFigure 27.Equivalent Circuit of the AD9761 DAC Output
IOUTA and IOUTB have a negative and positive voltage com-
pliance range which must be adhered to achieve optimum per-
formance. The negative output compliance range of –1 V is set
by the breakdown limits of the CMOS process. Operation be-
yond this maximum limit may result in a breakdown of the
output stage.
AD1580
1.2V
AVDD
RSET
