AD9752 Fast Delivery |IC PHOENIX CO.,LIMITED

AD9752 ,12-Bit, 100 MSPS+ TxDAC?D/A Converterapplications. Its power dissipation can be furthertion path based on resolution (8 to 14 bits), per ..
AD9752AR ,12-Bit, 125 MSPS High Performance TxDAC D/A Converterapplications. Matching between the twoDirect IFcurrent outputs ensures enhanced dynamic performance ..
AD9752ARU ,12-Bit, 125 MSPS High Performance TxDAC D/A ConverterSPECIFICATIONS(T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, unless otherwise noted)MIN MAX OUTFS P ..
AD9752ARUZ , 12-Bit, 125 MSPS High Performance TxDAC D/A Converter
AD9753AST ,12-Bit, 300 MSPS High Speed TxDAC+® D/A ConverterSPECIFICATIONS otherwise noted.)Parameter Min Typ Max UnitRESOLUTION 12 Bits1DC ACCURACYIntegral Li ..
AD9754 ,14-Bit, 100 MSPS+ TxDAC?D/A Converterapplications. Matching between the twoDirect IFcurrent outputs ensures enhanced dynamic performance ..
ADS8332IRGER ,2.7V-5.5V, 16 Bit 500KSPS Low Power Serial ADC, 8-Ch MUX and Breakout 24-VQFN -40 to 85Features:These converters are available in 24-pin, 4 × 4 VQFN– On-Chip Conversion Clock (CCLK)and 2 ..
ADS8332IRGET ,2.7V-5.5V, 16 Bit 500KSPS Low Power Serial ADC, 8-Ch MUX and Breakout 24-VQFN -40 to 85 SBAS363E–DECEMBER 2009–REVISED AUGUST 20165 Companion ProductsPart number NameREF3240 4.096V 4ppm/ ..
ADS8332IRGET ,2.7V-5.5V, 16 Bit 500KSPS Low Power Serial ADC, 8-Ch MUX and Breakout 24-VQFN -40 to 85Features 2 Applications1• Low-Power, Flexible Supply Range: • Communications– 2.7-V to 5.5-V Analog ..
ADS8341E ,16-Bit, 4-Channel Serial Output Sampling Analog-To-Digital ConverterFEATURES DESCRIPTION* PIN FOR PIN WITH ADS7841The ADS8341 is a 4-channel, 16-bit sampling Analog-to ..
ADS8341EB ,16-Bit, 4-Channel Serial Output Sampling Analog-To-Digital ConverterMaximum Ratings”may cause permanent damage to the device. Exposure to absolute maximumCH1 3 14 DINc ..
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AD9752
12-Bit, 100 MSPS+ TxDAC?D/A Converter
12-Bit, 125 MSPS High Performance
TxDAC® D/A Converter
FUNCTIONAL BLOCK DIAGRAMRSET
0.1mF
CLOCK
FEATURES
High Performance Member of Pin-Compatible
TxDAC Product Family
125 MSPS Update Rate
12-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 5 MHz Output:79 dBc
Differential Current Outputs:2 mA to 20 mA
Power Dissipation:185 mW @ 5V
Power-Down Mode:20 mW @ 5V
On-Chip 1.20 V Reference
CMOS-Compatible +2.7 V to +5.5 V Digital Interface
Package:28-Lead SOIC and TSSOP
Edge-Triggered Latches
APPLICATIONS
Wideband Communication Transmit Channel:
Direct IF
Basestations
Wireless Local Loop
Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation
PRODUCT DESCRIPTION
The AD9752 is a 12-bit resolution, wideband, second generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog-converters (DACs). The TxDAC family,
which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs, is
specifically optimized for the transmit signal path of communica-
tion systems. All of the devices share the same interface options,
small outline package and pinout, thus providing an upward or
downward component selection path based on performance,
resolution and cost. The AD9752 offers exceptional ac and dc
performance while supporting update rates up to 125 MSPS.
The AD9752’s flexible single-supply operating range of 4.5 V to
5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 65 mW, without a significant degradation in
performance, by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 20 mW.
The AD9752 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input latches
and a 1.2 V temperature compensated bandgap reference have
been integrated to provide a complete monolithic DAC solution.
The digital inputs support +2.7 V to +5 V CMOS logic families.
The AD9752 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 kW output impedance.
Differential current outputs are provided to support single-
ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen-
tary, single-ended voltage outputs or fed directly into a trans-
former. The output voltage compliance range is 1.25V.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9752 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier, which provides a wide
(>10:1) adjustment span, allows the AD9752 full-scale current
to be adjusted over a 2mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9752 may oper-
ate at reduced power levels or be adjusted over a 20dB range to
provide additional gain ranging capabilities.
The AD9752 is available in 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTSThe AD9752 is a member of the wideband TxDAC product
family that provides an upward or downward component selec-
tion path based on resolution (8 to 14 bits), performance and
cost. The entire family of TxDACs is available in industry
standard pinouts.Manufactured on a CMOS process, the AD9752 uses a
proprietary switching technique that enhances dynamic
performance beyond that previously attainable by higher
power/cost bipolar or BiCMOS devices.On-chip, edge-triggered input CMOS latches interface readily
to +2.7 V to +5 V CMOS logic families. The AD9752 can
support update rates up to 125 MSPS.A flexible single-supply operating range of 4.5V to 5.5 V and
a wide full-scale current adjustment span of 2mA to 20 mA
allow the AD9752 to operate at reduced power levels.The current output(s) of the AD9752 can be easily config-
TxDAC is a registered trademark of Analog Devices, Inc.
*. Patents Numbers 5450084, 5568145, 5689257, 5612697 and
5703519. Other patents pending.
AD9752–SPECIFICATIONS
(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)DC SPECIFICATIONS
REFERENCE INPUT
NOTESMeasured at IOUTA, driving a virtual ground.Nominal full-scale current, IOUTFS, is 32 · the IREF current.Use an external buffer amplifier to drive any external load.Requires +5 V supply.Measured at fCLOCK = 25 MSPS and IOUT = static full scale (20 mA).Logic level for SLEEP pin must be referenced to AVDD. Min VIH = 3.5 V.–5% Power supply variation.
Specifications subject to change without notice.
AD9752
DYNAMIC SPECIFICATIONS
AC LINEARITY
NOTESMeasured single ended into 50W load.
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Differential Transformer Coupled Output,V Doubly Terminated, unless otherwise noted)
AD9752
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
ABSOLUTE MAXIMUM RATINGS*
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
DIGITAL SPECIFICATIONS
NOTESWhen DVDD = +5 V and Logic 1 voltage »3.5 V and Logic 0 voltage »1.3 V. IVDD can increase by up to 10 mA, depending on fCLOCK.
Specifications subject to change without notice.
0.1%
DB0–DB11
CLOCK
IOUTA
IOUTB
Figure 1. Timing Diagram
(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)
ORDERING GUIDE
*R = Small Outline IC; RU = Thin Shrink Small Outline Package.
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 Mil SOICJA = 71.4°C/WJC = 23°C/W
28-Lead TSSOPJA = 97.9°C/WJC = 14.0°C/W
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
AD9752
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per °C. For reference drift, the drift is reported
in ppm per °C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range for an output containing mul-
tiple carrier tones of equal amplitude. It is measured as the
difference between the rms amplitude of a carrier tone to the
peak spurious signal in the region of a removed tone.
+5V
RSET
2kV
0.1mF
DVDD
DCOM
OUTPUT20pF
TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50V INPUT
MINI-CIRCUITS
T1-1T
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
Figure 2.Basic AC Characterization Test Setup
Typical AC Characterization Curves @ +5 V Supplies
(AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, 50V Doubly Terminated Load, Differential Output, TA = +258C, SFDR up to Nyquist, unless otherwise noted)
fOUT – MHz
SFDR – dB0110010
Figure 3.SFDR vs. fOUT @ 0 dBFS
fOUT – MHz
SFDR – dBc0530201525
Figure 6.SFDR vs. fOUT @ 65 MSPS
AOUT – dBFS
SFDR – dB
–20–15–5
Figure 9.Single-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/11
SFDR – dB021412810
fOUT – MHz
Figure 4.SFDR vs. fOUT @ 25MSPS
SFDR – dB01060403050
fOUT – MHz
Figure 7.SFDR vs. fOUT @ 125 MSPS
AOUT – dBFS
SFDR – dB
–20–15–5
Figure 10.Single-Tone SFDR vs.
AOUT @ fOUT = fCLOCK/5
fOUT – MHz
SFDR – dBc05251020
Figure 5.SFDR vs. fOUT @ 50 MSPS
fOUT – MHz
SFDR – dBc21281050
Figure 8.SFDR vs. fOUT and IOUTFS
@ 25 MSPS and 0 dBFS

fCLOCK – MSPS
SNR – dB201208060100
Figure 11.SNR vs. fCLOCK and IOUTFS
@ fOUT = 2 MHz and 0 dBFS
AD9752
CODE
ERROR – LSB4000100020003000
–0.4
Figure 12. Typical INL
fOUT – MHz
SIGNAL AMPLITUDE – dBm60102030
–9050
Figure 15.Dual-Tone SFDR
CODE
ERROR – LSB4000100020003000
–0.4
Figure 13.Typical DNL
SIGNAL AMPLITUDE – dBm30.05.010.015.0
fOUT – MHz
Figure 16.Four-Tone SFDR
TEMPERATURE – 8C
SFDR – dBc
–5595–30–52070
Figure 14.SFDR vs. Temperature @
125 MSPS, 0 dBFS
FUNCTIONAL DESCRIPTION
Figure 17 shows a simplified block diagram of the AD9752.
The AD9752 consists of a large PMOS current source array that
is capable of providing up to 20mA of total current. The array
is divided into 31 equal currents that make up the five most
significant bits (MSBs). The next four bits or middle bits consist
of 15 equal current sources whose value is 1/16th of an MSB
current source. The remaining LSBs are binary weighted frac-
tions of the middle-bits current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances its dynamic performance for multitone or low
amplitude signals and helps maintain the DAC’s high output
impedance (i.e., >100kW).
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on a new
architecture that drastically improves distortion performance.
This new switch architecture reduces various timing errors and
provides matching complementary drive signals to the inputs of
the differential current switches.
The analog and digital sections of the AD9752 have separate
power supply inputs (i.e., AVDD and DVDD). The digital
section, which is capable of operating up to a 125 MSPS clock
rate and over a +2.7 V to +5.5 V operating range, consists of
edge-triggered latches and segment decoding logic circuitry.
The analog section, which can operate over a +4.5 V to +5.5 V
range, includes the PMOS current sources, the associated differ-
ential switches, a 1.20 V bandgap voltage reference and a refer-
ence control amplifier.
The full-scale output current is regulated by the reference con-
trol amplifier and can be set from 2 mA to 20 mA via an exter-
nal resistor, RSET. The external resistor, in combination with
both the reference control amplifier and voltage reference VREFIO,
sets the reference current IREF, which is mirrored over to the
segmented current sources with the proper scaling factor. The
full-scale current, IOUTFS, is thirty-two times the value of IREF.
DAC TRANSFER FUNCTION
The AD9752 provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current output,
IOUTFS, when all bits are high (i.e., DAC CODE = 4095) while
IOUTB = (4095 – DAC CODE)/4096 · IOUTFS(2)
where DAC CODE = 0 to 4095 (i.e., Decimal Representation).
As mentioned previously, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage
VREFIO and external resistor RSET. It can be expressed as:
IOUTFS = 32 · IREF(3)
where IREF = VREFIO/RSET(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, which are tied to analog common, ACOM. Note,
RLOAD may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminatedW or 75W cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply :
VOUTA = IOUTA · RLOAD(5)
VOUTB = IOUTB · RLOAD(6)
Note the full-scale value of VOUTA and VOUTB should not exceed
the specified output compliance range to maintain specified
distortion and linearity performance.
The differential voltage, VDIFF, appearing across IOUTA and
IOUTB is:
VDIFF = (IOUTA – IOUTB) · RLOAD(7)
Substituting the values of IOUTA, IOUTB, and IREF; VDIFF can be
expressed as:
VDIFF = {(2 DAC CODE – 4095)/4096} ·
(32 RLOAD/RSET) · VREFIO(8)
These last two equations highlight some of the advantages of
operating the AD9752 differentially. First, the differential op-
eration will help cancel common-mode error sources associated
with IOUTA and IOUTB such as noise, distortion and dc offsets.
Second, the differential code dependent current and subsequent
voltage, VDIFF, is twice the value of the single-ended voltage
output (i.e., VOUTA or VOUTB), thus providing twice the signal
power to the load.
Note, the gain drift temperature performance for a single-ended
(VOUTA and VOUTB) or differential output (VDIFF) of the AD9752
DIGITAL DATA INPUTS (DB11–DB0)
+5V
2kV
0.1mF
CLOCK
Figure 17.Functional Block Diagram
AD9752
REFERENCE OPERATION
The AD9752 contains an internal 1.20 V bandgap reference
that can easily be disabled and overridden by an external refer-
ence. REFIO serves as either an input or output depending on
whether the internal or an external reference is selected. If
REFLO is tied to ACOM, as shown in Figure 18, the internal
reference is activated and REFIO provides a 1.20V output. In
this case, the internal reference must be compensated externally
with a ceramic chip capacitor of 0.1mF or greater from REFIO
to REFLO. Also, REFIO should be buffered with an external
amplifier having an input bias current less than 100nA if any
additional loading is required.
+5V
ADDITIONAL
LOAD
OPTIONAL
EXTERNAL
REF BUFFER
Figure 18.Internal Reference Configuration
The internal reference can be disabled by connecting REFLO to
AVDD. In this case, an external reference may then be applied
to REFIO as shown in Figure 19. The external reference may
provide either a fixed reference voltage to enhance accuracy and
drift performance or a varying reference voltage for gain control.
Note that the 0.1mF compensation capacitor is not required
since the internal reference is disabled, and the high input im-
pedance (i.e., 1 MW) of REFIO minimizes any loading of the
external reference.
AVDD
AVDD
Figure 19.External Reference Configuration
REFERENCE CONTROL AMPLIFIER
The AD9752 also contains an internal control amplifier that is
used to regulate the DAC’s full-scale output current, IOUTFS.
The control amplifier is configured as a V-I converter as shown
in Figure 19, such that its current output, IREF, is determined by
the ratio of the VREFIO and an external resistor, RSET, as stated
in Equation 4. IREF is copied over to the segmented current
sources with the proper scaling factor to set IOUTFS as stated in
Equation 3.
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS over a 2mA to 20 mA range by setting IREF between
62.5mA and 625mA. The wide adjustment span of IOUTFS
provides several application benefits. The first benefit relates
directly to the power dissipation of the AD9752, which is
proportional to IOUTFS (refer to the Power Dissipation section).
The second benefit relates to the 20dB adjustment, which is
useful for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 0.5 MHz. The output of the control amplifier is
internally compensated via a 150 pF capacitor that limits the
control amplifier small-signal bandwidth and reduces its
output impedance. Since the –3dB bandwidth corresponds to
the dominant pole, and hence the time constant, the settling
time of the control amplifier to a stepped reference input re-
sponse can be approximated. In this case, the time constant can
be approximated to be 320 ns.
There are two methods in which IREF can be varied for a fixed
RSET. The first method is suitable for a single-supply system in
which the internal reference is disabled, and the common-mode
voltage of REFIO is varied over its compliance range of 1.25 V
to 0.10 V. REFIO can be driven by a single-supply amplifier or
DAC, thus allowing IREF to be varied for a fixed RSET. Since the
input impedance of REFIO is approximately 1 MW, a simple,
low cost R-2R ladder DAC configured in the voltage mode
topology may be used to control the gain. This circuit is shown
in Figure 20 using the AD7524 and an external 1.2 V reference,
the AD1580.
1.2V
AVDD
AVDD
DB7–DB0
AD1580
The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed and IREF is
varied by an external voltage, VGC, applied to RSET via an ampli-
fier. An example of this method is shown in Figure 21, in which
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20V. The external voltage, VGC, is
referenced to ACOM and should not exceed 1.2 V. The value
of RSET is such that IREFMAX and IREFMIN do not exceed 62.5mA
and 625mA, respectively. The associated equations in Figure 21
can be used to determine the value of RSET.
AVDD
VGC
1mF
IREF = (1.2–VGC)/RSET
WITH VGC < VREFIO AND 62.5mA # IREF # 625A
Figure 21.Dual-Supply Gain Control Circuit
ANALOG OUTPUTS
The AD9752 produces two complementary current outputs,
IOUTA and IOUTB, which may be configured for single-end
or differential operation. IOUTA and IOUTB can be converted
into complementary single-ended voltage outputs, VOUTA and
VOUTB, via a load resistor, RLOAD, as described in the DAC
Transfer Function section by Equations 5 through 8. The
differential voltage, VDIFF, existing between VOUTA and VOUTB
can also be converted to a single-ended voltage via a transformer
or differential amplifier configuration.
Figure 22 shows the equivalent analog output circuit of the
AD9752 consisting of a parallel combination of PMOS differen-
tial current switches associated with each segmented current
source. The output impedance of IOUTA and IOUTB is deter-
mined by the equivalent parallel combination of the PMOS
switches and is typically 100 kW in parallel with 5 pF. Due to
the nature of a PMOS device, the output impedance is also
slightly dependent on the output voltage (i.e., VOUTA and VOUTB)
and, to a lesser extent, the analog supply voltage, AVDD, and
full-scale current, IOUTFS. Although the output impedance’s
signal dependency can be a source of dc nonlinearity and ac linear-
ity (i.e., distortion), its effects can be limited if certain precau-
tions are noted.
Figure 22.Equivalent Analog Output
IOUTA and IOUTB also have a negative and positive voltage
compliance range. The negative output compliance range of
–1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a break-
down of the output stage and affect the reliability of the AD9752.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from its
nominal 1.25 V for an IOUTFS = 20 mA to 1.00V for an IOUTFS =
2 mA. Operation beyond the positive compliance range will
induce clipping of the output signal which severely degrades
the AD9752’s linearity and distortion performance.
For applications requiring the optimum dc linearity, IOUTA
and/or IOUTB should be maintained at a virtual ground via an
I-V op amp configuration. Maintaining IOUTA and/or IOUTB
at a virtual ground keeps the output impedance of the AD9752
fixed, significantly reducing its effect on linearity. However,
it does not necessarily lead to the optimum distortion perfor-
mance due to limitations of the I-V op amp. Note that the
INL/DNL specifications for the AD9752 are measured in
this manner using IOUTA. In addition, these dc linearity
specifications remain virtually unaffected over the specified
power supply range of 4.5V to 5.5V.
Operating the AD9752 with reduced voltage output swings at
IOUTA and IOUTB in a differential or single-ended output
configuration reduces the signal dependency of its output
impedance thus enhancing distortion performance. Although
the voltage compliance range of IOUTA and IOUTB extends
from –1.0V to +1.25V, optimum distortion performance is
achieved when the maximum full-scale signal at IOUTA and
IOUTB does not exceed approximately 0.5 V. A properly se-
lected transformer with a grounded center-tap will allow the
AD9752 to provide the required power and voltage levels to
different loads while maintaining reduced voltage swings at
IOUTA and IOUTB. DC-coupled applications requiring a
differential or single-ended output configuration should size
RLOAD accordingly. Refer to Applying the AD9752 section for
examples of various output configurations.
The most significant improvement in the AD9752’s distortion
and noise performance is realized using a differential output
configuration. The common-mode error sources of both
IOUTA and IOUTB can be substantially reduced by the
common-mode rejection of a transformer or differential am-
plifier. These common-mode error sources include even-
order distortion products and noise. The enhancement in
distortion performance becomes more significant as the recon-
structed waveform’s frequency content increases and/or its
amplitude decreases.
The distortion and noise performance of the AD9752 is also
slightly dependent on the analog and digital supply as well as the
full-scale current setting, IOUTFS. Operating the analog supply at
5.0 V ensures maximum headroom for its internal PMOS current
sources and differential switches leading to improved distortion
performance. Although IOUTFS can be set between 2mA and
20 mA, selecting an IOUTFS of 20 mA will provide the best dis-
tortion and noise performance also shown in Figure 8. The
noise performance of the AD9752 is affected by the digital sup-
AD9752
In summary, the AD9752 achieves the optimum distortion and
noise performance under the following conditions:
(1)Differential Operation.
(2)Positive voltage swing at IOUTA and IOUTB limited to
+0.5 V.
(3)IOUTFS set to 20 mA.
(4)Analog Supply (AVDD) set at 5.0 V.
(5)Digital Supply (DVDD) set at 3.0V to 3.3 V with appro-
priate logic levels.
Note that the ac performance of the AD9752 is characterized
under the above mentioned operating conditions.
DIGITAL INPUTS
The AD9752’s digital input consists of 12 data input pins and a
clock input pin. The 12-bit parallel data inputs follow standard
positive binary coding where DB11 is the most significant bit
(MSB) and DB0 is the least significant bit (LSB). IOUTA
produces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.
The digital interface is implemented using an edge-triggered
master slave latch. The DAC output is updated following the
rising edge of the clock as shown in Figure 1 and is designed to
support a clock rate as high as 125 MSPS. The clock can be
operated at any duty cycle that meets the specified latch pulse-
width. The setup and hold times can also be varied within the
clock cycle as long as the specified minimum times are met;
although the location of these transition edges may affect digital
feedthrough and distortion performance. Best performance is
typically achieved when the input data transitions on the falling edge
of a 50% duty cycle clock.
The digital inputs are CMOS compatible with logic thresholds,
VTHRESHOLD set to approximately half the digital positive supply
(DVDD) or
VTHRESHOLD = DVDD/2 (–20%)
The internal digital circuitry of the AD9752 is capable of operating
over a digital supply range of 2.7V to 5.5 V. As a result, the
digital inputs can also accommodate TTL levels when DVDD is
set to accommodate the maximum high level voltage of the TTL
drivers VOH(MAX). A DVDD of 3V to 3.3V will typically ensure
proper compatibility with most TTL logic families. Figure 23
shows the equivalent digital input circuit for the data and clock
inputs. The sleep mode input is similar with the exception that
it contains an active pull-down circuit, thus ensuring that the
AD9752 remains enabled if this input is left disconnected.
DVDD
DIGITAL
INPUT
data interface circuitry should be specified to meet the mini-
mum setup and hold times of the AD9752 as well as its re-
quired min/max input logic level thresholds. Typically, the
selection of the slowest logic family that satisfies the above con-
ditions will result in the lowest data feedthrough and noise.
Digital signal paths should be kept short and run lengths
matched to avoid propagation delay mismatch. The insertion of
a low value resistor network (i.e., 20W to 100W) between the
AD9752 digital inputs and driver outputs may be helpful in reduc-
ing any overshooting and ringing at the digital inputs that con-
tribute to data feedthrough. For longer run lengths and high data
update rates, strip line techniques with proper termination resis-
tors should be considered to maintain “clean” digital inputs. Also,
operating the AD9752 with reduced logic swings and a corre-
sponding digital supply (DVDD) will also reduce data feedthrough.
The external clock driver circuitry should provide the AD9752
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a recon-
structed waveform. Thus, the clock input should be driven by
the fastest logic family suitable for the application.
Note, the clock input could also be driven via a sine wave, which is
centered around the digital threshold (i.e., DVDD/2), and meets
the min/max logic threshold. This will typically result in a slight
degradation in the phase noise, which becomes more noticeable
at higher sampling rates and output frequencies. Also, at higher
sampling rates, the 20% tolerance of the digital logic threshold
should be considered since it will affect the effective clock duty
cycle and subsequently cut into the required data setup and
hold times.
INPUT CLOCK/DATA TIMING RELATIONSHIP
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9752 is positive edge triggered, and
so exhibits SNR sensitivity when the data transition is close to
this edge. In general, the goal when applying the AD9752 is to
make the data transitions shortly after the positive clock edge.
This becomes more important as the sample rate increases. Figure
24 shows the relationship of SNR to clock placement with dif-
ferent sample rates and different frequencies out. Note that at
the lower sample rates, much more tolerance is allowed in clock
placement, while at higher rates, much more care must be taken.
SNR – dB

Partno	Mfg	Dc	Qty	Available	Descript
AD9752	AD	N/a	7	avai	12-Bit, 100 MSPS+ TxDAC?D/A Converter