AD974BN ,4-Channel, 16-Bit, 200 kSPS Data Acquisition SystemSPECIFICATIONS (f = 200 kHz, V = V = +5 V, –408C to +858C)S DIG ANAParameter Symbol Min Typ Max Uni ..
AD9750AR ,10-Bit, 125 MSPS High Performance TxDAC D/A ConverterSPECIFICATIONS50 V Doubly Terminated, unless otherwise noted)Parameter Min Typ Max UnitsDYNAMIC PER ..
AD9750ARU ,10-Bit, 125 MSPS High Performance TxDAC D/A ConverterSPECIFICATIONSMIN MAX OUTFS Parameter Min Typ Max UnitsRESOLUTION 10 Bits1DC ACCURACYIntegral Linea ..
AD9751AST ,10-Bit, 300 MSPS High Speed TxDAC+® D/A ConverterSPECIFICATIONS Transformer-Coupled Output, 50 Doubly Terminated, unless otherwise noted.)Paramete ..
AD9752 ,12-Bit, 100 MSPS+ TxDAC?D/A Converterapplications. Its power dissipation can be furthertion path based on resolution (8 to 14 bits), per ..
AD9752AR ,12-Bit, 125 MSPS High Performance TxDAC D/A Converterapplications. Matching between the twoDirect IFcurrent outputs ensures enhanced dynamic performance ..
ADS8330IBPW ,2.7V-5.5V, 16 Bit 1MSPS Serial ADC w 2-to-1 MUX 16-TSSOP -40 to 85These devices have limited built-in ESD protection. The leads should be shorted together or the dev ..
ADS8330IBRSAR ,2.7V-5.5V, 16 Bit 1MSPS Serial ADC w 2-to-1 MUX 16-QFN -40 to 85ELECTRICAL CHARACTERISTICST = –40°C to 85°C, +VA = 4.5 V to 5.5 V, +VBD = 1.65 V to 5.5 V, V = 5 V, ..
ADS8330IBRSARG4 ,Brown Corporation - LOW POWER, 16-BIT, 1-MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
ADS8330IBRSAT ,2.7V-5.5V, 16 Bit 1MSPS Serial ADC w 2-to-1 MUX 16-QFN -40 to 85FEATURES APPLICATIONS• Communications2• 2.7-V to 5.5-V Analog Supply, Low Power:• Transducer Interf ..
ADS8330IBRSAT ,2.7V-5.5V, 16 Bit 1MSPS Serial ADC w 2-to-1 MUX 16-QFN -40 to 85MAXIMUM RATINGS(1)Over operating free-air temperature range, unless otherwise noted.UNIT+IN to AGND ..
ADS8330IPW ,2.7V-5.5V, 16 Bit 1MSPS Serial ADC w 2-to-1 MUX 16-TSSOP -40 to 85maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
AD974AN-AD974AR-AD974BN
4-Channel, 16-Bit, 200 kSPS Data Acquisition System
REV. A
4-Channel, 16-Bit, 200 kSPS
Data Acquisition System
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Fast 16-Bit ADC with 200 kSPS Throughput
Four Single-Ended Analog Input Channels
Single +5 V Supply Operation
Input Ranges: 0 V to +4 V, 0 V to +5 V and 610 V
120 mW Max Power Dissipation
Power-Down Mode 50 mW
Choice of External or Internal 2.5 V Reference
On-Chip Clock
Power-Down Mode
GENERAL DESCRIPTIONThe AD974 is a four-channel, data acquisition system with a
serial interface. The part contains an input multiplexer, a high-
speed 16-bit sampling ADC and a +2.5 V reference. All of this
operates from a single +5 V power supply that also has a power-
down mode. The part will accommodate 0 V to +4 V, 0 V to
+5 V or –10 V analog input ranges.
The interface is designed for an efficient transfer of data while
requiring a low number of interconnects.
The AD974 is comprehensively tested for ac parameters such as
SNR and THD, as well as the more traditional parameters of
offset, gain and linearity.
The AD974 is fabricated on Analog Devices’ BiCMOS process,
which has high performance bipolar devices along with CMOS
transistors.
The AD974 is available in 28-lead DIP, SOIC and SSOP
packages.
PRODUCT HIGHLIGHTSThe AD974 is a complete data acquisition system combining
a four-channel multiplexer, a 16-bit sampling ADC and a
+2.5 V reference on a single chip.The part operates from a single +5 V supply and also has a
power-down feature.Interfacing to the AD974 is simple with a low number of
interconnect signals.The AD974 is comprehensively specified for ac parameters
such as SNR and THD, as well as dc parameters such as
linearity and offset and gain errors.
AD974–SPECIFICATIONS
(–408C to +858C, fS = 200 kHz, VDIG = VANA = +5 V, unless otherwise noted)
AD974NOTESLSB means Least Significant Bit. With a –10 V input, one LSB is 305 mV.Typical rms noise at worst case transitions and temperatures.Full-Scale Error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full-scale transition voltage, and includes the effect
of offset error. For bipolar input, the Full-Scale Error is the worst case of either the –Full-Scale or +Full-Scale code transition voltage errors. For unipolar input
ranges, Full-Scale Error is with respect to the +Full-Scale code transition voltage.External 2.5 V reference connected to REF.All specifications in dB are referred to a full-scale –10 V input.Full-Power Bandwidth is defined as full-scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60 dB, or 10 bits of accuracy.Recovers to specified performance after a 2 · FS input overvoltage.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
(fS = 200 kHz, VDIG = VANA = +5 V, –408C to +858C)
AD974
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD974 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1Analog Inputs
VxA, VxB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–25 V
CAP . . . . . . . . . . . . . . . .+VANA + 0.3 V to AGND2 – 0.3 V
REF . . . . . . . . . . . . . . . . . . . . Indefinite Short to AGND2,
Momentary Short to VANA
Ground Voltage Differences
DGND, AGND1, AGND2 . . . . . . . . . . . . . . . . . . .–0.3 V
Supply␣Voltages
VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V
VDIG to VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–7 V
VDIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V
Digital Inputs . . . . . . . . . . . . . . . . . . .–0.3 V to VDIG + 0.3 V
Internal␣Power␣Dissipation2
PDIP (N), SOIC (R), SSOP (RS) . . . . . . . . . . . . .700 mW
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature Range N, R . . . . . . . .–65°C to +150°C
Lead Temperature Range
(Soldering␣10␣sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Specification is for device in free air:
28-Lead PDIP: qJA = 100°C/W, qJC = 31°C/W
28-Lead SOIC: qJA = 75°C/W, qJC = 24°C/W
28-Lead SSOP: qJA = 109°C/W, qJC = 39°C/W
PIN CONFIGURATION
SOIC, DIP AND SSOPFigure 1.Load Circuit for Digital Interface Timing
ORDERING GUIDEAD974BN
AD974AR
AD974BR
AD974ARS
PIN FUNCTION DESCRIPTIONS
AD974
DEFINITION OF SPECIFICATIONS
INTEGRAL NONLINEARITY ERROR (INL)Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as “negative full scale” occurs 1/2 LSB
before the first code transition. “Positive full scale” is defined as
a level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY ERROR (DNL)In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
FULL-SCALE ERRORThe last + transition (from 011...10 to 011...11) should
occur for an analog voltage 1 1/2 LSB below the nominal full
scale (9.9995422 V for a –10 V range). The full-scale error is
the deviation of the actual level of the last transition from the
ideal level.
BIPOLAR ZERO ERRORBipolar zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the mid-
scale output code.
UNIPOLAR ZERO ERRORIn unipolar mode, the first transition should occur at a level
1/2 LSB above analog ground. Unipolar zero error is the devia-
tion of the actual transition from that point.
SPURIOUS FREE DYNAMIC RANGEThe difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
TOTAL HARMONIC DISTORTION (THD)THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of a full-scale input signal and is ex-
pressed in decibels.
SIGNAL TO (NOISE AND DISTORTION) (S/[N+D]) RATIOS/(N+D) is the ratio of the rms value of the measured input
signal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc.
The value for S/(N+D) is expressed in decibels.
FULL POWER BANDWIDTHThe full power bandwidth is defined as the full-scale input fre-
quency at which the S/(N+D) degrades to 60 dB, 10 bits of
accuracy.
APERTURE DELAYAperture delay is a measure of the acquisition performance, and
is measured from the falling edge of the R/C input to when the
input signal is held for a conversion.
TRANSIENT RESPONSEThe time required for the AD974 to achieve its rated accuracy
after a full-scale step function is applied to its input.
OVERVOLTAGE RECOVERYThe time required for the ADC to recover to full accuracy after
an analog input signal 150% of full-scale is reduced to 50% of
the full-scale value.
CONVERSION CONTROLThe AD974 is controlled by two signals: R/C and CS. When
R/C is brought low, with CS low, for a minimum of 50 ns, the
input signal will be held on the internal capacitor array and a
conversion “n” will begin. Once the conversion process does
begin, the BUSY signal will go low until the conversion is com-
plete. Internally, the signals R/C and CS are ORed together and
there is no requirement on which signal is taken low first when
initiating a conversion. The only requirement is that there be at
least 10 ns of delay between the two signals being taken low.
After the conversion is complete, the BUSY signal will return
high and the AD974 will again resume tracking the input signal.
Under certain conditions the CS pin can be tied Low and R/C
will be used to determine whether you are initiating a conver-
sion or reading data. On the first conversion, after the AD974 is
powered up, the DATA output will be indeterminate.
Conversion results can be clocked serially, using either an
internal clock generated by the AD974 or an external clock.
The AD974 is configured for the internal data clock mode by
pulling the EXT/INT pin low. It is configured for the external
clock mode by pulling the EXT/INT pin high.
INTERNAL DATA CLOCK MODEThe AD974 is configured to generate and provide the data clock
when the EXT/INT pin is held low. Typically CS will be tied
low and R/C will be used to initiate a conversion “n.” During
the conversion the AD974 will output 16 bits of data, MSB first,
from conversion “n-1” on the DATA pin. This data will be
synchronized with 16 clock pulses provided on the DATACLK
pin. The output data will be valid on both the rising and falling
edge of the data clock as shown in Figure 3. After the LSB has
been presented, the DATACLK pin will stay low until another
conversion is initiated.
In this mode, the digital input/output pins’ transitions are suit-
ably positioned to minimize degradation on the conversion
result, mainly during the second half of the conversion process.
EXTERNAL DATA CLOCK MODEThe AD974 is configured to accept an externally supplied data
clock when the EXT/INT pin is held high. This mode of opera-
tion provides several methods by which conversion results can
be read. The output data from conversion “n-1” can be read
during conversion “n,” or the output data from conversion “n”
CS, R/C
BUSY
MODE
A0, A1
WR1, WR2Figure 2.Basic Conversion Timing
R/C
DATACLK
DATA
BUSYt11Figure 3.Serial Data Timing for Reading Previous Conversion Results with Internal Clock
(CS and EXT/INT Set to Logic Low)
AD974can be read after the conversion is complete. The external clock
can be either a continuous or discontinuous clock. A discontinu-
ous clock can be either normally low or normally high when
inactive. In the case of the discontinuous clock, the AD974 can be
configured to either generate or not generate a SYNC output
(with a continuous clock a SYNC output will always be produced).
Each of the methods will be described in the following sections
and are illustrated in Figures 4 through 9. It should be noted
that all timing diagrams assume that the receiving device is
latching data on the rising edge of the external clock. If the
falling edge of DATACLK is used then, in the case of a discon-
tinuous clock, one less clock pulse is required than shown in
Figures 4 through 7 to latch in a 16-bit word. Note that data is
valid on the falling edge of a clock pulse (for t13 greater than t18)
and the rising edge of the next clock pulse.
The AD974 provides error correction circuitry that can correct
for an improper bit decision made during the first half of the
conversion cycle. Normally the occurrence of an incorrect bit
decision during a conversion cycle is irreversible. This error
occurs as a result of noise during the time of the decision or due
to insufficient settling time. As the AD974 is performing a
conversion it is important that transitions not occur on digital
input/output pins or degradation of the conversion result could
occur. This is particularly important during the second half of
the conversion process. For this reason it is recommended that
when an external clock is being provided it be a discontinuous
clock that is not toggling during the time that BUSY is low or,
more importantly, that it does not transition during the latter
half of BUSY low.
EXTERNAL DISCONTINUOUS CLOCK DATA READ
AFTER CONVERSION WITH NO SYNC OUTPUT
GENERATEDFigure 4 illustrates the method by which data from conversion
“n” can be read after the conversion is complete using a discon-
tinuous external clock without the generation of a SYNC
output. After a conversion is complete, indicated by BUSY
returning high, the result of that conversion can be read whileCS is Low and R/C is high. In this mode CS can be tied low.
The MSB will be valid on the first falling edge and the second
rising edge of DATACLK. The LSB will be valid on the 16th
falling edge and the 17th rising edge of DATACLK. A mini-
mum of 16 clock pulses are required for DATACLK if the
receiving device will be latching data on the falling edge of
DATACLK. A minimum of 17 clock pulses are required for
DATACLK if the receiving device will be latching data on the
rising edge of DATACLK.
The advantage of this method of reading data is that data is not
being clocked out during a conversion and therefore conversion
performance is not degraded.
When reading data after the conversion is complete, with the
highest frequency permitted for DATACLK (15.15 MHz), the
maximum possible throughput is approximately 195 kHz, and
not the rated 200 kHz.
EXT
DATACLK
R/C
BUSY
SYNC
DATA
t12
t13Figure 4.Conversion and Read Timing Using an External Discontinuous Data Clock
(EXT/INT Set to Logic High, CS Set to Logic Low)
EXTERNAL DISCONTINUOUS CLOCK DATA READ
DURING CONVERSION WITH NO SYNC OUTPUT
GENERATEDFigure 5 illustrates the method by which data from conversion
“n-1” can be read during conversion “n” while using a discon-
tinuous external clock, without the generation of a SYNC out-
put. After a conversion is initiated, indicated by BUSY going
low, the result of the previous conversion can be read while CS
is low and R/C is high. In this mode CS can be tied low. The
MSB will be valid on the 1st falling edge and the 2nd rising edge of
DATACLK. The LSB will be valid on the 16th falling edge and
the 17th rising edge of DATACLK. A minimum of 16 clock
pulses are required for DATACLK if the receiving device will be
latching data on the falling edge of DATACLK. A minimum of
17 clock pulses are required for DATACLK if the receiving
device will be latching data on the rising edge of DATACLK.
In this mode the data should be clocked out during the first half
of BUSY so not to degrade conversion performance. This re-
quires use of a 10 MHz DATACLK or greater, with data being
read out as soon as the conversion process begins.
EXTERNAL DISCONTINUOUS CLOCK DATA READ
AFTER CONVERSION WITH SYNC OUTPUT GENERATEDFigure 6 illustrates the method by which data from conver-
sion “n” can be read after the conversion is complete using a
discontinuous external clock, with the generation of a SYNC
output. What permits the generation of a SYNC output is a
transition of DATACLK while either CS is high or while bothCS and R/C are low. After a conversion is complete, indicated
by BUSY returning high, the result of that conversion can be
read while CS is Low and R/C is high. In this mode CS can be
tied low. In Figure 6 clock pulse #0 is used to enable the gen-
eration of a SYNC pulse. The SYNC pulse is actually clocked
out approximately 40 ns after the rising edge of clock pulse #1.
The SYNC pulse will be valid on the falling edge of clock pulse
#1 and the rising edge of clock pulse #2. The MSB will be valid
on the falling edge of clock pulse #2 and the rising edge of clock
pulse #3. The LSB will be valid on the falling edge of clock
pulse #17 and the rising edge of clock pulse #18. The advan-
tage of this method of reading data is that it is not being clocked
out during a conversion and therefore conversion performance is
not degraded.
When reading data after the conversion is complete, with the
highest frequency permitted for DATACLK (15.15 MHz), the
maximum possible throughput is approximately 195 kHz and
not the rated 200 kHz.
EXT
DATACLK
R/C
BUSY
SYNC
DATAFigure 5.Conversion and Read Timing for Reading Previous Conversion Results During a Conversion
Using External Discontinuous Data Clock (EXT/INT Set to Logic High, CS Set to Logic Low)
EXT
DATACLK
R/C
BUSY
SYNC
DATA
t12
t15
AD974
EXTERNAL DISCONTINUOUS CLOCK DATA READ
DURING CONVERSION WITH SYNC OUTPUT
GENERATEDFigure 7 illustrates the method by which data from conversion
“n-1” can be read during conversion “n” while using a discon-
tinuous external clock, with the generation of a SYNC output.
What permits the generation of a SYNC output is a transition of
DATACLK while either CS is High or while both CS and R/C
are low. In Figure 7 a conversion is initiated by taking R/C low
with CS tied low. While this condition exists a transition of
DATACLK, clock pulse #0, will enable the generation of a
SYNC pulse. Less then 83 ns after R/C is taken low the BUSY
output will go low to indicate that the conversion process has
begun. Figure 7 shows R/C then going high and after a delay of
greater than 15 ns (t15) clock pulse #1 can be taken high to
request the SYNC output. The SYNC output will appear ap-
proximately 40 ns after this rising edge and will be valid on the
falling edge of clock pulse #1 and the rising edge of clock pulse
#2. The MSB will be valid approximately 40 ns after the rising
edge of clock pulse #2 and can be latched off either the falling
edge of clock pulse #2 or the rising edge of clock pulse #3. The
LSB will be valid on the falling edge of clock pulse #17 and the
rising edge of clock pulse #18.
Data should be clocked out during the first half of BUSY to
avoid degrading conversion performance. This requires use of a
10 MHz DATACLK or greater, with data being read out as
soon as the conversion process begins.
EXT
DATACLK
R/C
BUSY
SYNC
DATAFigure 7.Conversion and Read Timing for Reading Previous Conversion Results During a Conversion
Using External Discontinuous Data Clock (EXT/INT Set to Logic High, CS Set to Logic Low)
