AD9742ARU ,12-Bit, 165 MSPS TxDAC D/A ConverterSPECIFICATIONS Output, 50 Doubly Terminated, unless otherwise noted.)Parameter Min Typ Max UnitDY ..
AD9744ARU ,14-Bit, 165 MSPS TxDAC D/A ConverterSPECIFICATIONS Output, 50 Doubly Terminated, unless otherwise noted.)Parameter Min Typ Max UnitDY ..
AD9747BCPZ , Dual 8-/10-/12-/14-/16-Bit 250 MSPS Digital-to-Analog Converters
AD974AN ,4-Channel, 16-Bit, 200 kSPS Data Acquisition SystemSPECIFICATIONS S DIG ANA A Grade B GradeParameter Conditions Min Typ Max Min Typ Ma ..
AD974AR ,4-Channel, 16-Bit, 200 kSPS Data Acquisition SystemGENERAL DESCRIPTIONThe AD974 is a four-channel, data acquisition system with aserial interface. The ..
AD974BN ,4-Channel, 16-Bit, 200 kSPS Data Acquisition SystemSPECIFICATIONS (f = 200 kHz, V = V = +5 V, –408C to +858C)S DIG ANAParameter Symbol Min Typ Max Uni ..
ADS8327IRSAT ,2.7V~5.5V, 16 Bit 500KSPS Serial ADC 16-QFN -40 to 85ADS8327ADS8328
ADS8328IBPW ,2.7V~5.5V, 16 bit 500KSPS Serial ADC w 2-to-1 MUX 16-TSSOP -40 to 85MAXIMUM RATINGS(1)Over operating free-air temperature range, unless otherwise noted.UNIT+IN to AGND ..
ADS8328IBPWG4 ,2.7V~5.5V, 16 bit 500KSPS Serial ADC w 2-to-1 MUX 16-TSSOP -40 to 85maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
ADS8328IBRSAT ,2.7V~5.5V, 16 bit 500KSPS Serial ADC w 2-to-1 MUX 16-QFN -40 to 85FEATURES APPLICATIONS• Communications• 2.7-V to 5.5-V Analog Supply, Low Power:• Transducer Interfa ..
ADS8328IPW ,2.7V~5.5V, 16 bit 500KSPS Serial ADC w 2-to-1 MUX 16-TSSOP -40 to 85This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated cir ..
ADS8328IPWG4 ,2.7V~5.5V, 16 bit 500KSPS Serial ADC w 2-to-1 MUX 16-TSSOP -40 to 85.2 Submit Documentation Feedback 2006–2011, Texas Instruments IncorporatedProduct Folder Link(s): A ..
AD9742AR-AD9742ARU
12-Bit, 165 MSPS TxDAC D/A Converter
12-Bit, 165 MSPS
TxDAC D/A ConverterREV.0
PRODUCT DESCRIPTIONThe AD9742 is a 12-bit resolution, wideband, third generation
member of the TxDAC series of high-performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC family,
consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is
specifically optimized for the transmit signal path of communica-
tion systems. All of the devices share the same interface options,
small outline package, and pinout, providing an upward or down-
ward component selection path based on performance, resolution,
and cost. The AD9742 offers exceptional ac and dc performance
while supporting update rates up to 165 MSPS.
The AD9742’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can be
further reduced to a mere 60 mW with a slight degradation in
performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 15 mW. A segmented current source architecture
is combined with a proprietary switching technique to reduce
spurious components and enhance dynamic performance. Edge-
triggered input latches and a 1.2 V temperature compensated
band gap reference have been integrated to provide a complete
monolithic DAC solution. The digital inputs support 3 V CMOS
logic families.
PRODUCT HIGHLIGHTSThe AD9742 is the 12-bit member of the pin compatible
TxDAC family that offers excellent INL and DNL
performance.Data input supports two’s complement or straight binary
data coding.High-speed, single-ended CMOS clock input supports
165 MSPS conversion rate.Low power: Complete CMOS DAC function operates on
135 mW from a 3.0 V to 3.6 V single supply. The DAC full-
scale current can be reduced for lower power operation, and
a sleep mode is provided for low power idle periods.On-chip voltage reference: The AD9742 includes a 1.2 V
temperature-compensated band gap voltage reference.Industry standard 28-lead SOIC and TSSOP packages.
TxDAC is a registered trademark of Analog Devices, Inc.. Patent Numbers 5568145, 5689257, and 5703519.
12-Bit, 165 MSPS
TxDAC D/A Converter
FUNCTIONAL BLOCK DIAGRAM
FEATURES
High Performance Member of Pin-Compatible
TxDAC Product Family
Excellent Spurious-Free Dynamic Range Performance
SNR @ 5 MHz Output, 125 MSPS: 73 dB
Two’s Complement or Straight Binary Data Format
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 135 mW @ 3.3 V
Power-Down Mode: 15 mW @ 3.3 V
On-Chip 1.20 V Reference
CMOS-Compatible Digital Interface
Package: 28-Lead SOIC and TSSOP Packages
Edge-Triggered Latches
APPLICATIONS
Wideband Communication Transmit Channel:
Direct IF
Base Stations
Wireless Local Loop
Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation
AD9742
DC SPECIFICATIONSNOTESMeasured at IOUTA, driving a virtual ground.Nominal full-scale current, IOUTFS, is 32 times the IREF current.An external buffer amplifier with input bias current <100 nA should be used to drive any external load.Measured at fCLOCK = 25 MSPS and fOUT = 1.0 MHz.Measured as unbuffered voltage output with IOUTFS = 20 mA and 50 W RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz.±5% power supply variation.
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.)
AD9742NOTESMeasured single-ended into 50 W load.Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.
Specifications subject to change without notice.
DYNAMIC SPECIFICATIONS
(TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, Differential Transformer Coupled
Output, 50 � Doubly Terminated, unless otherwise noted.)
AD9742
DIGITAL SPECIFICATIONS
(TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.)
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9742 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE*R = Small Outline IC; RU = Thin Shrink Small Outline Package
THERMAL CHARACTERISTICS
Thermal Resistance28-Lead 300-Mil SOICJA= 71.4∞C/W
28-Lead TSSOPJA= 97.9∞C/W
ABSOLUTE MAXIMUM RATINGS*Storage Temperature
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
Figure 1.Timing Diagram
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
AD9742
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)Linearity error is defined as the maximum deviation of the actual
analog output from the ideal output, determined by a straight line
drawn from zero to full scale.
Differential Nonlinearity (or DNL)DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
MonotonicityA D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset ErrorThe deviation of the output current from the ideal of zero is
called the offset error. For IOUTA, 0 mA output is expected
when the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain ErrorThe difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance RangeThe range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
Temperature DriftTemperature drift is specified as the maximum change from the
ambient (25∞C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale range
(FSR) per ∞C. For reference drift, the drift is reported in ppm per ∞C.
Power Supply RejectionThe maximum change in the full-scale output as the supplies are
varied from nominal to minimum and maximum specified voltages.
Settling TimeThe time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch ImpulseAsymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic RangeThe difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic DistortionTHD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Multitone Power RatioThe spurious-free dynamic range containing multiple carrier
tones of equal amplitude. It measures as the difference between
the rms amplitude of a carrier tone to the peak spurious signal
in the region of a removed tone.
Figure 2.Basic AC Characterization Test Setup
TPC 1. SFDR vs. fOUT @ 0 dBFS
TPC 4.SFDR vs. fOUT @ 165 MSPS
TPC 7.Single-Tone SFDR vs.
AOUT @ fOUT = fCLOCK/5
TPC 2.SFDR vs. fOUT @ 65 MSPS
TPC 5.SFDR vs. fOUT and IOUTFS
@ 65 MSPS and 0 dBFS
TPC 8.SNR vs. fCLOCK and
IOUTFS @ fOUT = 5 MHz and 0 dBFS
TPC 3.SFDR vs. fOUT @ 125 MSPS
TPC 6.Single-Tone SFDR vs.
AOUT @ fOUT = fCLOCK/11
TPC 9. Dual-Tone IMD vs. AOUT
@ fOUT = fCLOCK/7
AD9742TPC 12. SFDR vs. Temperature @
165 MSPS, 0 dBFS
TPC 15.Four-Tone SFDR
TPC 10. Typical INL
TPC 13.Single-Tone SFDR
TPC 11. Typical DNL
TPC 14.Dual-Tone SFDR
FUNCTIONAL DESCRIPTIONFigure 3 shows a simplified block diagram of the AD9742. The
AD9742 consists of a DAC, digital control logic, and full-scale
output current control. The DAC contains a PMOS current
source array capable of providing up to 20 mA of full-scale
current (IOUTFS). The array is divided into 31 equal currents
that make up the five most significant bits (MSBs). The next
four bits, or middle bits, consist of 15 equal current sources
whose value is 1/16th of an MSB current source. The remaining
LSBs are binary weighted fractions of the middle bits current
sources. Implementing the middle and lower bits with current
sources, instead of an R-2R ladder, enhances its dynamic perfor-
mance for multitone or low amplitude signals and helps maintain
the DAC’s high output impedance (i.e., >100 kW).
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on the
architecture that was pioneered in the AD9764 family, with
further refinements to reduce distortion contributed by the
switching transient. This switch architecture also reduces
various timing errors and provides matching complementary
drive signals to the inputs of the differential current switches.
The analog and digital sections of the AD9742 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 3.0 V to 3.6 V range. The digital section,
which is capable of operating up to a 165 MSPS clock rate,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.2 V band gap
voltage reference, and a reference control amplifier.
The DAC full-scale output current is regulated by the refer-
ence control amplifier and can be set from 2 mA to 20 mA via
an external resistor, RSET, connected to the full-scale adjust
(FSADJ) pin. The external resistor, in combination with both
the reference control amplifier and voltage reference, VREFIO,
sets the reference current IREF, which is replicated to the
segmented current sources with the proper scaling factor. The
full-scale current, IOUTFS, is 32 times IREF.
REFERENCE OPERATIONThe AD9742 contains an internal 1.2 V band gap reference.
The internal reference can be disabled by raising REFLO to
AVDD. It can also be easily overridden by an external reference
with no effect on performance. REFIO serves as either an input
or output depending on whether the internal or an external
reference is used. To use the internal reference, simply decouple
the REFIO pin to ACOM with a 0.1 mF capacitor and connect
REFLO to ACOM via a resistance less than 5 W. The internal
reference voltage will be present at REFIO. If the voltage at
REFIO is to be used anywhere else in the circuit, an external
buffer amplifier with an input bias current of less than 100 nA
should be used. An example of the use of the internal reference
is given in Figure 4.
Figure 4.Internal Reference Configuration
An external reference can be applied to REFIO as shown in
Figure 5. The external reference may provide either a fixed refer-
ence voltage to enhance accuracy and drift performance or a
varying reference voltage for gain control. Note that the 0.1 mF
compensation capacitor is not required since the internal refer-
ence is overridden, and the relatively high input impedance of
REFIO minimizes any loading of the external reference.
DIGITAL DATA INPUTS (DB11DB0)
3.3V
2k�
0.1�F
CLOCKFigure 3.Simplified Block Diagram
AD9742
REFERENCE CONTROL AMPLIFIERThe AD9742 contains a control amplifier that is used to regu-
late the full-scale output current, IOUTFS. The control amplifier
is configured as a V-I converter as shown in Figure 4, so that its
current output, IREF, is determined by the ratio of the VREFIO
and an external resistor, RSET, as stated in Equation 4. IREF is
copied to the segmented current sources with the proper scale
factor to set IOUTFS as stated in Equation 3.
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS over a 2mA to 20 mA range by setting IREF between
62.5mA and 625mA. The wide adjustment span of IOUTFS provides
several benefits. The first relates directly to the power dissipation
of the AD9742, which is proportional to IOUTFS (refer to the
Power Dissipation section). The second relates to the 20dB
adjustment, which is useful for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low-frequency small
signal multiplying applications.
DAC TRANSFER FUNCTIONBoth DACs in the AD9742 provide complementary current
outputs, IOUTA and IOUTB. IOUTA will provide a near full-
scale current output, IOUTFS, when all bits are high (i.e., DAC
CODE = 4095), while IOUTB, the complementary output,
provides no current. The current output appearing at IOUTA
and IOUTB is a function of both the input code and IOUTFS and
can be expressed as:(1)(2)
where DAC CODE = 0 to 4095 (i.e., Decimal Representation).
As mentioned previously, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage,
VREFIO, and external resistor, RSET. It can be expressed as:(3)
where(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, that are tied to analog common, ACOM. Note,
RLOAD may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated
50 W or 75 W cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply;(5)
(6)
Note the full-scale value of VOUTA and VOUTB should not exceed
the specified output compliance range to maintain specified
distortion and linearity performance.
Substituting the values of IOUTA, IOUTB, IREF, and VDIFF can
be expressed as:(8)
These last two equations highlight some of the advantages of
operating the AD9742 differentially. First, the differential
operation will help cancel common-mode error sources associ-
ated with IOUTA, and IOUTB such as noise, distortion, and dc
offsets. Second, the differential code dependent current and
subsequent voltage, VDIFF, is twice the value of the single-ended
voltage output (i.e., VOUTA or VOUTB), thus providing twice the
signal power to the load.
Note, the gain drift temperature performance for a single-ended
(VOUTA and VOUTB) or differential output (VDIFF) of the AD9742
can be enhanced by selecting temperature tracking resistors for
RLOAD and RSET due to their ratiometric relationship as shown in
Equation 8.
ANALOG OUTPUTSThe complementary current outputs in each DAC, IOUTA and
IOUTB, may be configured for single-ended or differential
operation. IOUTA and IOUTB can be converted into comple-
mentary single-ended voltage outputs, VOUTA and VOUTB, via a
load resistor, RLOAD, as described in the DAC Transfer Function
section by Equations 5 through 8. The differential voltage, VDIFF,
existing between VOUTA and VOUTB can also be converted to a
single-ended voltage via a transformer or differential amplifier
configuration. The ac performance of the AD9742 is optimum and
specified using a differential transformer coupled output in which
the voltage swing at IOUTA and IOUTB is limited to ±0.5V.
The distortion and noise performance of the AD9742 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can
be significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode error
sources include even-order distortion products and noise. The
enhancement in distortion performance becomes more signifi-
cant as the frequency content of the reconstructed waveform
increases and/or its amplitude decreases. This is due to the first
order cancellation of various dynamic common-mode distortion
mechanisms, digital feedthrough, and noise.
Performing a differential-to-single-ended conversion via a trans-
former also provides the ability to deliver twice the reconstructed
signal power to the load (i.e., assuming no source termination).
Since the output currents of IOUTA and IOUTB are comple-
mentary, they become additive when processed differentially. A
properly selected transformer will allow the AD9742 to provide
the required power and voltage levels to different loads.
The output impedance of IOUTA and IOUTB is determined
by the equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 100kW in
parallel with 5 pF. It is also slightly dependent on the output
voltage (i.e., VOUTA and VOUTB) due to the nature of a PMOS
device. As a result, maintaining IOUTA and/or IOUTB at a
