AD9742ACP ,12-Bit, 165 MSPS TxDAC® D/A ConverterGENERAL DESCRIPTION sated band gap reference have been integrated to provide a 1The AD9742 is a 12 ..
AD9742AR ,12-Bit, 165 MSPS TxDAC D/A ConverterSPECIFICATIONS (T to T , AVDD = 3.3 V, DVDD = 3.3 V, I = 20 mA, unless otherwise noted.)MIN MAX OUT ..
AD9742ARU ,12-Bit, 165 MSPS TxDAC D/A ConverterSPECIFICATIONS Output, 50 Doubly Terminated, unless otherwise noted.)Parameter Min Typ Max UnitDY ..
AD9744ARU ,14-Bit, 165 MSPS TxDAC D/A ConverterSPECIFICATIONS Output, 50 Doubly Terminated, unless otherwise noted.)Parameter Min Typ Max UnitDY ..
AD9747BCPZ , Dual 8-/10-/12-/14-/16-Bit 250 MSPS Digital-to-Analog Converters
AD974AN ,4-Channel, 16-Bit, 200 kSPS Data Acquisition SystemSPECIFICATIONS S DIG ANA A Grade B GradeParameter Conditions Min Typ Max Min Typ Ma ..
ADS8327IRSAT ,2.7V~5.5V, 16 Bit 500KSPS Serial ADC 16-QFN -40 to 85ADS8327ADS8328
ADS8328IBPW ,2.7V~5.5V, 16 bit 500KSPS Serial ADC w 2-to-1 MUX 16-TSSOP -40 to 85MAXIMUM RATINGS(1)Over operating free-air temperature range, unless otherwise noted.UNIT+IN to AGND ..
ADS8328IBPWG4 ,2.7V~5.5V, 16 bit 500KSPS Serial ADC w 2-to-1 MUX 16-TSSOP -40 to 85maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
ADS8328IBRSAT ,2.7V~5.5V, 16 bit 500KSPS Serial ADC w 2-to-1 MUX 16-QFN -40 to 85FEATURES APPLICATIONS• Communications• 2.7-V to 5.5-V Analog Supply, Low Power:• Transducer Interfa ..
ADS8328IPW ,2.7V~5.5V, 16 bit 500KSPS Serial ADC w 2-to-1 MUX 16-TSSOP -40 to 85This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated cir ..
ADS8328IPWG4 ,2.7V~5.5V, 16 bit 500KSPS Serial ADC w 2-to-1 MUX 16-TSSOP -40 to 85.2 Submit Documentation Feedback 2006–2011, Texas Instruments IncorporatedProduct Folder Link(s): A ..
AD9742ACP
12-Bit, 165 MSPS TxDAC® D/A Converter
12-Bit, 210 MSPS
TxDAC® D/A Converter
Rev. B
FEATURES
High performance member of pin-compatible
TxDAC product family
Excellent spurious-free dynamic range performance
SNR @ 5 MHz output, 125 MSPS: 70 dB
Twos complement or straight binary data format
Differential current outputs: 2 mA to 20 mA
Power dissipation: 135 mW @ 3.3 V
Power-down mode: 15 mW @ 3.3 V
On-chip 1.2 V Reference
CMOS compatible digital interface
28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP
packages
Edge-triggered latches
APPLICATIONS
Wideband communication transmit channel:
Direct IF
Base stations
Wireless local loops
Digital radio links
Direct digital synthesis (DDS)
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
3.3VRSET
SLEEP02913-B
DIGITAL DATA INPUTS (DB11–DB0)
Figure 1.
GENERAL DESCRIPTION The AD97421 is a 12-bit resolution, wideband, third generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC family,
consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is
specifically optimized for the transmit signal path of communi-
cation systems. All of the devices share the same interface
options, small outline package, and pinout, providing an upward
or downward component selection path based on performance,
resolution, and cost. The AD9742 offers exceptional ac and dc
performance while supporting update rates up to 210 MSPS.
The AD9742’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can
be further reduced to a mere 60 mW with a slight degradation
in performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 15 mW. A segmented current source architecture
is combined with a proprietary switching technique to reduce
spurious components and enhance dynamic performance.
Edge-triggered input latches and a 1.2 V temperature compen-
sated band gap reference have been integrated to provide a
complete monolithic DAC solution. The digital inputs support
3 V CMOS logic families.
PRODUCT HIGHLIGHTS 1. The AD9742 is the 12-bit member of the pin-compatible
TxDAC family, which offers excellent INL and DNL
performance.
2. Data input supports twos complement or straight binary
data coding.
3. High speed, single-ended CMOS clock input supports
210 MSPS conversion rate.
4. Low power: Complete CMOS DAC function operates on
135 mW from a 2.7 V to 3.6 V single supply. The DAC full-
scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.
5. On-chip voltage reference: The AD9742 includes a 1.2 V
temperature compensated band gap voltage reference.
6. Industry-standard 28-lead SOIC, 28-lead TSSOP, and
32-lead LFCSP packages.
1 . Patent Numbers 5568145, 5689257, and 5703519.
TABLE OF CONTENTS Specifications.....................................................................................3
DC Specifications.........................................................................3
Dynamic Specifications...............................................................4
Digital Specifications...................................................................5
Absolute Maximum Ratings............................................................6
Thermal Characteristics..............................................................6
ESD Caution..................................................................................6
Pin Configuration and Function Descriptions.............................7
Terminology......................................................................................8
Typical Performance Characteristics.............................................9
Functional Description..................................................................12
Reference Operation..................................................................12
Reference Control Amplifier.....................................................13
DAC Transfer Function.............................................................13
Analog Outputs...........................................................................13
Digital Inputs..............................................................................14
Clock Input..................................................................................14
DAC Timing................................................................................15
Power Dissipation.......................................................................15
Applying the AD9742................................................................16
Differential Coupling Using a Transformer................................16
Differential Coupling Using an Op Amp................................16
Single-Ended, Unbuffered Voltage Output.............................17
Single-Ended, Buffered Voltage Output Configuration........17
Power and Grounding Considerations, Power Supply
Rejection......................................................................................17
Evaluation Board............................................................................19
General Description...................................................................19
Outline Dimensions.......................................................................29
Ordering Guide...........................................................................30
REVISION HISTORY
6/04—Data Sheet Changed from Rev. A to Rev. B Changes to the Title.................................................................................1
Changes to General Description............................................................1
Changes to Product Highlights..............................................................1
Changes to Dynamic Specifications......................................................4
Changes to Figures 6 and 10...................................................................9
Changes to Figures 12 to 15.................................................................10
Changes to the Functional Description Section................................12
Changes to the Digital Inputs Section................................................14
Changes to Figure 29.............................................................................15
Changes to Figure 30.............................................................................16
5/03—Data Sheet Changed from Rev. 0 to Rev. A Added 32-Lead LFCSP Package...........................................Universal
Edits to Features.....................................................................................1
Edits to Product Highlights..................................................................1
Edits to DC Specifications....................................................................2
Edits to Dynamic Specifications..........................................................3
Edits to Digital Specifications..............................................................4
Edits to Absolute Maximum Ratings..................................................5
Edits to Thermal Characteristics.........................................................5
Edits to Ordering Guide.......................................................................5
Edits to Pin Configuration...................................................................6
Edits to Pin Function Descriptions.....................................................6
Edits to Figure 2.....................................................................................7
Replaced TPCs 1, 4, 7, and 8................................................................8
Edits to Figure 3...................................................................................10
Edits to Functional Description Section..........................................10
Added Clock Input Section................................................................12
Added Figure 7.....................................................................................12
Edits to DAC Timing Section............................................................12
Edits to Sleep Mode Operation Section............................................13
Edits to Power Dissipation Section...................................................13
Renumbered Figures 8 to 26..............................................................13
Added Figure 11...................................................................................13
Added Figures 27 to 35.......................................................................21
Updated Outline Dimensions............................................................26
5/02—Revision 0: Initial Version SPECIFICATIONS
DC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1. Measured at IOUTA, driving a virtual ground.
2 Nominal full-scale current, IOUTFS, is 32 times the IREF current. An external buffer amplifier with input bias current <100 nA should be used to drive any external load. Measured at fCLOCK = 25 MSPS and fOUT = 1 MHz. Measured as unbuffered voltage output with IOUTFS = 20 mA and 50 Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz. ±5% power supply variation.
DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly ter-
minated, unless otherwise noted.
Table 2 1 Measured single-ended into 50 Ω load. Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only. Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.
DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 3. 1 Includes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode. Applicable to CLK+ and CLK− inputs when configured for differential or PECL clock input mode.
0.1%0.1%
DB0–DB11
CLOCK
IOUTA
IOUTB02912-B
Figure 2. Timing Diagram
