AD9740ACP ,10-Bit, 165 MSPS TxDAC® D/A ConverterSPECIFICATIONS coupled output, 50 doubly terminated, unless otherwise noted.)Parameter Min Typ Ma ..
AD9740AR ,10-Bit, 165 MSPS TxDAC D/A ConverterSPECIFICATIONS Output, 50 Doubly terminated, unless otherwise noted.)Parameter Min Typ Max UnitDY ..
AD9740ARUZ-RL7 , 10-Bit, 210 MSPS TxDAC D/A Converter
AD9742ACP ,12-Bit, 165 MSPS TxDAC® D/A ConverterGENERAL DESCRIPTION sated band gap reference have been integrated to provide a 1The AD9742 is a 12 ..
AD9742AR ,12-Bit, 165 MSPS TxDAC D/A ConverterSPECIFICATIONS (T to T , AVDD = 3.3 V, DVDD = 3.3 V, I = 20 mA, unless otherwise noted.)MIN MAX OUT ..
AD9742ARU ,12-Bit, 165 MSPS TxDAC D/A ConverterSPECIFICATIONS Output, 50 Doubly Terminated, unless otherwise noted.)Parameter Min Typ Max UnitDY ..
ADS8326IDRBT ,16-Bit, Pseudo Diff Input, 250kSPS Serial Out, 2.7V to 5.5V Micro Power Sampling ADC 8-SON -40 to 85.. SBAS343C –MAY 2007–REVISED SEPTEMBER 2009DISSIPATION RATINGSDERATINGFACTOR ABOVE T≤ +25°C T = +7 ..
ADS8327IBPW ,2.7V~5.5V, 16 Bit 500KSPS Serial ADC 16-TSSOP -40 to 85MAXIMUM RATINGS(1)Over operating free-air temperature range, unless otherwise noted.UNIT+IN to AGND ..
ADS8327IBPWG4 ,2.7V~5.5V, 16 Bit 500KSPS Serial ADC 16-TSSOP -40 to 85maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
ADS8327IBRSAT ,2.7V~5.5V, 16 Bit 500KSPS Serial ADC 16-QFN -40 to 85FEATURES APPLICATIONS• Communications• 2.7-V to 5.5-V Analog Supply, Low Power:• Transducer Interfa ..
ADS8327IPW ,2.7V~5.5V, 16 Bit 500KSPS Serial ADC 16-TSSOP -40 to 85This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated cir ..
ADS8327IRSAT ,2.7V~5.5V, 16 Bit 500KSPS Serial ADC 16-QFN -40 to 85ADS8327ADS8328
AD9740ACP
10-Bit, 165 MSPS TxDAC® D/A Converter
REV. A
10-Bit, 165 MSPS
TxDAC D/A Converters*. Patent Numbers 5568145, 5689257, and 5703519.
FEATURES
High Performance Member of Pin Compatible
TxDAC Product Family
Excellent Spurious-Free Dynamic Range Performance
SNR @ 5 MHz Output, 125 MSPS: 65 dB
Twos Complement or Straight Binary Data Format
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 135 mW @ 3.3 V
Power-Down Mode: 15 mW @ 3.3 V
On-Chip 1.2 V Reference
CMOS Compatible Digital Interface
28-Lead SOIC, 28-Lead TSSOP, and 32-Lead LFCSP
Packages
Edge-Triggered Latches
APPLICATIONS
Wideband Communication Transmit Channel:
Direct IF
Base Stations
Wireless Local Loop
Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe AD9740 is a 10-bit resolution, wideband, third generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC family,
consisting of pin compatible 8-, 10-, 12-, and 14-bit DACs, is
specifically optimized for the transmit signal path of communica-
tion systems. All of the devices share the same interface options,
small outline package, and pinout, providing an upward or
downward component selection path based on performance,
resolution, and cost. The AD9740 offers exceptional ac andperformance while supporting update rates up to 165 MSPS.
The AD9740’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation canfurther reduced to a mere 60 mW with a slight degradation
in performance by lowering the full-scale current output. Also,power-down mode reduces the standby power dissipation to
approximately 15 mW. A segmented current source architecture
is combined with a proprietary switching technique to reduce
spurious components and enhance dynamic performance. Edge-
triggered input latches and a 1.2 V temperature compensated
band gap reference have been integrated to provide a complete
monolithic DAC solution. The digital inputs support 3 V CMOS
logic families.
PRODUCT HIGHLIGHTSThe AD9740 is the 10-bit member of the pin compatible
TxDAC family, which offers excellent INL and DNL
performance.Data input supports twos complement or straight binary data
coding.High speed, single-ended CMOS clock input supports
165MSPS conversion rate.Low power: Complete CMOS DAC function operates on
135 mW from a 2.7 V to 3.6 V single supply. The DAC full-
scale current can be reduced for lower power operation, and
a sleep mode is provided for low power idle periods.On-chip voltage reference: The AD9740 includes a 1.2V
temperature compensated band gap voltage reference.Industry-standard 28-lead SOIC, 28-lead TSSOP, and 32-lead
LFCSP packages.
AD9740–SPECIFICATIONS
(TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.)DC SPECIFICATIONSANALOG OUTPUT
REFERENCE INPUT
NOTESMeasured at IOUTA, driving a virtual ground.Nominal full-scale current, IOUTFS, is 32 times the IREF current.An external buffer amplifier with input bias current <100 nA should be used to drive any external load.Measured at fCLOCK = 25 MSPS and fOUT = 1 MHz.Measured as unbuffered voltage output with IOUTFS = 20 mA and 50 W RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz.±5% power supply variation.
Specifications subject to change without notice.
AD9740
DYNAMIC SPECIFICATIONSAC LINEARITY
NOTESMeasured single-ended into 50 W load.Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, differential transformer
coupled output, 50� doubly terminated, unless otherwise noted.)
AD9740
(TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.)DIGITAL SPECIFICATIONSCLK INPUTS
NOTESIncludes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode.Applicable to CLK+ and CLK– inputs when configured for differential or PECL clock input mode.
Specifications subject to change without notice.
Figure 1. Timing Diagram
ORDERING GUIDE*R = Small Outline IC; RU = Thin Shrink Small Outline Package; CP = Lead Frame Chip Scale Package
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9740 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
THERMAL CHARACTERISTICS*
Thermal Resistance28-Lead 300-Mil SOIC
�JA = 55.9°C/W
28-Lead TSSOP
�JA = 67.7°C/W
32-Lead LFCSP
�JA = 32.5°C/W
*Thermal impedance measurements were taken on a 4-layer board in still air, in
accordance with EIA/JESD51-7.
ABSOLUTE MAXIMUM RATINGS*
ParameterAVDD
DVDD
CLKVDD
ACOM
ACOM
DCOM
AVDD
AVDD
DVDD
CLOCK, SLEEP
Digital Inputs, MODE
IOUTA, IOUTB
REFIO, REFLO, FSADJ
CLK+, CLK–, CMODE
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
