AD9732BRS Fast Delivery |IC PHOENIX CO.,LIMITED

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AD9732BRS
10-Bit, 200 MSPS D/A Converter
REV. A
10-Bit, 200 MSPS
D/A Converter
FUNCTIONAL BLOCK DIAGRAM
FEATURES
200 MSPS Throughput Rate
3.3 V PECL Digital Input
65 dB SFDR @ 2 MHz AOUT, 200 MSPS/54 dB @ 40 MHz
AOUT, 200 MSPS
Low Power: 305 mW
Fast Settling: 5 ns to 1/2 LSB
Low Glitch Energy: 6 pVs
Internal Reference
28-Lead SSOP Packaging
APPLICATIONS
Digital Communications
Direct Digital Synthesis
Waveform Reconstruction
High Speed Imaging
GENERAL DESCRIPTION
The AD9732 is a 10-bit, 200 MSPS, bipolar D/A converter that
is optimized to provide high dynamic performance, yet offers
lower power dissipation and a more economical price than pre-
vious high speed DAC solutions. The AD9732 was primarily
designed for demanding communications systems applications
where maximum spurious-free dynamic range (SFDR) is required
at high throughput rates. The proliferation of digital communi-
cations into base station and high volume subscriber-end mar-
kets has created a demand for high performance bipolar DACs
delivered at CMOS associated levels of power dissipation and
cost. The AD9732 is the answer to that demand.
Optimized for direct digital synthesis (DDS) and digital modu-
lator waveform reconstruction, the AD9732 provides >50 dB of
wideband harmonic suppression over the dc to 80 MHz analog
output bandwidth. This signal bandwidth addresses the transmit
spectrum in many of the emerging digital communications ap-
plications where signal purity is critical. Narrowband (–1 MHz
window), the AD9732 provides an SFDR of greater than 75 dB.
This level of wideband and narrowband ac performance, coupled
with its 200 MSPS throughput rate, enables the AD9732 to
present outstanding value in the high speed DAC function.
The AD9732 is packaged in a 28-lead SSOP and is specified to
operate over the extended industrial temperature range of –40°C
to +85°C. Digital inputs and clock are positive-ECL compatible.
AD9732–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS(+VS = +5 V, ENCODE = 125 MSPS, RSET = 1.95 kV (for 20 mA IOUT) unless otherwise noted)
AD9732
NOTESMeasured as an error in ratio of full-scale current to current through RSET (640 mA nominal); ratio is nominally 32. DAC load is virtual ground.Internal reference voltage is tested under load conditions specified in Internal Reference Output Current specification.Internal reference output current defines load conditions applied during Internal Reference Voltage test.Full-scale current variations among devices are higher when driving REFERENCE IN directly.Frequency at which a 3 dB change in output of DAC is observed; RL = 50 W; 100 mV modulation at midscale.Based on IFS = 32 ([CONTROL AMP IN – (+VS)]/RSET) when using internal control amplifier. DAC load is virtual ground.Measured as voltage settling at midscale transition to 0.1%; RL = 50 W.Measured from 50% point of rising edge of CLOCK signal to 1/2 LSB change in output signal.Peak glitch impulse is measured as the largest area under a single positive or negative transient.Measured with RL = 50 W and DAC operating in latched mode.Data must remain stable for a specified time prior to rising edge of CLOCK.Data must remain stable for a specified time after rising edge of CLOCK.Supply voltages should remain stable with –5% for nominal operation.Power dissipation calculation includes current through a 50 W load.SFDR is defined as the difference in signal energy between the full-scale fundamental signal and worst case spurious frequencies in the output spectrum window.
The frequency span dc to Nyquist unless otherwise noted.Intermodulation distortion is the measure of the sum and difference products produced when a two-tone input is driven into the DAC. The distortion products
created will manifest themselves at sum and difference frequencies of the two tones.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level100% production tested.100% production tested at +25°C and sample tested at
specified temperatures.
IIISample tested only.Parameter is guaranteed by design and characterization
testing.Parameter is a typical value only.100% production tested at +25°C; guaranteed by design
and characterization testing for industrial temperature
range.
ORDERING GUIDE
AD9732
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9732 features proprietary ESD protection circuitry, permanent damage may
ABSOLUTE MAXIMUM RATINGS*
Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+VS
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +VS
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . .30 mA
Control Amplifier Input Voltage Range . . . . . . . . .0 V to +VS
Reference Input Voltage Range . . . . . . . . . . . . . . .0 V to +VS
Internal Reference Output Current . . . . . . . . . . . . . . .500 mA
Control Amplifier Output Current . . . . . . . . . . . . . .–2.5 mA
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +175°C
Lead Temperature (10 sec) Soldering . . . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
NC = NO CONNECT
DIGITAL +VS
CLOCK
D0 (LSB)
D9 (MSB)
DIGITAL +VS
GND
RSET
ANALOG +VS
ANALOG RETURN
IOUT
IOUTB
DIGITAL +VS
GND
CONTROL AMP IN
REF OUT
GND
REF IN
CONTROL AMP OUT
CODE 4
CODE 2
CODE 1
CODE 3
CLOCK
DATA
ANALOG OUTPUT
ERROR BANDtPD
tST
CLOCK
ANALOG OUTPUT
DETAIL OF SETTLING TIME
Figure 1.Timing Diagrams
AD9732
AOUT – MHz100102030405060708090
SFDR – dB50
Figure 2. Narrowband SFDR (Clock = 200 MHz) vs. AOUT
Frequency
AOUT – MHz56010
SFDR – dB2025303540455055
Figure 3. Narrowband SFDR (Clock = 125 MHz) vs. AOUT
Frequency
AOUT – MHz9020
SFDR – dB4050607080
Figure 4. Wideband SFDR (200 MHz Clock) vs. AOUT
Figure 5. SFDR vs. IOUT
CLOCK – MHz5145
SFDR – dB456585105125
165185205
Figure 6. SFDR vs. Clock for fCLK/AOUT = 3.125
Figure 7. Typical Differential Nonlinearity Performance
(DNL)

Partno	Mfg	Dc	Qty	Available	Descript
AD9732BRS	AD	N/a	4	avai	10-Bit, 200 MSPS D/A Converter