AD9726BSVZ ,16-Bit, 600 MSPS TxDAC+® D/A ConverterAPPLICATIONS CLK+Instrumentation and test CLK–Wideband communications systems Point-to-point wirel ..
AD9726BSVZ ,16-Bit, 600 MSPS TxDAC+® D/A ConverterFEATURES FUNCTIONAL BLOCK DIAGRAM600+ MSPS DAC update rate FSADJ16/14/12/10-bit resolution family C ..
AD9731BR ,10-Bit, 170 MSPS D/A ConverterSPECIFICATIONSREFParameter Temp Test Level Min Typ Max UnitsRESOLUTION 10 BitsTHROUGHPUT RATE +25
AD9726BSVZ
16-Bit, 600 MSPS TxDAC+® D/A Converter
16-Bit, 600+ MSPS
D/A Converter
Rev. PrD
FEATURES 600+ MSPS DAC update rate
16/14/12/10-bit resolution family
LVDS interface with built-in 100-termination resistors
Single data rate and double data rate capability
Excellent dynamic performance
SFDR = 65 dBc at 140 MHz
IMD = 75 dBc at 140 MHz
Differential current outputs: 2 mA to 20 mA
–40°C to +85°C temperature range operation
On-chip 1.20 V reference
Package: 80-lead thermally-enhanced TQFP
Versatile clock and data interface
APPLICATIONS Instrumentation and test
Wideband communications systems
Point-to-point wireless
LMDS
PA linearization
High resolution displays
FUNCTIONAL BLOCK DIAGRAM
SDIO
CSB
IOUTA
IOUTB
FSADJ
REFIO
SDO/SYNC_ALRM
SCLK/SYNC_UPD
RESET
DB[15:0]+
DB[15:0]–
DATACLK_IN+
DATACLK_IN–
REXT
DATACLK_OUT+
DATACLK_OUT–
CLK+
CLK–
DDR04540-0-001
Figure 1
PRODUCT DESCRIPTION The AD9726 is a 16-bit digital-to-analog converter (DAC) that
utilizes an LVDS interface to achieve conversion rates in excess
of 600 MSPS. It is in a family of pin compatible converters that
offers selection of 10-bit, 12-bit, 14-bit, and 16-bit resolution
grades. All of the devices share the same interface options, small
outline package, and pinout, providing an upward or downward
component selection path based on performance, resolution
and cost.
PRODUCT HIGHLIGHTS Ultralow noise and intermodulation distortion (IMD) enable
high quality waveform synthesis at intermediate frequencies up
to 200 MHz.
LVDS receivers support SDR or DDR modes, with the maxi-
mum conversion rate exceeding 600 MSPS.
Manufactured on a CMOS process, the AD9726 uses a proprie-
tary switching technique that enhances dynamic performance.
The current output of the AD9726 can be easily configured for
various single-ended or differential circuit topologies.
TABLE OF CONTENTS Specifications.....................................................................................3
DC Specifications.........................................................................3
AC Specifications..........................................................................4
Digital Specifications...................................................................5
Digital Timing Information........................................................5
Absolute Maximum Ratings............................................................6
Pin Configuration and Function Description..............................7
Serial Port Interface Register Maps................................................9
Definitions.......................................................................................11
Typical Performance Curves.........................................................12
Theory of Operation......................................................................13
LVDS Inputs................................................................................13
Data Synchronization Circuitry...............................................13
Internal Reference and Full-Scale Output Current................13
Analog Output............................................................................14
SPI Port Control.........................................................................14
General Operation of the Serial Port Interface......................14
Instruction Byte..........................................................................14
Serial Port Interface Pin Description.......................................14
Notes on Serial Port Operation................................................15
Outline Dimension.........................................................................16
Ordering Guide..........................................................................16
SPECIFICATIONS
DC SPECIFICATIONS
Table 1. TMIN to TMAX, AVDD1, AVDD2, DBVDD = 3.3 V, ADVDD, ACVDD, CLKVDD, DVDD = 2.5 V, IOUTFS = 20 mA, unless
otherwise noted. Specifications subject to change without notice 1Supply currents measured under the following conditions: fDAC = 200 MSPS, fOUT = 11 MHz, nominal power supply voltages Power dissipation measured under the following conditions: fDAC = 200 MSPS, fOUT = 11 MHz, nominal power supply voltages
3Power dissipation measured under the following conditions: fDAC = 600 MSPS, fOUT = 111 MHz, nominal power supply voltages
AC SPECIFICATIONS
Table 2. TMIN to TMAZ, AVDD1, AVDD2, DBVDD = 3.3 V, ADVDD, ACVDD, CLKVDD, DVDD = 2.5 V, IOUTFS = 20 mA, unless
otherwise noted. Specifications subject to change without notice. DIGITAL SPECIFICATIONS
Table 3. TMIN to TMAX, AVDD1, AVDD2, DBVDD = 3.3 V, ADVDD, ACVDD, CLKVDD, DVDD = 2.5 V , IOUTFS = 20 mA, unless
otherwise noted. Specifications subject to change without notice.
DIGITAL TIMING INFORMATION CLK
DB[15:0]
DATACLK_IN
Figure 2. Single Datarate (SDR) Mode
CLK
DB[15:0]
DATACLK_IN
DATACLK_OUT
Figure 3. Double Datarate (DDR) Mode
ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V
readily accumulate on the human body and test equipment and can discharge without
detection. Although this product features proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges.
Therefore, proper ESD precautions are recommended to avoid performance degrada-
tion or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTION
FSADJ
REFIO
RESET
CSB
SCLK/SYNC_UPD
SDO/SYNC_ALRM
DGND
DVDD
DB4–
DB4+
DBGND
CLKVDD
REXT
CLKVDD
CLKGND
CLK+
CLK–
CLKGND
DGND
DVDD
DB15+
DB15–
DB14+
DB13+
DB12+DB3–
DB3+
DB2–
DB2+
DB1–
DB1+
DB0–
DB0+
DB14–
DB13–
DB12–
DB11+
DB11–
DBVDD
SDIOSPI_D
IOUTAIOUTBAGND1AV
DD1
AGND2AV
DD2
ACGNDACV
ADGNDADV
DDRAGND1AV
DD1
AGND2AV
DD2
ACGNDACV
ADGNDADV
DBGNDDBV
DBGNDDBV
10+
DB9
DB9
DB8
DB8
DB7
DB7
DB6
DB6
DB5
DB5
DATACLK_
OUT+
DATACLK_
OUT
DATACLK_
IN+
DATACLK_
Figure 4. Pin Configuration
Table 4. Pin Function Description
