AD9712BAP-AD9712BBN-AD9713BAN-AD9713BAP-AD9713BBN-AD9713BBP Fast Delivery |IC PHOENIX CO.,LIMITED

AD9713BAP ,12-Bit, 100 MSPS D/A ConvertersFEATURES100 MSPS Update RateECL/TTL CompatibilityAD9712B/AD9713BSFDR @ 1 MHz: 70 dBcLATCH26Low Glit ..
AD9713BBN ,12-Bit, 100 MSPS D/A Convertersapplications, both devices featurelow glitch impulse of 28 pV-s and fast settling times of 27 ns.Bo ..
AD9713BBP ,12-Bit, 100 MSPS D/A ConvertersGENERAL DESCRIPTION–VOLTAGEThe AD9712B and AD9713B D/A converters are replacementsREFERENCEfor the ..
AD9713BBP ,12-Bit, 100 MSPS D/A ConvertersAPPLICATIONSTHRU DATE 12 16IOUT Signal ReconstructionArbitrary Waveform Generators1 ..
AD9713BBP ,12-Bit, 100 MSPS D/A ConvertersSPECIFICATIONS[–V = –5.2 V; +V = +5 V (AD9713B only); Reference Voltage = –1.2 V;S SR = 7.5 kV; V = ..
AD9713JN ,12-BIT, 100MSPS D/A CONVERTERSCHARACTERISTICS (-Vs = -5.2 V;+vs = +5 V(AD9713Only); CONTROL AMP IN = -1.2 V(external); R$ET =1.5 ..
ADS8323YB/250 ,Pseudo Bipolar, 16-Bit, 500kSPS CMOS Analog-to-Digital ConverterThis integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated cir ..
ADS8323YB/250G4 ,Pseudo Bipolar, 16-Bit, 500kSPS CMOS Analog-to-Digital Converter 32-TQFP -40 to 85Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
ADS8324E ,14-Bit/ High Speed/ 1.8V MicroPower Sampling ANALOG-TO-DIGITAL CONVERTERELECTRICAL CHARACTERISTICS: +V = +1.8VCC At –40°C to +85°C, V = 0.9V, –In = 0.9V, f = 50kHz, and f ..
ADS8324E/250 ,14-Bit 50 kSPS ADC Ser. Out, 1.8V OperationMAXIMUM RATINGS PIN CONFIGURATIONV .... +6VTop View MSOPCCAnalog Input ....... –0.3V to (V + 0.3V)C ..
ADS8324E/250G4 ,14-Bit 50 kSPS ADC Ser. Out, 1.8V Operation 8-VSSOP -40 to 85TYPICAL CHARACTERISTICSAt T = +25°C, V = 1.8V, V = 0.9V, f = 50kHz, f = 24 • f , unless otherwise s ..
ADS8324E/2K5 ,14-Bit 50 kSPS ADC Ser. Out, 1.8V OperationELECTRICAL CHARACTERISTICS: +V = +1.8VCC At –40°C to +85°C, V = 0.9V, –In = 0.9V, f = 50kHz, and f ..

AD9712BAP-AD9712BBN-AD9713BAN-AD9713BAP-AD9713BBN-AD9713BBP
12-Bit, 100 MSPS D/A Converters
FUNCTIONAL BLOCK DIAGRAM
REV.B12-Bit, 100 MSPS
D/A Converters
FEATURES
100 MSPS Update Rate
ECL/TTL Compatibility
SFDR @ 1 MHz: 70 dBc
Low Glitch Impulse: 28 pV-s
Fast Settling: 27 ns
Low Power: 725 mW
1/2 LSB DNL (B Grade)
40 MHz Multiplying Bandwidth
APPLICATIONS
ATE
Signal Reconstruction
Arbitrary Waveform Generators
Digital Synthesizers
Signal Generators
GENERAL DESCRIPTION
The AD9712B and AD9713B D/A converters are replacements
for the AD9712 and AD9713 units which offer improved ac and
dc performance. Like their predecessors, they are 12-bit, high
speed digital-to-analog converters fabricated in an advanced
oxide isolated bipolar process. The AD9712B is an ECL-
compatible device featuring update rates of 100 MSPS mini-
mum; the TTL-compatible AD9713B will update at 80 MSPS
minimum.
Designed for direct digital synthesis, waveform reconstruction,
and high resolution imaging applications, both devices feature
low glitch impulse of 28 pV-s and fast settling times of 27 ns.
Both units are characterized for dynamic performance and have
excellent harmonic suppression.
The AD9712B and AD9713B are available in 28-pin plastic
DIPs and PLCCs, with an operating temperature range of
–25°C to +85°C. Both are also available for extended tempera-
ture ranges of –55°C to +125°C in cerdips and 28-pin LCC
packages.
AD9712B/AD9713B–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AC LINEARITY
[–VS = –5.2 V; +VS = +5 V (AD9713B only); Reference Voltage = –1.2 V;
RSET = 7.5 kV; VOUT = 0 V (virtual ground); unless otherwise noted]
NOTESMeasured as error in ratio of full-scale current to current through RSET (160 μA nominal); ratio is nominally 128.Full-scale variations among devices are higher when driving REFERENCE INPUT directly.Frequency at which the gain is flat ±0.5 dB; RL = 50 Ω; 50% modulation at midscale.Based on IFS = 128 (VREF/RSET) when using internal amplifier.Data registered into DAC accurately at this rate; does not imply settling to 12-bit accuracy.Measured as voltage settling at midscale transition to ±0.024%, RL = 50 Ω.Measured as the time between the 50% point of the falling edge of LATCH ENABLE and the point where the output signal has left a 1 LSB error band
around its previous value.Peak glitch impulse is measured as the largest area under a single positive or negative transient.Measured with RL = 50 Ω and DAC operating in latched mode.Data must remain stable for specified time prior to falling edge of LATCH ENABLE signal.Data must remain stable for specified time after rising edge of LATCH ENABLE signal.SFDR is defined as the difference in signal energy between the fundamental and worst case spurious frequencies in the output spectrum window, which is
centered at the fundamental frequency and covers the indicated span.Supply voltages should remain stable within ±5% for normal operation.108 mA typ on Digital –VS, 37 mA typ on Analog –VS.Measured at ±5% of +VS (AD9713B only) and –VS (AD9712B or AD9713B) using external reference.
Specifications subject to change without notice.
ORDERING GUIDE
EXPLANATION OF TEST LEVELS
Test Level–100% production tested.–100% production tested at +25°C, and sample tested at
specified temperatures.
III–Sample tested only.–Parameter is guaranteed by design and characterization
testing.–Parameter is a typical value only.–All devices are 100% tested at +25°C. 100% production
tested at temperature extremes for extended tempera-
ABSOLUTE MAXIMUM RATINGS1
Positive Supply Voltage (+VS) (AD9713B Only) . . . . . . .+6 V
Negative Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . . .–7 V
Analog-to-Digital Ground Voltage Differential . . . . . . . .0.5 V
Digital Input Voltages (D1–D12, LATCH ENABLE)
AD9712B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V to –VS
AD9713B . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +VS
Internal Reference Output Current . . . . . . . . . . . . . . . .500 μA
Control Amplifier Input Voltage Range . . . . . . . . .0 V to –4 V
Control Amplifier Output Current . . . . . . . . . . . . . . .±2.5 mA
Reference Input Voltage Range (VREF) . . . . . . . . . . .0 V to –VS
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . . .30 mA
Operating Temperature Range
AD9712B/AD9713BAN/AP/BN/BP . . . . . . .–25°C to +85°C
AD9712B/AD9713BSE/SQ/TE/TQ . . . . . .–55°C to +125°C
Maximum Junction Temperature2
AD9712B/AD9713BAN/AP/BN/BP . . . . . . . . . . . . .+150°C
AD9712B/AD9713BSE/SQ/TE/TQ . . . . . . . . . . . . .+175°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . .+300°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
NOTESAbsolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.Typical thermal impedances with parts soldered in place: 28-pin plastic DIP:
θJA = 37°C/W, θJC = 10°C/W; 28-pin PLCC: θJA = 44°C/W, θJC = 14°C/W;
Cerdip: θJA = 32°C/W, θJC = 10°C/W; LCC: θJA = 41°C/W, θJC = 13°C/W. No air
flow.
AD9712B/AD9713B
AD9712B/AD9713B
PIN DESCRIPTIONS
PIN CONFIGURATIONS
PLCC/LCC
ANALOG –VS
RSET
DIGITAL +VS
REFERENCE
GROUND
DIGITAL –VS
REFERENCE
OUT
CONTROL
AMP IN
D (MSB)
DIGITAL GROUND
D11
D10
OUT
LATCH ENABLE
D (LSB)12
OUT
DIP
D11
D10
D12 (LSB)2
DIGITAL –VS
D1 (MSB0)
DIGITAL GROUND
LATCH ENABLE
RSET
REFERENCE GROUND
REFERENCE OUT
CONTROL AMP IN
REFERENCE IN
CONTROL AMP OUT
ANALOG –VS
DIGITAL +VS
DIGITAL –VS
DIE LAYOUT AND METALIZATION INFORMATION
Die Dimensions . . . . . . . . . . . . . . . . .220 × 196 × 15 (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Nitride
THEORY AND APPLICATIONS
The AD9712B and AD9713B high speed digital-to-analog
converters utilize Most Significant Bit (MSB) decoding and
segmentation techniques to reduce glitch impulse and main-
tain 12-bit linearity without trimming.
As shown in the functional block diagram, the design is based
on four main subsections: the Decoder/Driver circuits, the
Transparent Latches, the Switch Network, and the Control Am-
plifier. An internal bandgap reference is also included to allow
operation with a minimum of external components.
Digital Inputs/Timing
The AD9712B employs single-ended ECL-compatible inputs
for data inputs D1–D12 and LATCH ENABLE. The internal
ECL midpoint reference is designed to match 10K ECL device
thresholds. On the AD9713B, a TTL translator is added at each
input; with this exception, the AD9712B and AD9713B are
identical.
In the Decoder/Driver section, the four MSBs (D1–D4) are
decoded to 15 “thermometer code” lines. An equalizing delay is
included for the eight Least Significant Bits (LSBs) and
LATCH ENABLE. This delay minimizes data skew, and data
setup and hold times at the latch inputs; this is important when
operating the latches in the transparent mode. Without the
delay, skew caused by the decoding circuits would degrade
glitch impulse.
The latches operate in their transparent mode when LATCH
ENABLE (Pin 26) is at logic level “0.” The latches should be
used to synchronize data to the current switches by applying a
narrow LATCH ENABLE pulse with proper data setup and
hold times as shown in the Timing Diagram. An external latch
at each data input, clocked out of phase with the Latch Enable,
operates the AD9712B/AD9713B in a master slave (edge-
triggered) mode. This is the optimum way to operate the DAC
because data is always stable at the DAC input. An external
latch eases timing constraints when using the converter.
Although the AD9712B/AD9713B chip is designed to provide
isolation from digital inputs to the outputs, some coupling of
digital transitions is inevitable, especially with TTL or CMOS
inputs applied to the AD9713B. Digital feedthrough can be re-
duced by forming a low-pass filter using a (200 Ω) series resistor
in series with the capacitance of each digital input; this rolls off
the slew rate of the digital inputs.
References
As shown in the functional block diagram, the internal bandgap
reference, control amplifier, and reference input are pinned out
for maximum user flexibility when setting the reference.
When using the internal reference, REFERENCE OUT (Pin 20)
should be connected to CONTROL AMP IN (Pin 19). CON-
TROL AMP OUT (Pin 18) should be connected to REFER-
ENCE IN (Pin 17) through a 20 Ω resistor. A 0.1 μF ceramic
capacitor from Pin 17 to –VS (Pin 15) improves settling by
decoupling switching noise from the current sink base line. A
reference current cell provides feedback to the control amp by
sinking current through RSET (Pin 24).
tLPW– LATCH PULSE WIDTHH– INPUT HOLD TIMEST– OUTPUT SETTLING TIME

OUTPUT
ERROR
ERROR
BAND
tPD
LATCH
ENABLE
tPD
DATA INPUTS
OUTPUT
LATCH ENABLE
AD9712B/AD9713B
The REFERENCE IN pin can also be driven directly for wider
bandwidth multiplying operation. The analog signal for this
mode of operation must have a signal swing in the range of
–3.75 V to –4.25 V. This can be implemented by capacitively
coupling into REFERENCE IN a signal with a dc bias of –3.75 V
to –4.25 V, as shown in Figure 3; or by driving REFERENCE
IN with a low impedance op amp whose signal swing is limited
to the stated range.
Outputs
As indicated earlier, D1–D4 (four MSBs) are decoded and drive
15 discrete current sinks. D5 and D6 are binarily weighted; and
D7–D12 are applied to the R-2R network. This segmented archi-
tecture reduces frequency domain errors due to glitch impulse.
–VS
Figure 3.Wideband Multiplying Circuit
The Switch Network provides complementary current outputs
IOUT and IOUT. These current outputs are based on statistical
current source matching which provides 12-bit linearity without
trim. Current is steered to either IOUT or IOUT in proportion to
the digital input code. The sum of the two currents is always
equal to the full-scale output current minus one LSB.
The current output can be converted to a voltage by resistive
loading as shown in Figure 4. Both IOUT and IOUT should be
loaded equally for best overall performance. The voltage which
is developed is the product of the output current and the value
of the load resistor.
Full-scale output current is determined by CONTROL AMP
IN and RSET according to the equation:
IOUT (FS) = (CONTROL AMP IN/RSET) × 128
The internal reference is nominally –1.18 V with a tolerance of
±3.5% and typical drift over temperature of 50 ppm/°C. If
greater accuracy or better temperature stability is required, an
external reference can be utilized. The AD589 reference shown
in Figure 1 features ±10 ppm/°C drift over temperatures from
0°C to +70°C.
AD589–11k
–VS
Figure 1.Use of AD589 as External Reference
Two modes of multiplying operation are possible with the
AD9712B/AD9713B. Signals with small signal bandwidths up
to 300 kHz and input swings of 100 mV, or dc signals from
–0.6 V to –1.2 V can be applied to the CONTROL AMP input
as shown in Figure 2. Because the control amplifier is internally
compensated, the 0.1 μF capacitor at Pin 17 can be reduced to
0.01 μF to maximize the multiplying bandwidth. However, it
should be noted that settling time for changes to the digital in-
puts will be degraded.
RSET
–0.6V TO –1.2V
300 kHz MAX
Figure 2.Low Frequency Multiplying Circuit

Partno	Mfg	Dc	Qty	Available	Descript
AD9712BAP	AD	N/a	55	avai	12-Bit, 100 MSPS D/A Converters
AD9712BBN	AD	N/a	120	avai	12-Bit, 100 MSPS D/A Converters
AD9713BAN	AD	N/a	114	avai	EVALUATION BOARD
AD9713BAP		N/a	7949	avai	12-Bit, 100 MSPS D/A Converters
AD9713BBN	AD	N/a	44	avai	12-Bit, 100 MSPS D/A Converters
AD9713BBP	AD ?	N/a	294	avai	12-Bit, 100 MSPS D/A Converters
AD9713BBP	AD	N/a	72	avai	12-Bit, 100 MSPS D/A Converters
AD9713BBP	ADI	N/a	4	avai	12-Bit, 100 MSPS D/A Converters