AD9709AST Fast Delivery |IC PHOENIX CO.,LIMITED

AD9709AST ,8-Bit, 125 MSPS Dual TxDAC D/A ConverterSPECIFICATIONS (T to T , AVDD = 5 V, DVDD = 5 V, I = 20 mA, unless otherwise noted)MIN MAX OUTFSPar ..
AD9712BAP ,12-Bit, 100 MSPS D/A ConvertersSPECIFICATIONS[–V = –5.2 V; +V = +5 V (AD9713B only); Reference Voltage = –1.2 V;S SR = 7.5 kV; V = ..
AD9712BBN ,12-Bit, 100 MSPS D/A Converters12-Bit, 100 MSPSaD/A ConvertersAD9712B/AD9713BFUNCTIONAL BLOCK DIAGRAM
AD9713BAN ,EVALUATION BOARDCHARACTERISTICSSET OUTAD9712B/AD9713B AD9712B/AD9713B AD9712B/AD9713B AD9712B/AD9713BTest AN/AP BN ..
AD9713BAP ,12-Bit, 100 MSPS D/A ConvertersFEATURES100 MSPS Update RateECL/TTL CompatibilityAD9712B/AD9713BSFDR @ 1 MHz: 70 dBcLATCH26Low Glit ..
AD9713BBN ,12-Bit, 100 MSPS D/A Convertersapplications, both devices featurelow glitch impulse of 28 pV-s and fast settling times of 27 ns.Bo ..
ADS8322Y/250 ,Unipolar, 16-Bit, 500kSPS CMOS Analog-to-Digital ConverterThis integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated cir ..
ADS8322YB ,Brown Corporation - 16-Bit, 500kHz, MicroPower Sampling ANALOG-TO-DIGITAL CONVERTER
ADS8322YB/250 ,Unipolar, 16-Bit, 500kSPS CMOS Analog-to-Digital ConverterMAXIMUM RATINGSOver operating free-air temperature range (unless otherwise noted).ADS8322 UNIT+IN t ..
ADS8323Y , 16-Bit, 500kSPS, microPower Sampling ANALOG-TO-DIGITAL CONVERTER
ADS8323Y , 16-Bit, 500kSPS, microPower Sampling ANALOG-TO-DIGITAL CONVERTER
ADS8323Y/250 ,Pseudo Bipolar, 16-Bit, 500kSPS CMOS Analog-to-Digital ConverterMAXIMUM RATINGSOver operating free-air temperature range (unless otherwise noted).ADS8323 UNITSuppl ..

AD9709AST
8-Bit, 125 MSPS Dual TxDAC D/A Converter
REV. 0
8-Bit, 125MSPS
Dual TxDAC+® D/A Converter
PRODUCT DESCRIPTION
The AD9709 is a dual-port, high-speed, two-channel, 8-bit
CMOS DAC. It integrates two high-quality 8-bit TxDAC+
cores, a voltage reference, and digital interface circuitry into a
small 48-lead LQFP package. The AD9709 offers exceptional
ac and dc performance while supporting update rates up to
125MSPS.
The AD9709 has been optimized for processing I and Q data in
communications applications. The digital interface consists of
two double-buffered latches as well as control logic. Separate
write inputs allow data to be written to the two DAC ports
independent of one another. Separate clocks control the update
rate of the DACs.
A mode control pin allows the AD9709 to interface to two sep-
arate data ports, or to a single interleaved high-speed data port.
In interleaving mode, the input data stream is demuxed into
its original I and Q data and then latched. The I and Q data
is then converted by the two DACs and updated at half the
input data rate.
The GAINCTRL pin allows two modes for setting the full-scale
current (IOUTFS) of the two DACs. IOUTFS for each DAC can be
set independently using two external resistors, or IOUTFS for
both DACs can be set using a single external resistor.
The DACs utilize a segmented current source architecture
combined with a proprietary switching technique to reduce
glitch energy and to maximize dynamic accuracy. Each DAC
provides differential current output thus supporting single-ended
or differential applications. Both DACs can be simultaneously
updated and provide a nominal full-scale current of 20mA.
The full-scale currents between each DAC are matched to
within 0.1%.
The AD9709 is manufactured on an advanced low-cost CMOS
process. It operates from a single supply of 3.0V to 5.0V and
consumes 380 mW of power.
PRODUCT HIGHLIGHTSThe AD9709 is a member of a pin-compatible family of dual
TxDACs providing 8-, 10-, 12-, and 14-bit resolution.Dual 8-Bit, 125 MSPS DACs: A pair of high-performance
DACs optimized for low-distortion performance provide for
flexible transmission of I and Q information.Matching: Gain matching is typically 0.1% of full-scale, and
offset error is better than 0.02%.Low Power: Complete CMOS Dual DAC function operates
on 380 mW from a 3.0V to 5.0V single supply. The DAC
full-scale current can be reduced for lower power operation,
and a sleep mode is provided for low-power idle periods.On-Chip Voltage Reference: The AD9709 includes a 1.20V
temperature-compensated bandgap voltage reference.Dual 8-Bit Inputs: The AD9709 features a flexible dual-port
interface allowing dual or interleaved input data.
FEATURES
8-Bit Dual Transmit DAC
125 MSPS Update Rate
Excellent SFDR to Nyquist @ 5 MHz Output = 66 dBc
Excellent Gain and Offset Matching: 0.1%
Fully Independent or Single Resistor Gain Control
Dual Port or Interleaved Data
On-Chip 1.2V Reference
Single 5V or 3V Supply Operation
Power Dissipation: 380mW @ 5V
Power-Down Mode: 50 mW @ 5V
48-Lead LQFP
APPLICATIONS
Communications
Basestations
Digital Synthesis
Quadrature Modulation
3D Ultrasound
FUNCTIONAL BLOCK DIAGRAM
TxDAC+ is a registered trademark of Analog Devices, Inc.
*Patent pending.
AD9709–SPECIFICATIONS
DC SPECIFICATIONS
NOTESMeasured at IOUTA, driving a virtual ground.Nominal full-scale current, IOUTFS, is 32 times the IREF current.An external buffer ampliﬁer with input bias current <100 nA should be used to drive any external load.Measured at fCLOCK = 25 MSPS and fOUT = 1.0 MHz.Measured at fCLOCK = 100 MSPS and fOUT = 1 MHz.Measured as unbuffered voltage output with IOUTFS = 20 mA and 50 Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz.±10% power supply variation.
Speciﬁcations subject to change without notice.
(TMIN to TMAX, AVDD = 5V, DVDD = 5V, IOUTFS = 20 mA, unless otherwise noted)
AD9709
DYNAMIC SPECIFICATIONS
AC LINEARITY
NOTESMeasured single-ended into 50Ω load.
Speciﬁcations subject to change without notice.
(TMIN to TMAX, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA, Differential Transformer-Coupled Output,� Doubly Terminated, unless otherwise noted)
AD9709–SPECIFICATIONS
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9709 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
DIGITAL SPECIFICATIONS
Speciﬁcations subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Figure 1.Timing Diagram for Dual and Interleaved Modes
(TMIN to TMAX, AVDD = 5V, DVDD = 5V, IOUTFS = 20 mA, unless otherwise noted)
ORDERING GUIDE
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP
θJA = 91°C/WSee Dynamic and Digital sections for timing specifications.
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
AD9709
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is deﬁned as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full-scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full-scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected when
all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
Figure 2.Basic AC Characterization Test Setup for AD9709, Testing Port 1 in Dual Port Mode, Using Independent
GAINCTRL Resistors on FSADJ1 and FSADJ2
Temperature Drift
Temperature drift is speciﬁed as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum speciﬁed
voltages.
Settling Time
The time required for the output to reach and remain within a
speciﬁed error band about its ﬁnal value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantiﬁed by a glitch impulse. It is
speciﬁed as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the speciﬁed bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the ﬁrst six harmonic
components to the rms value of the measured input signal. It
is expressed as a percentage or in decibels (dB).
Typical Characterization Curves
(AVDD = 5V, DVDD = 3.3V, IOUTFS = 20 mA, 50� Doubly Terminated Load, Differential Output, TA = 25�C, SFDR up to Nyquist, unless
otherwise noted)
SFDR
dBc10100
fOUT – MHz
0.1
Figure 3.SFDR vs. fOUT @ 0 dBFS
fOUT – MHz
SFDR
dBc2510152035
Figure 6. SFDR vs. fOUT @ 65 MSPS
AOUT – dBFS
SFDR
dBc
–22–13–10–4–1
Figure 9. Single-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/11
Figure 4.SFDR vs. fOUT @ 5 MSPS
fOUT – MHz
SFDR
dBc0105020304070
Figure 7.SFDR vs. fOUT @ 125 MSPS
AOUT – dBFS
SFDR
dBc–20–15–5
–25
Figure 10.Single-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/5
fOUT – MHz
SFDR
dBc21246810
Figure 5.SFDR vs. fOUT @ 25 MSPS
Figure 8.SFDR vs. fOUT and IOUTFS
@ 65 MSPS and 0 dBFS
Figure 11.Dual-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/7
AD9709
fCLK – MSPS
SINAD
dBc140406080100120
Figure 12.SINAD vs. fCLOCK and IOUTFS
@ fOUT = 5 MHz and 0 dBFS
TEMPERATURE – �C
SFDR
dBc
–30–107050104590–50
Figure 15.SFDR vs. Temperature @
fCLK = 125 MSPS, 0 dBFS
Figure 18.Dual-Tone SFDR @
fCLK = 125 MSPS
Figure 14.Typical DNL
Figure 17.Single-Tone SFDR @
fCLK = 125 MSPS
Figure 13.Typical INL
Figure 16.Gain and Offset Error vs.
Temperature @ fCLK = 125 MSPS
Figure 19.Four-Tone SFDR @
fCLK = 125 MSPS
FUNCTIONAL DESCRIPTION
Figure 20 shows a simpliﬁed block diagram of the AD9709.
The AD9709 consists of two DACs, each one with its own
independent digital control logic and full-scale output current
control. Each DAC contains a PMOS current source array
capable of providing up to 20 mA of full-scale current (IOUTFS).
The array is divided into 31 equal currents that make up the ﬁve
most signiﬁcant bits (MSBs). The three lower bits consist of
seven equal current sources whose value is 1/8th of an MSB
current source. Implementing the lower bits with current sources,
instead of an R-2R ladder, enhances the dynamic performance
for multitone or low-amplitude signals and helps maintain the
DACs high-output impedance (i.e., >100kΩ).
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS differ-
ential current switches. The switches are based on a new archi-
tecture that drastically improves distortion performance. This
new switch architecture reduces various timing errors and pro-
vides matching complementary drive signals to the inputs of the
differential current switches.
The analog and digital sections of the AD9709 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 3V to 5.5V range. The digital section,
which is capable of operating up to a 125 MSPS clock rate,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current sources,
the associated differential switches, a 1.20V bandgap voltage
reference and two reference control ampliﬁers.
The full-scale output current of each DAC is regulated by sepa-
rate reference control ampliﬁers and can be set from 2 mA tomA via an external resistor, RSET, connected to the Full-Scale
Adjust (FSADJ) pin. The external resistor, in combination with
both the reference control ampliﬁer and voltage reference VREFIO,
sets the reference current IREF, which is replicated to the seg-
mented current sources with the proper scaling factor. The full-
scale current, IOUTFS, is 32 × IREF.
REFERENCE OPERATION
The AD9709 contains an internal 1.20V bandgap reference.
This can be easily overridden by an external reference with no
effect on performance. REFIO serves as either an input or output
depending on whether the internal or an external reference is
used. To use the internal reference, simply decouple the REFIO
pin to ACOM with a 0.1µF capacitor. The internal reference
voltage will be present at REFIO. If the voltage at REFIO is to
be used elsewhere in the circuit, an external buffer ampliﬁer
with an input bias current of less than 100nA should be used.
An example of the use of the internal reference is shown in
Figure 21.
An external reference can be applied to REFIO as shown in
Figure 22. The external reference may provide either a ﬁxed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1µF
compensation capacitor is not required since the internal refer-
ence is overridden, and the relatively high-input impedance of
REFIO minimizes any loading of the external reference.
GAINCTRL MODE
The AD9709 allows the gain of each channel to be set indepen-
dently by connecting one RSET resistor to FSADJ1 and another
RSET resistor to FSADJ2. To add flexibility and reduce system
cost, a single RSET resistor can be used to set the gain of both
channels simultaneously.
When GAINCTRL is low (i.e., connected to AGND), the inde-
pendent channel gain control mode using two resistors is enabled.
In this mode, individual RSET resistors should be connected to
FSADJ1 and FSADJ2. When GAINCTRL is high (i.e., connected
to AVDD), the master/slave channel gain control mode using one
resistor is enabled. In this mode, a single RSET resistor is con-
nected to FSADJ1 and the resistor on FSADJ2 can be removed.
DIGITAL DATA INPUTS
IREF1
IREF2
DB0-DB7GAINCTRLWRT1/
IQWRT
RSET2
2k�
MODE
CLK2/
CLK1/
RSET1
2k�
0.1�F
FSADJ2
DB0-DB7WRT2/
IQSEL
RL1A
50�
Figure 20.Simpliﬁed Block Diagram
AD9709
REFERENCE CONTROL AMPLIFIER
Both of the DACs in the AD9709 contain a control ampliﬁer
that is used to regulate the full-scale output current, IOUTFS. The
control ampliﬁer is conﬁgured as a V-I converter as shown in
Figure 21, so that its current output, IREF, is determined by the
ratio of the VREFIO and an external resistor, RSET, as stated in
Equation 4. IREF is copied to the segmented current sources with
the proper scale factor to set IOUTFS as stated in Equation 3.
Figure 21.Internal Reference Conﬁguration
Figure 22.External Reference Conﬁguration
The control ampliﬁer allows a wide (10:1) adjustment span of
IOUTFS from 2mA to 20 mA by setting IREF between 62.5µA
and 625µA. The wide adjustment range of IOUTFS provides
several beneﬁts. The ﬁrst relates directly to the power dissipa-
tion of the AD9709, which is proportional to IOUTFS (refer to the
Power Dissipation section). The second relates to the 20dB
adjustment, which is useful for system gain control purposes.
The small signal bandwidth of the reference control ampliﬁer
is approximately 500kHz and can be used for low frequency,
small signal multiplying applications.
DAC TRANSFER FUNCTION
Both DACs in the AD9709 provide complementary current out-
puts, IOUTA and IOUTB. IOUTA will provide a near full-scale current
output, IOUTFS, when all bits are high (i.e., DAC CODE = 1023)
while IOUTB, the complementary output, provides no current. The
current output appearing at IOUTA and IOUTB is a function of both
the input code and IOUTFS and can be expressed as:
IOUTA = (DAC CODE/256) × IOUTFS(1)
IOUTB = (255 – DAC CODE)/256 × IOUTFS(2)
where DAC CODE = 0 to 255 (i.e., Decimal Representation).
As mentioned previously, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage, VREFIO
and external resistor RSET. It can be expressed as:IOUTFS = 32 × IREF(3)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, that are tied to analog common, ACOM. Note,
RLOAD may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated 50Ω
or 75Ω cable. The single-ended voltage output appearing at the
IOUTA and IOUTB nodes is simply :
VOUTA = IOUTA × RLOAD(5)
VOUTB = IOUTB × RLOAD(6)
Note the full-scale value of VOUTA and VOUTB should not exceed
the speciﬁed output compliance range to maintain speciﬁed
distortion and linearity performance.
VDIFF = (IOUTA – IOUTB) × RLOAD(7)
Substituting the values of IOUTA, IOUTB and IREF; VDIFF can be
expressed as:
VDIFF = {(2 × DAC CODE – 255)/256} ×
(32 × RLOAD/RSET) × VREFIO(8)
These last two equations highlight some of the advantages of
operating the AD9709 differentially. First, the differential
operation will help cancel common-mode error sources associ-
ated with IOUTA and IOUTB such as noise, distortion and dc
offsets. Second, the differential code dependent current and
subsequent voltage, VDIFF, is twice the value of the single-ended
voltage output (i.e., VOUTA or VOUTB), thus providing twice the
signal power to the load.
Note, the gain drift temperature performance for a single-ended
(VOUTA and VOUTB) or differential output (VDIFF) of the AD9709
can be enhanced by selecting temperature tracking resistors for
RLOAD and RSET due to their ratiometric relationship as shown
in Equation 8.
ANALOG OUTPUTS
The complementary current outputs in each DAC, IOUTA and
IOUTB, may be conﬁgured for single-ended or differential opera-
tion. IOUTA and IOUTB can be converted into complementary
single-ended voltage outputs, VOUTA and VOUTB, via a load
resistor, RLOAD, as described in the DAC Transfer Function
section by Equations 5 through 8. The differential voltage, VDIFF,
existing between VOUTA and VOUTB can also be converted to a
single-ended voltage via a transformer or differential ampliﬁer
conﬁguration. The ac performance of the AD9709 is optimum
and speciﬁed using a differential transformer coupled output in
which the voltage swing at IOUTA and IOUTB is limited to ±0.5V.
If a single-ended unipolar output is desirable, IOUTA should be
selected.
The distortion and noise performance of the AD9709 can be
enhanced when it is conﬁgured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can be
signiﬁcantly reduced by the common-mode rejection of a
transformer or differential ampliﬁer. These common-mode error
sources include even-order distortion products and noise. The
enhancement in distortion performance becomes more signiﬁ-
cant as the frequency content of the reconstructed waveform
increases. This is due to the ﬁrst order cancellation of various
Performing a differential-to-single-ended conversion via a trans-
former also provides the ability to deliver twice the reconstructed
signal power to the load (i.e., assuming no source termination).
Since the output currents of IOUTA and IOUTB are complementary,
they become additive when processed differentially. A prop-
erly selected transformer will allow the AD9709 to provide the
required power and voltage levels to different loads.
The output impedance of IOUTA and IOUTB is determined by the
equivalent parallel combination of the PMOS switches associ-
ated with the current sources and is typically 100kΩ in parallel
with 5 pF. It is also slightly dependent on the output voltage
(i.e., VOUTA and VOUTB) due to the nature of a PMOS device.
As a result, maintaining IOUTA and/or IOUTB at a virtual ground
via an I-V op amp conﬁguration will result in the optimum dc
linearity. Note the INL/DNL speciﬁcations for the AD9709 are
measured with IOUTA maintained at a virtual ground via an op amp.
IOUTA and IOUTB also have a negative and positive voltage com-
pliance range that must be adhered to in order to achieve opti-
mum performance. The negative output compliance range of
–1.0V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a break-
down of the output stage and affect the reliability of the AD9709.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from its
nominal 1.25V for an IOUTFS = 20 mA to 1.00V for an IOUTFS =mA. The optimum distortion performance for a single-ended
or differential output is achieved when the maximum full-scale
signal at IOUTA and IOUTB does not exceed 0.5V. Applications
requiring the AD9709’s output (i.e., VOUTA and/or VOUTB) to
extend its output compliance range should size RLOAD accord-
ingly. Operation beyond this compliance range will adversely
affect the AD9709’s linearity performance and subsequently
degrade its distortion performance.
DIGITAL INPUTS
The AD9709’s digital inputs consists of two independent chan-
nels. For the dual port mode, each DAC has its own dedicated
8-bit data port, WRT line and CLK line. In the interleaved
timing mode, the function of the digital control pins changes
as described below under the Interleaved Mode Timing section.
The 8-bit parallel data inputs follow straight binary coding
where DB7 is the most signiﬁcant bit (MSB) and DB0 is the
least signiﬁcant bit (LSB). IOUTA produces a full-scale output
current when all data bits are at Logic 1. IOUTB produces a
complementary output with the full-scale current split between
the two outputs as a function of the input code.
The digital interface is implemented using an edge-triggered
master slave latch. The DAC outputs are updated following
either the rising edge, or every other rising edge of the clock,
depending on whether dual or interleaved mode is being used.
The DAC outputs are designed to support a clock rate as high
as 125 MSPS. The clock can be operated at any duty cycle that
meets the speciﬁed latch pulsewidth. The setup and hold times
can also be varied within the clock cycle as long as the speciﬁed
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion perfor-
DAC TIMING
The AD9709 can operate in two timing modes, dual and inter-
leaved, which are described below. The block diagram in Figure
25 represents the latch architecture in the interleaved timing mode.
DUAL PORT MODE TIMING
When the mode pin is at Logic 1, the AD9709 operates in dual
port mode. The AD9709 functions as two distinct DACs. Each
DAC has its own completely independent digital input and con-
trol lines.
The AD9709 features a double buffered data path. Data enters
the device through the channel input latches. This data is then
transferred to the DAC latch in each signal path. Once the data
is loaded into the DAC latch, the analog output will settle to its
new value.
For general consideration, the WRT lines control the channel
input latches and the CLK lines control the DAC latches. Both
sets of latches are updated on the rising edge of their respective
control signals.
The rising edge of CLK should occur before or simultaneously
with the rising edge of WRT. Should the rising edge of CLK
occur after the rising edge of WRT, a 2ns minimum delay should
be maintained from rising edge of WRT to rising edge of CLK.
Figure 23.Dual Mode Timing
Timing speciﬁcations for dual port mode are given in Figures 23
and 24.
Figure 24.Dual Mode Timing
INTERLEAVED MODE TIMING
When the mode pin is at Logic 0, the AD9709 operates in inter-
leaved mode. WRT1 now functions as IQWRT and CLK1
functions as IQCLK. WRT2 functions as IQSEL and CLK2
functions as IQRESET.
Data enters the device on the rising edge of IQWRT. The logic
level of IQSEL will steer the data to either Channel Latch 1
AD9709
When IQRESET is high, IQCLK is disabled. When IQRESET
goes low, the following rising edge on IQCLK will update both
DAC latches with the data present at their inputs. In the inter-
leaved mode IQCLK is divided by 2 internally. Following this
first rising edge, the DAC latches will only be updated on every
other rising edge of IQCLK. In this way, IQRESET can be used
to synchronize the routing of the data to the DACs.
As with the dual port mode, IQCLK should occur before or
simultaneously with IQWRT.
Figure 25.Latch Structure in Interleaved Mode
Timing speciﬁcations for interleaved mode are given in Figures
26 and 27.
Figure 26.Interleaved Mode Timing
Figure 27.Interleaved Mode Timing
The digital inputs are CMOS-compatible with logic thresholds,
VTHRESHOLD, set to approximately half the digital positive supply
(DVDD) or
VTHRESHOLD = DVDD/2 (±20%)
The internal digital circuitry of the AD9709 is capable of oper-
ating over a digital supply range of 3V to 5.5V. As a result, the
digital inputs can also accommodate TTL levels when DVDD is
set to accommodate the maximum high-level voltage of the
TTL drivers VOH(MAX). A DVDD of 3V to 3.3V will typically
ensure proper compatibility with most TTL logic families. Fig-
ure 28 shows the equivalent digital input circuit for the data and
clock inputs. The sleep mode input is similar with the exception
that it contains an active pull-down circuit, thus ensuring that
the AD9709 remains enabled if this input is left disconnected.
Since the AD9709 is capable of being clocked up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. Operating the AD9709
with reduced logic swings and a corresponding digital supply
(DVDD) will result in the lowest data feedthrough and on-chip
digital noise. The drivers of the digital data interface circuitry
should be speciﬁed to meet the minimum setup and hold times
of the AD9709 as well as its required min/max input logic level
thresholds.
Digital signal paths should be kept short and run lengths matched
to avoid propagation delay mismatch. The insertion of a low-
value resistor network (i.e., 20 Ω to 100 Ω) between the AD9709
digital inputs and driver outputs may be helpful in reducing any
overshooting and ringing at the digital inputs that contribute to
digital feedthrough. For longer board traces and high-data update
rates, stripline techniques with proper impedance and termina-
tion resistors should be considered to maintain “clean” digital
inputs.
The external clock driver circuitry should provide the AD9709
with a low-jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a reconstructed
waveform. Thus, the clock input should be driven by the fastest
logic family suitable for the application.
Figure 28.Equivalent Digital Input
Note that the clock input could also be driven via a sine wave,
which is centered around the digital threshold (i.e., DVDD/2)
and meets the min/max logic threshold. This will typically result
in a slight degradation in the phase noise, which becomes more
noticeable at higher sampling rates and output frequencies.
Also, at higher sampling rates, the 20% tolerance of the digital
logic threshold should be considered since it will affect the
effective clock duty cycle and, subsequently, cut into the required
Figure 29.SINAD vs. Clock Placement @ fOUT = 20 MHz
INPUT CLOCK AND DATA TIMING RELATIONSHIP
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9709 is rising edge triggered, and so
exhibits SNR sensitivity when the data transition is close to this
edge. In general, the goal when applying the AD9709 is to make
the data transition close to the falling clock edge. This becomes
more important as the sample rate increases. Figure 29 shows
the relationship of SNR to clock/data placement.
SLEEP MODE OPERATION
The AD9709 has a power down function that turns off the
output current and reduces the supply current to less than
8.5mA over the speciﬁed supply range of 3.0V to 5.5V and
temperature range. This mode can be activated by applying a
logic level 1 to the SLEEP pin. The SLEEP pin logic threshold
is equal to 0.5 × AVDD. This digital input also contains an
active pull-down circuit that ensures the AD9709 remains
enabled if this input is left disconnected. The AD9709 takes
less than 50ns to power down and approximately 5µs to
power back up.
POWER DISSIPATION
The power dissipation, PD, of the AD9709 is dependent on
several factors that include: (1) The power supply voltages
(AVDD and DVDD), (2) the full-scale current output IOUTFS,
(3) the update rate fCLOCK, (4) and the reconstructed digital
input waveform. The power dissipation is directly proportional
to the analog supply current, IAVDD, and the digital supply cur-
rent, IDVDD. IAVDD is directly proportional to IOUTFS as shown in
Figure 30 and is insensitive to fCLOCK.
Conversely, IDVDD is dependent on both the digital input wave-
form, fCLOCK, and digital supply DVDD. Figures 31 and 32
show IDVDD as a function of full-scale sine wave output ratios
(fOUT/fCLOCK) for various update rates with DVDD = 5V and
DVDD = 3V, respectively. Note how IDVDD is reduced by more
than a factor of 2 when DVDD is reduced from 5V to 3V.
APPLYING THE AD9709
the optimum dynamic performance, a differential output
conﬁguration is suggested. A differential output conﬁguration
may consist of either an RF transformer or a differential op amp
conﬁguration. The transformer conﬁguration provides the opti-
mum high-frequency performance and is recommended for any
application allowing for ac coupling. The differential op amp
conﬁguration is suitable for applications requiring dc coupling,
a bipolar output, signal gain and/or level shifting, within the
bandwidth of the chosen op amp.
Figure 30.IAVDD vs. IOUTFS
RATIO – fOUT/fCLK0.10
IDVDD
mA
0.20.30.40.5
Figure 31.IDVDD vs. Ratio @ DVDD = 5 V
AD9709
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if IOUTA and/or IOUTB is connected to an appropriately
sized load resistor, RLOAD, referred to ACOM. This conﬁguration
may be more suitable for a single-supply system requiring a dc-
coupled, ground referred output voltage. Alternatively, an
ampliﬁer could be conﬁgured as an I-V converter, thus converting
IOUTA or IOUTB into a negative unipolar voltage. This conﬁguration
provides the best dc linearity since IOUTA or IOUTB is maintained at
a virtual ground. Note that IOUTA provides slightly better perfor-
mance than IOUTB.
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-to-
single-ended signal conversion as shown in Figure 33. A
differentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral content
lies within the transformer’s passband. An RF transformer such
as the Mini-Circuits T1-1T provides excellent rejection of
common-mode distortion (i.e., even-order harmonics) and
noise over a wide frequency range. It also provides electrical
isolation and the ability to deliver twice the power to the load.
Transformers with different impedance ratios may also be used
for impedance matching purposes. Note that the transformer
provides ac coupling only.
Figure 33.Differential Output Using a Transformer
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages appearing
at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetrically
around ACOM and should be maintained with the speciﬁed
output compliance range of the AD9709. A differential resistor,
RDIFF, may be inserted in applications where the output of the
transformer is connected to the load, RLOAD, via a passive
reconstruction ﬁlter or cable. RDIFF is determined by the
transformer’s impedance ratio and provides the proper source
termination that results in a low VSWR. Note that approximately
half the signal power will be dissipated across RDIFF.
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used to perform a differential to single-
ended conversion as shown in Figure 34. The AD9709 is
conﬁgured with two equal load resistors, RLOAD, of 25 Ω. The
differential voltage developed across IOUTA and IOUTB is converted
to a single-ended signal via the differential op amp conﬁguration.
An optional capacitor can be installed across IOUTA and IOUTB,
forming a real pole in a low-pass ﬁlter. The addition of this
capacitor also enhances the op amps distortion performance by
preventing the DACs high-slewing output from overloading the
op amp’s input.
some additional signal gain. The op amp must operate off of a
dual supply since its output is approximately ±1.0V. A high-
speed ampliﬁer capable of preserving the differential performance
of the AD9709 while meeting other system level objectives (i.e.,
cost, power) should be selected. The op amp’s differential gain,
its gain setting resistor values, and full-scale output swing capa-
bilities should all be considered when optimizing this circuit.
The differential circuit shown in Figure 35 provides the necessary
level-shifting required in a single supply system. In this case,
AVDD which is the positive analog supply for both the AD9709
and the op amp is also used to level-shift the differential output
of the AD9709 to midsupply (i.e., AVDD/2). The AD8041 is a
suitable op amp for this application.
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
Figure 36 shows the AD9709 conﬁgured to provide a unipolar
output range of approximately 0V to 0.5V for a doubly termi-
nated 50Ω cable since the nominal full-scale current, IOUTFS, of
20 mA flows through the equivalent RLOAD of 25Ω. In this case,
RLOAD represents the equivalent load resistance seen by IOUTA or
IOUTB. The unused output (IOUTA or IOUTB) can be connected to
ACOM directly or via a matching RLOAD. Different values of
IOUTFS and RLOAD can be selected as long as the positive compli-
ance range is adhered to. One additional consideration in this
mode is the integral nonlinearity (INL) as discussed in the
Analog Output section of this data sheet. For optimum INL
performance, the single-ended, buffered voltage output conﬁgu-
ration is suggested.
Figure 34.DC Differential Coupling Using an Op Amp
Figure 35.Single Supply DC Differential Coupled Circuit

Partno	Mfg	Dc	Qty	Available	Descript
AD9709AST	AD	N/a	75	avai	8-Bit, 125 MSPS Dual TxDAC D/A Converter