AD9708AR-AD9708ARU Fast Delivery |IC PHOENIX CO.,LIMITED

AD9708AR ,8-Bit, 100 MSPS TxDAC D/A Converterapplications. The current outputs may beSignal Reconstructiondirectly tied to an output resistor to ..
AD9708ARU ,8-Bit, 100 MSPS TxDAC D/A ConverterSPECIFICATIONS(T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, unless otherwise noted)MIN MAX OUTFS P ..
AD9708ARZ , 8-Bit, 100 MSPS TxDAC D/A Converter
AD9709AST ,8-Bit, 125 MSPS Dual TxDAC D/A ConverterSPECIFICATIONS (T to T , AVDD = 5 V, DVDD = 5 V, I = 20 mA, unless otherwise noted)MIN MAX OUTFSPar ..
AD9712BAP ,12-Bit, 100 MSPS D/A ConvertersSPECIFICATIONS[–V = –5.2 V; +V = +5 V (AD9713B only); Reference Voltage = –1.2 V;S SR = 7.5 kV; V = ..
AD9712BBN ,12-Bit, 100 MSPS D/A Converters12-Bit, 100 MSPSaD/A ConvertersAD9712B/AD9713BFUNCTIONAL BLOCK DIAGRAM
ADS8320EB/250G4 ,16-Bit, High-Speed, 2.7V to 5V Micro Power Sampling Analog-to-Digital Converter 8-VSSOP -40 to 85Features... 18 Application and Implementation...... 162 Applications..... 18.1 Application Informat ..
ADS8321E/250 ,16-Bit, High Speed, MicroPower Sampling Analog-to-Digital ConverterMAXIMUM RATINGSELECTROSTATICV .... +6VCCDISCHARGE SENSITIVITYAnalog Input ....... –0.3V to (V + 0.3 ..
ADS8321E/250G4 ,16-Bit, High Speed, MicroPower Sampling Analog-to-Digital Converter 8-VSSOP -40 to 85SPECIFICATIONS: +V = +5VCC At –40°C to +85°C, V = +2.5V, –In = 2.5V, f = 100kHz, and f = 24 • f , u ..
ADS8321E/2K5 ,16-Bit, High Speed, MicroPower Sampling Analog-to-Digital Converterfeatures a synchronous serial (SPI/SSI* PIN-COMPATIBLE TO ADS7816 AND ADS7822 compatible) interface ..
ADS8321EB ,Brown Corporation - 16-Bit, High Speed, MicroPower Sampling ANALOG-TO-DIGITAL CONVERTER
ADS8321EB/250G4 ,16-Bit, High Speed, MicroPower Sampling Analog-to-Digital Converter 8-VSSOP -40 to 85TYPICAL PERFORMANCE CURVESAt T = +25°C, V = +5V, V = +2.5V, f = 100kHz, f = 24 • f , unless otherwi ..

AD9708AR-AD9708ARU
8-Bit, 100 MSPS TxDAC D/A Converter
REV.B
8-Bit, 100 MSPS+
TxDAC® D/A Converter
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Member of Pin-Compatible TxDAC Product Family
125 MSPS Update Rate
8-Bit Resolution
Linearity: 1/4 LSB DNL
Linearity: 1/4 LSB INL
Differential Current Outputs
SINAD @ 5 MHz Output:50 dB
Power Dissipation:175 mW @ 5V to 45mW @ 3V
Power-Down Mode:20 mW @ 5V
On-Chip 1.20 V Reference
Single +5 V or +3 V Supply Operation
Packages:28-Lead SOIC and 28-Lead TSSOP
Edge-Triggered Latches
Fast Settling: 35 ns Full-Scale Settling to 0.1%
APPLICATIONS
Communications
Signal Reconstruction
Instrumentation
PRODUCT DESCRIPTION
The AD9708 is the 8-bit resolution member of the TxDAC
series of high performance, low power CMOS digital-to-analog
converters (DACs). The TxDAC family, which consists of pin
compatible 8-, 10-, 12-, and 14-bit DACs, was specifically opti-
mized for the transmit signal path of communication systems. All
of the devices share the same interface options, small outline
package and pinout, thus providing an upward or downward
component selection path based on performance, resolution and
cost. The AD9708 offers exceptional ac and dc performance
while supporting update rates up to 125 MSPS.
The AD9708’s flexible single-supply operating range of +2.7 V
to +5.5 V and low power dissipation are well suited for portable
and low power applications. Its power dissipation can be
further reduced to 45 mW, without a significant degradation in
performance, by lowering the full-scale current output. In addi-
tion, a power-down mode reduces the standby power dissipa-
tion to approximately 20 mW.
The AD9708 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input latches
and a temperature compensated bandgap reference have been inte-
grated to provide a complete monolithic DAC solution. Flexible
supply options support +3 V and +5 V CMOS logic families.
The AD9708 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 kW output impedance.
TxDAC is a registered trademark of Analog Devices, Inc.
*Patent pending.
Differential current outputs are provided to support single-
ended or differential applications. The current outputs may be
directly tied to an output resistor to provide two complemen-
tary, single-ended voltage outputs. The output voltage compliance
range is 1.25V.
The AD9708 contains a 1.2 V on-chip reference and reference
control amplifier, which allows the full-scale output current to
be simply set by a single resistor. The AD9708 can be driven by
a variety of external reference voltages. The AD9708’s full-scale
current can be adjusted over a 2mA to 20 mA range without
any degradation in dynamic performance. Thus, the AD9708
may operate at reduced power levels or be adjusted over a 20dB
range to provide additional gain ranging capabilities.
The AD9708 is available in 28-lead SOIC and 28-lead TSSOP
packages. It is specified for operation over the industrial tem-
perature range.
PRODUCT HIGHLIGHTSThe AD9708 is a member of the TxDAC product family, which
provides an upward or downward component selection path
based on resolution (8 to 14 bits), performance and cost.Manufactured on a CMOS process, the AD9708 uses a pro-
prietary switching technique that enhances dynamic perfor-
mance well beyond 8- and 10-bit video DACs.On-chip, edge-triggered input CMOS latches readily interface
to +3V and +5 V CMOS logic families. The AD9708 can
support update rates up to 125 MSPS.A flexible single-supply operating range of +2.7V to +5.5 V
and a wide full-scale current adjustment span of 2mA tomA allows the AD9708 to operate at reduced power levels
(i.e., 45 mW) without any degradation in dynamic performance.A temperature compensated, 1.20 V bandgap reference is
included on-chip providing a complete DAC solution. An
external reference may be used.The current output(s) of the AD9708 can easily be config-
DC SPECIFICATIONS
REFERENCE INPUT
TEMPERATURE COEFFICIENTS
NOTESMeasured at IOUTA, driving a virtual ground.Nominal full-scale current, IOUTFS, is 32 · the IREF current.Use an external buffer amplifier to drive any external load.Reference bandwidth is a function of external cap at COMP1 pin.For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.Measured at fCLOCK = 50 MSPS and fOUT = 1.0 MHz.Measured as unbuffered voltage output into 50W RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz.
Specifications subject to change without notice.
(TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)
AD9708–SPECIFICATIONS
DYNAMIC SPECIFICATIONS
NOTESMeasured single ended into 50W load.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Specifications subject to change without notice.
0.1%
DB0–DB7
CLOCK
IOUTA
(TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Single-Ended Output, IOUTA, 50V Doubly
Terminated, unless otherwise noted)
AD9708
(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA unless otherwise noted)
AD9708
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature
Lead Temperature
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 mil SOICJA = 71.4°C/WJC = 23°C/W
28-Lead TSSOPJA = 97.9°C/WJC = 14.0°C/W
PIN CONFIGURATION
NC = NO CONNECT
(MSB) DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CLOCK
DVDD
DCOM
AVDD
COMP2
IOUTA
IOUTB
ACOM
COMP1
FS ADJ
REFIO
REFLO
SLEEP
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
PIN FUNCTION DESCRIPTIONS
ORDERING GUIDE
*R = Small Outline IC; RU = Thin Small Outline IC.
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio
S/N+D is the ratio of the rms value of the measured output
signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/N+D is expressed in decibels.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured output signal. It is
expressed as a percentage or in decibels (dB).
DVDD
DCOM20pF
TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50V INPUT
* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
+5V
RSET
2kV
Figure 2.Basic AC Characterization Test Setup
AD9708
Typical AC Characterization Curves
FREQUENCY – MHz
SINAD/THD – dB
0.1110010
Figure 3.SINAD/THD vs. fOUT (AVDD
and DVDD = 5.0 V)
FREQUENCY – MHz
SINAD/THD – dB
0.1110010
Figure 6.SINAD/THD vs. fOUT (AVDD
and DVDD = 3.0 V)
START: 0HzSTOP: 12.5MHz
10dB – Div
Figure 9.Single-Tone Spectral Plot
@ 25 MSPS
FREQUENCY – MHz
SINAD/THD – dB
0.1110010
Figure 4.SINAD/THD vs. fOUT (Differ-
ential Output, AVDD and DVDD = 5.0 V)
FREQUENCY – MHz
SINAD/THD – dB
0.1110010
Figure 7.SINAD/THD vs. fOUT (Differ-
ential Output, AVDD and DVDD = 3.0 V)
START: 0HzSTOP: 62.5MHz
10dB – Div
Figure 10.Single-Tone Spectral
Plot @ 125 MSPS
Figure 5.SINAD vs. IOUTFS
@ 100 MSPS
FREQUENCY – MHz
SINAD – dB
0.1101
Figure 8.SINAD vs. IOUTFS
@ 20 MSPS
Figure 11.Step Response
(AVDD = +5 V or +3 V, DVDD = +5 V or +3 V, 50V Doubly Terminated Load,
Single-Ended Output, IOUTA, IOUTFS = 20 mA, TA = +258C, unless otherwise noted)
FUNCTIONAL DESCRIPTION
Figure 12 shows a simplified block diagram of the AD9708. The
AD9708 consists of a large PMOS current source array capable of
providing up to 20mA of total current. The array is divided into
31 equal currents that make up the five most significant bits
(MSBs). The remaining 3 LSBs are also implemented with equally
weighted current sources whose sum total equals 7/8th of an
MSB current source. Implementing the upper and lower bits
with current sources helps maintain the DAC’s high output
impedance (i.e. > 100 kW). All of these current sources are
switched to one or the other of the two output nodes (i.e., IOUTA
or IOUTB) via PMOS differential current switches. The switches
are based on a new architecture that drastically improves
distortion performance.
The analog and digital sections of the AD9708 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 2.7 volt to 5.5 volt range. The digital section,
which is capable of operating up to a 125 MSPS clock rate,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V bandgap
voltage reference and a reference control amplifier.
The full-scale output current is regulated by the reference con-
trol amplifier and can be set from 2 mA to 20 mA via an exter-
nal resistor, RSET. The external resistor, in combination with
both the reference control amplifier and voltage reference
VREFIO, sets the reference current IREF, which is mirrored over to
the segmented current sources with the proper scaling factor.
The full-scale current, IOUTFS, is thirty-two times the value of IREF.
DAC TRANSFER FUNCTION
The AD9708 provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current output,
IOUTFS, when all bits are high (i.e., DAC CODE = 255), while
IOUTB, the complementary output, provides no current. The
current output appearing at IOUTA and IOUTB are a function
of both the input code and IOUTFS and can be expressed as:
IOUTA = (DAC CODE/256) · IOUTFS(1)
IOUTB = (255 – DAC CODE)/256 · IOUTFS(2)
where DAC CODE = 0 to 255 (i.e., Decimal Representation).
As previously mentioned, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage
VREFIO and external resistor RSET. It can be expressed as:
IOUTFS = 32 · IREF(3)
where
IREF = VREFIO/RSET(4)
The two current outputs will typically drive a resistive load
directly. If dc coupling is required, IOUTA and IOUTB should
be directly connected to matching resistive loads, RLOAD, which
are tied to analog common, ACOM. Note, RLOAD may repre-
sent the equivalent load resistance seen by IOUTA or IOUTB
as would be the case in a doubly terminated 50W or 75W cable.
The single-ended voltage output appearing at the IOUTA and
IOUTB nodes is simply:
VOUTA = IOUTA · RLOAD(5)
VOUTB = IOUTB · RLOAD(6)
Note the full-scale value of VOUTA and VOUTB should not exceed
the specified output compliance range to maintain specified
distortion and linearity performance.
The differential voltage, VDIFF, appearing across IOUTA and
IOUTB is:
VDIFF = (IOUTA – IOUTB) · RLOAD(7)
Substituting the values of IOUTA, IOUTB, and IREF; VDIFF can be
expressed as:
VDIFF = {(2 DAC CODE – 255)/256}/ · (32 RLOAD/RSET) VREFIO(8)
VOLTAGE REFERENCE AND CONTROL AMPLIFIER
The AD9708 contains an internal 1.20 V bandgap reference
that can be easily disabled and overridden by an external refer-
ence. REFIO serves as either an input or output depending on
whether the internal or an external reference is selected. If
REFLO is tied to ACOM, as shown in Figure 13, the internal
reference is activated and REFIO provides a 1.20V output. In
this case, the internal reference must be compensated externally
with a ceramic chip capacitor of 0.1mF or greater from REFIO
to REFLO. Note that REFIO is not designed to drive any ex-
ternal load. It should be buffered with an external amplifier
having an input bias current less than 100nA if any additional
loading is required.
+5V
RSET
2kV
0.1mF
VOUTA
CLOCK
AD9708
+5V
ADDITIONAL
LOAD
OPTIONAL
EXTERNAL
REF BUFFER
Figure 13.Internal Reference Configuration
The internal reference can be disabled by connecting REFLO to
AVDD. In this case, an external reference may then be applied
to REFIO as shown in Figure 14. The external reference may
provide either a fixed reference voltage to enhance accuracy and
drift performance or a varying reference voltage for gain control.
Note that the 0.1mF compensation capacitor is not required
since the internal reference is disabled, and the high input
impedance (i.e., 1 MW) of REFIO minimizes any loading of the
external reference.
AVDD
AVDD
Figure 14.External Reference Configuration
The AD9708 also contains an internal control amplifier that is
used to regulate the DAC’s full-scale output current, IOUTFS.
The control amplifier is configured as a V-I converter, as shown
in Figure 14, such that its current output, IREF, is determined by
the ratio of the VREFIO and an external resistor, RSET, as stated
in Equation 4. The control amplifier allows a wide (10:1)
adjustment span of IOUTFS over a 2mA to 20 mA range by setting
IREF between 62.5mA and 625mA. The wide adjustment span of
IOUTFS provides several application benefits. The first benefit
relates directly to the power dissipation of the AD9708, which is
proportional to IOUTFS (refer to the POWER DISSIPATION
section). The second benefit relates to the 20dB adjustment,
which is useful for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 1.8 MHz and can be reduced by connecting an
external capacitor between COMP1 and AVDD. The output of
the control amplifier, COMP1, is internally compensated via a
50 pF capacitor that limits the control amplifier small-signal
bandwidth and reduces its output impedance. Any additional
external capacitance further limits the bandwidth and acts as
a filter to reduce the noise contribution from the reference
amplifier. If IREF is fixed for an application, a 0.1mF ceramic chip
capacitor is recommended.
IREF can be varied for a fixed RSET by disabling the internal
reference and varying the common-mode voltage over its
compliance range of 1.25 V to 0.10 V. REFIO can be driven by
a single-supply amplifier or DAC, thus allowing IREF to be var-
ied for a fixed RSET. Since the input impedance of REFIO is
approximately 1 MW, a simple R-2R ladder DAC configured in
the voltage mode topology may be used to control the gain. This
circuit is shown in Figure 15 using the AD7524 and an external
1.2 V reference, the AD1580. Note another AD9708 could also
be used as the gain control DAC since it can also provide a
programmable unipolar output up to 1.2 V.
ANALOG OUTPUTS AND OUTPUT CONFIGURATIONS
The AD9708 produces two complementary current outputs,
IOUTA and IOUTB, which may be converted into complementary
single-ended voltage outputs, VOUTA and VOUTB, via a load resistor,
RLOAD, as described in the DAC TRANSFER FUNCTION
section. Figure 16 shows the AD9708 configured to provide a
positive unipolar output range of approximately 0 V to +0.5 V
for a double terminated 50 W cable for a nominal full-scale
current, IOUTFS, of 20 mA. In this case, RLOAD represents the
equivalent load resistance seen by IOUTA or IOUTB and is
equal to 25 W. The unused output (IOUTA or IOUTB) can be
connected to ACOM directly or via a matching RLOAD. Different
values of IOUTFS and RLOAD can be selected as long as the posi-
tive compliance range is adhered to.
VOUTA = 0 TO +0.5VIOUTFS = 20mA
Figure 16.0 V to +0.5V Unbuffered Voltage Output
Alternatively, an amplifier could be configured as an I-V converter
thus converting IOUTA or IOUTB into a negative unipolar
1.2V
AVDD
AVDD
AD1580

Partno	Mfg	Dc	Qty	Available	Descript
AD9708AR	AD	N/a	154	avai	8-Bit, 100 MSPS TxDAC D/A Converter
AD9708ARU	AD ?	N/a	3	avai	8-Bit, 100 MSPS TxDAC D/A Converter