AD9630AN-AD9630AR Fast Delivery |IC PHOENIX CO.,LIMITED

AD9630AR ,Low Distortion 750 MHz Closed-Loop Buffer AmpSpecifications ApplyII 100% Production tested at +25

AD9630AN-AD9630AR
Low Distortion 750 MHz Closed-Loop Buffer Amp
REV.B
Low Distortion 750 MHz
Closed-Loop Buffer Amp
PIN CONFIGURATION
FEATURES
Excellent Gain Accuracy: 0.99 V/V
Wide Bandwidth: 750 MHz
Slew Rate: 1200 V/ms
Low Distortion
–65 dBc @ 20 MHz
–80 dBc @ 4.3 MHz
Settling Time
5 ns to 0.1%
8 ns to 0.02%
Low Noise: 2.4 nV/√Hz
Improved Source for CLC-110
APPLICATIONS
IF/Communications
Impedance Transformations
Drives Flash ADCs
Line Driving
GENERAL DESCRIPTION
The AD9630 is a monolithic buffer amplifier that utilizes a
patented, innovative, closed-loop design technique to achieve
exceptional gain accuracy, wide bandwidth, and low distortion.
Slew rate limiting has been overcome as indicated by the
1200V/ms slew rate; this improvement allows the user greater
flexibility in wideband and pulse applications. The second har-
monic distortion terms for an analog input tone of 4.3 MHz
and 20 MHz are –80 dBc and –66 dBc, respectively. Clearly,
the AD9630 establishes a new standard by combining out-
standing dc and dynamic performance in one part.
The large signal bandwidth, low distortion over frequency, and
drive capabilities of the AD9630 make the buffer an ideal flash
ADC driver. The AD9630 provides better signal fidelity than
many of the flash ADCs that it has been designed to drive.
Other applications that require increased current drive at unity
voltage gain (such as cable driving) benefit from the AD9630’s
performance.
The AD9630 is available in plastic DIP (N) and SOIC (R).
*Protected under U.S. patent numbers 5,150,074 and 5,537,079.
AD9630–SPECIFICATIONS
TIME DOMAIN
NOTESShort-term settling with 50 W source impedance.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS(unless otherwise noted, 6VS = 65 V; RIN = 50 V, RLOAD = 100 V)
ABSOLUTE MAXIMUM RATINGS1
Supply Voltages (–VS) . . . . . . . . . . . . . . . . . . . . . . . . . . .–7 V
Continuous Output Current2 . . . . . . . . . . . . . . . . . . . . .70 mA
Temperature Range over Which Specifications Apply
AD9630AN/AR . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . .+300°C
Storage Temperature
AD9630AN/AR . . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature3
AD9630AN/AR . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
NOTESAbsolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.Output is short-circuit protected to ground, but not to supplies. Prolonged short
circuit to ground may affect device reliability.Typical thermal impedances (part soldered onto board): Plastic DIP (N): qJA =
110°C/W; qJC = 30°C/W; SOIC (R): qJA = 155°C/W; qJC = 40°C/W.
ORDERING GUIDE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9630 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
EXPLANATION OF TEST LEVELS
Test Level100% Production tested.100% Production tested at +25°C and sample tested at
specified temperatures. AC testing of AN and AR grades
done on sample basis only.
IIISample tested only.Parameter is guaranteed by design and characterization
testing.Typical value.S Versions are 100% production tested at temperature
extremes. Other grades are sample tested at extremes.
AD9630 Burn-In Circuit
THEORY OF OPERATION
The AD9630 is a wide-bandwidth, closed-loop, unity-gain
buffer that makes use of a new voltage-feedback architecture.
This architecture brings together wide bandwidth and high slew
rate along with exceptional dc linearity. Most previous wide-
bandwidth buffers achieved their bandwidth by utilizing an
open-loop topology which sacrificed both dc linearity and fre-
quency distortion when driven into low load impedances. The
design’s high loop correction factor radically improves dc lin-
earity and distortion characteristics without diminishing
bandwidth. This, in combination with high slew rate, results in
exceptionally low distortion over a wide frequency range.
The AD9630 is an excellent choice to drive high speed and high
resolution analog-to-digital converters. Its output stage is de-
signed to drive high speed flash converters with minimal or no
series resistance. A current booster built into the output driver
helps to maintain low distortion.
Parasitic or load capacitance (>7 pF) connected directly to the
AD9630 output will result in frequency peaking. A small series
resistor (RS) connected between the buffer output and capaci-
tive load will negate this effect. Figure 1 shows the optimal value
of RS as a function of CL to obtain the flattest frequency re-
sponse. Figure 2 illustrates frequency response for various
capacitive loads utilizing the recommended RS.
AD9630
In pulse mode applications, with RS equal to approximately
12 W, capacitive loads of up to 50 pF can be driven with mini-
mal settling time degradation.
The output stage has short circuit protection to ground. The
output driver will shut down if more than approximately
130 mA of instantaneous sink or source current is reached. This
level of current ensures that output clipping will not result when
driving heavy capacitive loads during high slew conditions,
although average load currents above 70 mA may reduce device
reliability.
LAYOUT CONSIDERATIONS
Due to the high frequency operation of the AD9630 attention to
board layout is necessary to achieve optimum dynamic perfor-
mance. A two ounce copper ground plane on the top side of the
board is recommended; it should cover as much of the board as
possible with appropriate openings for supply decoupling ca-
pacitors as well as for load and source termination resistors, (see
Figure 3).
Optimum settling time and ac performance results will be
achieved with surface mount 0.1 mF supply decoupling ceramic
chip capacitors mounted within 50 mils of the corresponding
device pins with the other side soldered directly to the ground
plane. For best high resolution (<0.02%) settling times, the op-
tional power supply pins should be decoupled as shown above.
If the optional power supply pins are not used, they should be
left open.
If surface mount capacitors cannot be used, radial lead ceramic
capacitors with leads less than 30 mils long are recommended.
Low frequency power supply decoupling is necessary and can be
accomplished with 4.7 mF tantalum capacitors mounted within
0.5 inches of the supply pins. Due to the series inductance of
these capacitors interacting with the 0.1 mF capacitors and
power supply leads, high frequency oscillations might appear on
<0.1MHz
FREQUENCY RESPONSE – dB
100MHz200MHz300MHz
Figure 2.Frequency Response vs. CL
with Recommended RS
the device output. To avoid this occurrence, the power supply
leads should be tightly twisted (if appropriate). Ferrite beads
mounted between the tantalum and ceramic capacitors will
serve the same purpose.
All unused pins (except the optional power supply pins) should
be connected to ground to reduce pin-to-pin capacitive coupling
and prevent external RF interference. If the source and drive
electronics require “remote” operation (> 1 inch from the
AD9630), the PC board line impedances should be matched
with the buffer input and output resistances. Basic microstrip
techniques should be observed. RIN and RS should be connected
as close to the AD9630 as possible.
With only minimal pulse overshoot and ringing, the AD9630
can drive terminated cables directly without the use of an output
termination resistor (RS). Termination resistors (RS and RIN)
can be either standard carbon composition or microwave type.
For matching characteristic impedances, precision microwave
resistors of 1% or better tolerance are preferred.
The AD9630 should be soldered directly to the PC board with
as little vertical clearance as possible. The use of zero insertion
sockets is strongly discouraged because of the high effective pin
inductances. Use of this type socket will result in peaking and
possibly induce oscillation.
4.7mF
–VS
RIN
VINVOUT
+VS
*SEE PINOUTS
**SEE FIGURE 1
Figure 3.AD9630 Application Circuit
VOLTS
ppm
–400
Figure 4.Endpoint DC Linearity

FREQUENCY – Hz1M10M1G100M
PSRR – dB
Figure 7.PSRR vs. Frequency
FREQUENCY – Hz
MAGNITUDE – dB1G200M400M600M800M
PHASE – Degrees
Figure 10 .Forward Gain and Phase
FREQUENCY – Hz
100k
10k
10M100M1G
Figure 5.Input Impedance
INTERCEPT – +dBm
FREQUENCY – MHz25050100150200
Figure 8.2-Tone Intermodulation
Distortion

FREQUENCY – MHz
MAGNITUDE – dB020080120160
Figure 11.Frequency Response vs.
RLOAD
Figure 6.Output Impedance
Figure 9.Offset Voltage and Bias
Current vs. Temperature
Figure 12.Small-Signal Pulse
Response
2ns/DIVISION
VOLTS
0.25
AD9630
TIME – ns
SETTLING PERCENTAGE – %
Figure 13.Short-Term Settling Time
dBc
FREQUENCY – MHz
110100
Figure 16.Harmonic Distortion
VOUT = 4 V p-p
SETTLING PERCENTAGE – %
–0.11001k10k100k
TIME – ns
Figure 14.Long-Term Settling Time
dBc
FREQUENCY – MHz
100
Figure 17.Harmonic Distortion
VOUT = 2 V p-p
Figure 15.Large-Signal Pulse
Response

Partno	Mfg	Dc	Qty	Available	Descript
AD9630AN	AD	N/a	75	avai	Low Distortion 750 MHz Closed-Loop Buffer Amp
AD9630AR	AD	N/a	282	avai	Low Distortion 750 MHz Closed-Loop Buffer Amp