AD9618JR ,Low Distortion, Precision, Wide Bandwidth Op AmpCHARACTERISTICS Ru...) = IN n)
Test AD9618JN/JR AD9618AQ/SQ AD9618BQ/TQ
Parameter Conditions Temp ..
AD9618JR ,Low Distortion, Precision, Wide Bandwidth Op AmpCHARACTERISTICS Rm = 100 n)
Test AD9618JN/JR AD9618AQ/SQ AD9618BQ/TQ
Parameter Conditions Temp Le ..
AD9621AN ,Wideband Voltage Feedback AmplifierSpecifications subject to change without notice.–2– REV. 0AD96211ABSOLUTE MAXIMUM RATINGS THEORY OF ..
AD9627BCPZ-125 , 12-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
AD9630AN ,Low Distortion 750 MHz Closed-Loop Buffer AmpSPECIFICATIONSOutput Offset Voltage +25
AD9618AQ-AD9618JR
Low Distortion, Precision, Wide Bandwidth Op Amp
ANALOG
DEVICES
Low Distortion, Precision,
Wide Bandwidth 0p Amp
AD9618*
FEATURES
Usable Closed-Loop Gain Range: +51-1 to t100
Low Distortion: -63 dBc (2nd) at 20 MHz
Small Signal Bandwidth: 160 MHz (AV = +10)
Large Signal Bandwidth: 150 MHz at 5 V p-p
Settling Time: 10 ns to 0.1%; 14 ns to 0.02%
Overdrive and Output Short Circuit Protected
Fast Overdrive Recovery
DC Nonlinearity 5 ppm
APPLICATIONS
Driving Flash Converters
D/A Current to Voltage Converters
IF, Radar Processors
Baseband and Video Communications
Photodiode, CCD Preamps
GENERAL DESCRIPTION
The AD9618 is a current feedback amplifier which utilizes a
proprietary architecture to produce superior distortion and dc
precision. It achieves this along with fast settling, very fast slew
rate, wide bandwidth (both small signal and large signal), and
exceptional signal fidelity. The device achieves -ti3 dBc 2nd
harmonic distortion at 20 MHz while maintaining 160 MHz
small signal and 150 MHz large signal bandwidths.
These attributes position the AD9618 as an ideal choice for driv-
ing flash ADCs and buffering the latest generation of DACs.
Optimized for applications requiring gain between -5/-1
to t40, the AD9618 is unity gain stable without external
compensation.
Additional benefits of the AD9618B and T grades include
input offset voltage of 500 WV and temperature coefficient (TC)
of 3 wV/'C. These accuracy performance levels make the
AD9618 an excellent choice for driving emerging high resolution
(12-16 bits), high speed analog to digital converters and flash
converters.
The AD9618 offers outstanding performance in high fidelity,
wide bandwidth applications in instrumentation ranging from
network and spectrum analyzers t0 oscilloscope, and in military
systems such as radar, SIGINT, and ESM systems. The supe-
rior slew rate, low overshoot, and fast settling of the AD9618
allow the device to be used in pulse applications such as com-
munications receivers and high speed ATE. Most monolithic op
amps suffer in these precision pulse applications due to slew rate
limiting.
*Patent pending.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PIN CONFIGURATION
AD9618
- INPUT + vs
+ INPUT OUTPUT
“OPTIONAL +Vs
NOTE: FOR BEST SETTLING TIME AND DISTOR-
TION PERFORMANCE, USE OPTIONAL SUPPLY
CONNECTIONS. PERFORMANCE INDICATED IN
SPECIFICATIONS IS BASED ON SUPPLY CON-
NECTIONS TO THESE PINS.
"OPTIONAL -Vs
The AD9618] operates over the range of 0 to +70°C and is
available in either an 8-pin plastic mini-DIP or an 8 lead plastic
small outline package (SOIC). The AD9618A and B versions are
rated over the industrial temperature range of -4(Y'C to +85°C.
The AD9618S and T versions are rated over the military tem-
perature range of -5VC to +125°C; and are available processed
to MIL-STD-883B.
One Technology Way, PO. Box 9106, Norwood, MA 02062-9106
Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577
West Coast Central Atlantic
714/641-9391 214/231-5094 215/643-7790
JllM18--SPEClFltyrrlaS
ABSOLUTE MAXIMUM RATINGS1
Storage Temperature
Supply Voltages (+VS) ....................... t7 V AD9618JN/JR ................... --65c'C to + 125°C
Common Mode Input Voltage ................... tVs AD9618AQ/BQ/SQ/TQ ............. -6Y'C to + 150°C
Differential Input Voltage ...................... 3 V Junction Temperature"
Continuous Output Current2 .................. 70 mA AD9618JNOR .......................... 150°C
Operating Temperature Ranges AD9618AQ/BQ/SQ/T Q ..................... 175°C
AD9618JN/JR ....................... 0 to +70°C Lead Soldering Temperature (10 Seconds) ........ +300°C
AD9618AQ/BQ ................... -40t to +85°C
AD9618SQ/TQ .................. -55T to + 125°C
(unless otherwise noted, Av = +10; :Vs = t5 ll; RF = 1000 n,
DC ELECTRICAL CHARACTERISTICS Rm = 100 ft)
Test AD9618JNOR AD9618AQ/SQ AD9618BQ/T Q
Parameter Conditions Temp Level Min Typ Max Min Typ Max Min Typ Max Units
Input Offset Voltage', 5 725°C I -1.1 +0.5 +2.2 -l.l +0.5 +2.2 0.0 +0.5 +1.1 mV
Input Offset Voltage TCf Full IV -4 +3 +25 -sl +3 +25 -4 +3 +25 IW/T
Input Bias Currents
Inverting +25°C -45 0 +45 -45 0 +45 -20 0 +20 wh
Noninverting +25°C I -25 +5 +35 -25 +5 1 35 13 +5 718 WA
Input Bias Current TC'
Noninverting Full IV -50 +30 +125 7 50 +30 7125 -50 730 -125 nAf'C
Inverting Full IV -5() +40 + 130 -50 +40 + 130 -50 +40 + 130 nA/°C
Input Resistance
Noninverting +25°C V 75 75 75 kft
Input Capacitance
Noninverting 725°C V 1.5 1.5 1.5 pF
Common Mode Input Range" T = Tmam - 11 t-l.0 tl. r 1.0 tl. :1.0 tl. V
T---Tminto-25''C _ 11 +1.4 tl.5 71.4 :1.5 tl.4 tl.5 V
Common Mode Rejection Ratio7 T = Tmax 7 II 44 48 44 48 44 48 dB
T = +2 ''C _ II 48 52 48 52 48 52 dB
T = Tmin _ II 50 54 50 54 50 54 dB
Power Supply Rejection Ratio Ave,, = :5% Full II 50 60 50 60 50 60 dB
Open Loop Gain
TO At dc + 25°C V 3 3 3 Mn
Nonlinearity q At dc +25°C V 5 5 5 ppm
Output Voltage Range 725°C II 13.3 t3.7 :3.3 :3.7 t3.3 t3.7 V
Output Impedance At dc 725°C V 0.08 0.08 0.08 n
Output Current (50 n Load) T = +25°C to Tmax _ II 60 60 60 mA
T - Tmin K--- II 50 50 ( 50 mA
(tmless otherwise noted, Av = +10; 1t:lls = to,. ll, = 1 kn;
AC ELECTRICAL CHARACTERISTICS RLuAn = IN fl)
Test AD9618JN/JR AD9618AQ/SQ AD9618BQ/T Q
Parameter Conditions Temp Level Min Typ Max Min Typ Max Min Typ Max Units
FREQUENCY DOMAIN
Bandwidth _ dB)
Small Signal ' VOUT E, 2 V p-p Full 11 130 160 130 160 130 160 MHz
Large Signal VOUT S 5 V p-p Full IV 150 120 150 120 150 MHz
Bandwidth Variation vs. As, AV = -l to +40 +25°C V 35 35 35 MHz
Amplitude of Peaking (<50 MHZ) T 7 Tmin to 725°C - II 0 0 0.4 0 0.4 dB
T = Tmax - II 0 0 0.7 0 0.7 dB
Amplitude of Peaking (>50 MHz) T = Tmin to 725°C F-- II 0 O 0.6 0 0.6 dB
T = Tmax _ II 0 0 1.2 0 1.2 dB
Amplitude of Roll-Off (<75 MHz) Full II 0.5 0.5 1.2 0.5 1.2 dB
Phase Nonlinearity dc to 75 MHz +25°C V 0.5 0.5 0.5 Degree
2nd Harmonic Distortion 2 V p-p; 4.3 MHz Full IV -83 -75 -83 -75 -83 -75 dBc
2 V Ir-p; 20 MHz Full IV -63 _55 -63 -55 -63 -55 dBc
2 V p-p; 60 MHz Full II -51 -43 -51 -43 -51 -43 dBc
3rd Harmonic Distortion 2 V p-p; 4.3 MHz Full IV -85 -77 -85 -77 _85 -77 dBc
2 V p-p; 20 MHz Full IV -70 -62 -70 7 62 -7() -62 dBc
2 V p-p; 60 MHz Full II -62 -54 -62 -54 -62 -54 dBc
Input Noise Voltage ; 10 MHz +25°C V 1.2 1.2 1.2 nV/v 'Crt-r)
Inverting Input Noise Current 10 MHz +25°C V 24 24 24 pA/V (fl)
-2- REV. A
AD9618
Test AD961HNOR AD9618AQ/SQ AD9618BQ/TQ
Parameter Conditions Temp Level Min Typ Max Min Typ Max Min Typ Max Units
Average Equivalent Integrated
Input Noise Voltage 0.1 to 200 MHz +25T V 38 38 38 11V, rms
TIME DOMAIN
Slew Rate VOUT = 4 V Step Full IV 1800 1400 1800 1400 1800 V/ws
Rise/Fall Time
VOUT = 2 V Step Full IV 2.2 2.2 2.6 2.2 2.6 ns
VOUT = 5 V Step T = +25°C to _ IV 2.3 2.3 2.8 2.3 2.8 ns
T = Tm,n _ IV 2.3 2.3 3.1 2.3 3.1 ns
Overshoot Vorrr = 2 V Step Full IV 2 2 10 2 10 %
Settling Time
To 0.1% VOUT = 2 V Step Full IV 9 9 15 9 15 ns
To 0.02% VOUT = 2 V Step Full IV 14 14 23 14 23 ns
To 0.1% Vour = 4 V Step Full IV 10 10 16 10 16 ns
To 0.02% Votrr = 4 V Step Full IV 16 16 24 16 24 ns
2» Overdrive Recovery to
t2 mV of Final Value VIN = 0.6 V Step +25°C V 50 50 50 ns
Propagation Delay +25°C V 2 2 2 ns
Differential Gain8 Full V 0.01 0.01 0.01 %
Differential Phase8 Full V 0.02 0.02 0.02 Degree
POWER SUPPLY REQUIREMENTS
Quiescent Current
+1s Full 11 31 43 31 43 31 43 mA
-1s Full II 31 43 31 43 31 43 mA
'Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
zOutput is short circuit protected to ground, but not to supplies. Continuous short circuit to ground may affect device reliability.
'Typical thermal impedances (part soldered onto board):
Mini-DIP: Br, = 140°C/W; 61C = 30°C/W.
Side Brazed/Cerdip: (ls, = 110°C/W; 91L. = 20°C/W.
SOIC Package: 01A = 150°C/W; (Ir. = 30°C/W.
"Measured with respect to the inverting input.
'Typical is defined as the mean of the distribution.
Bfeasuredin voltage follower configuration.
7Measured with VIN = 10.25 V.
SFrequency = 4.3 MHz; RL = 150 l, As, = +10.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS ORDERING GUIDE
Test Level
I _ 100% production tested. Temperature Package Package
II - 100% production tested at +25°C and sample tested at Model Range Description Option
specified temperatures. AC testing of J grade devices done AD96181N 0 to +70°C Plastic DIP N-8
on sample basis. AD9618JR 0 to +70°C SOIC R-8
III _ Sample tested only. AD9618AQ -40''C to +85°C Cerdip Q-8
- . . . . AD9618BQ -4(Y'C to +85°C Cerdip Q-8
IV iirgrgeter IS guaranteed by design and characterization AD9 61 8 S Q - 55°C to + 125°C Cerdip Q-8
. . . AD9618TQ -55''C to +125°C Cerdip Q-8
V - Parameter IS a typical value only.
VI - All devices are 100% production tested at +25°C. 100% DIE CONNECTIONS
production tested at temperature extremes for extended W
temperature devices; sample tested at temperature s
extremes for commercial/industrial devices. D D
-iNPUT I E] W5
TOP VIEW
(Not to Scale)
+INPUT I LC] OUTPUT
D C] I
-Vs, -us
DIE SIZE = 53 x 67 X 15 mils
REV. A
AD9618
THEORY OF OPERATION
The AD9618 has been designed to combine the key attributes of
traditional "low frequency" precision amplifiers with exceptional
high frequency characteristics that are independent of closed-
loop gain. Previous "high frequency" closed-loop amplifiers have
low open loop gain relative to precision amplifiers. This results
in relatively poor dc nonlinearity and precision, as well as exces-
sive high frequency distortion due to open loop gain roll-off.
Operational amplifiers use two basic types of feedback correc-
tion, each with advantages and disadvantages. Voltage feedback
topologies exhibit an essentially constant gain bandwidth prod-
uct. This forces the closed-loop bandwidth to vary inversely
with closed-loop gain. Moreover, this type design typically slew
rate limits in a way that causes the large signal bandwidth to be
much lower than its small signal characteristics.
A newer approach is to use current feedback to realize better
dynamic performance. This architecture provides two key
attributes over voltage feedback configurations: (1) avoids slew
rate limiting and therefore large signal bandwidth can approach
small signal performance; and (2) low bandwidth variation ver-
sus gain settings, due to the inherently low open loop inverting
input resistance (Rs).
The AD9618 uses a new current feedback topology that over-
comes these limitations and combines the positive attributes of
both current feedback and voltage feedback designs. These
devices achieve excellent high frequency dynamics (slew, BW
and distortion) along with excellent low frequency linearity and
good dc precision.
DC GAIN CHARACTERISTICS
A simplified equivalent schematic is shown below. When operat-
ing the device in the inverting mode, the input signal error cur-
rent (IE) is amplified by the open loop transimpedance gain
(TO). The output signal generated is equal to To x IE. Nega-
tive feedback is applied through RF such that the device oper-
ates at a gain (G) equal to -Re/Rr.
Noninverting operation is similar, with the input signal applied
to the high impedance buffer (noninverting) input. As before,
Equivalent Circuit
an output (buffer) error current (11;) is generated at the low im-
pedance inverting input. The signal generated at the output is
fed back to the inverting input such that the external gain is
(1+ IV/RO. The feedback mechanics are identical to the voltage
feedback topology when exact equations are used.
The major difference lies in the front end architecture. A voltage
feedback amplifier has symmetrical high resistance (buffered)
inputs. A current feedback amplifier has a high noninverting
resistance (buffered) input and a low inverting (buffer output)
input resistance. The feedback mechanics can be easily devel-
oped using current feedback and transresistance open loop gain
T(s) to describe the I/O relationship. (See typical specification
chart.)
DC closed-loop gain for the AD9618 can be calculated using the
following equations:
Vo 'RF/RI . .
G = - 5t: --_-- t 1
v, 1 + l/LG inver mg ( )
V 1 + R /R
G - ii, 've-s l/FLGI noninverting (2)
l R R _ + R R I
where: -- "_s"2Lltillz_l) F SH I (3)
LG W TISHRSHRn
Because the noninverting input buffer is not ideal, input resir
tance RS (at dc) is gain dependent and is typically higher for
noninverting operation than for inverting operation. RS will ap-
proach the same value (s-S ft) for both at input frequencies
above 50 MHz. Below the open loop corner frequency, the non-
inverting RS can be approximated as:
Rs lnoninvertingt Tct. 9 - - -
where: Ao=Open Loop Voltage Gain '- Gx350
Inverting Rs below the open loop corner frequency can be ap-
proximated as:
Rs (invertingy 'ts 9 - ---
where: A0 = 140,000
R = won
ERROR RELATIVE TO FS ‘
O 0001 "/u/ DIVISION
-1 0 +1 +2
Vow - Volts
DC Nonlinearity vs. VOUT
The AD9618 approaches this condition. With TO = 3 X 106 n
and Rs = 32 n (dc), a gain error of 0.04% typically results for
G = -1 and 0.11% for G = -100. Moreover, the architecture
linearizes the open loop gain over its operating voltage range and
temperature resulting in >16 bits of linearity.
REV. A
A09618
AC GAIN CHARACTERISTICS
Closed-loop bandwidth at high frequencies is determined prima-
rily by the roll-off of T(s). But circuit layout is critical to mini-
mize external parasitics which can degrade performance by
causing premature peaking and/or reduced bandwidth.
The inverting and noninverting dynamic characteristics are simi-
lar. When driving the noninverting input, the inverting input
capacitance (C1) will cause the noninverting closed-loop band-
width to be higher than the inverting bandwidth for gains less
than five (5). In the remaining cases, inverting and noninverting
responses are nearly identical.
For best overall dynamic performance, the value of the feedback
resistor JV) should be 1000 fi. Although bandwidth reduces as
closed-loop gain increases, the change is relatively small due to
low equivalent series input impedance, ZS. (See typical perfor-
mance charts.) The simplified equations governing the device's
dynamic performance are shown below.
Closed-Loop Gain vs. Frequency:
(noninverting operation)
Vo N + R (6)
VS N 1 + Rs' + 1
where:T--RrxCc-1.0 ns (RF=1 120)
Slew Rate FW; RFKE‘C x e’T’RHth (7)
where: K71+RI
Increasing Bandwidth at Low Gains
By reducing RF, wider bandwidth and faster pulse response can
be attained beyond the specified values, although increased over-
shoot, settling time, and possible ac peaking may result. As a
rule of thumb, overshoot and bandwidth will increase by 1%
and 8%, respectively, for a 5% reduction in RF at gains of i 10.
Equations 6 and 7 are simplified and do not accurately model
the second order (open loop) frequency response term which is
the primary contributor to overshoot, peaking, and nonlinear
bandwidth expansion. (See Open Loop Bode Plots.) The user
should exercise caution when selecting RF values much lower
than 1000 fl. Note that a feedback resistor must be used in all
situations.
Increasing Bandwidth at High Gains
Closed-loop bandwidth can be extended at high closed-loop gain
by reducing RF. Bandwidth reduction is a result of the feedback
current being split between RS and RI. As the gain increases
(for a given RF), more feedback current is shunted through RI,
which reduces closed-loop bandwidth (see Equation 6). To
maintain specified BW, the following equations can be used to
approximate RF and R, for any gain from = +5/-1 t0 i40.
RF = 1100 I 8 G (8)
(f for inverting and - for noninverting)
1100 - 10 G C _ . V
R; cat fi (non1nvertmg) (9)
1100 + 10 G . _
R, ctr. T (inverting) (IO)
G - Closed-Loop Gain.
Bandwidth Reduction
The closed-loop bandwidth can be reduced by increasing IV.
Equations 6 and 7 can be used to determine the closed-loop
bandwidth for any value Re. Do not connect a feedback capaci-
tor across RF, as this will degrade dynamic performance and
possibly induce oscillation.
DC Precision and Noise
Output offset voltage results from both input bias currents and
input offset voltage. These input errors are multiplied by the
noise gain term (1 + RF/RI) and algebraically summed at the
output as shown below.
Re q Rr' .
VOZVIOX 11" iIBnXRNX 1+_-" :IBIXRF (11)
Since the inputs are asymmetrical, IBi and IBn do not correlate.
Canceling their output effects by making Rs = RAR, will not
reduce output offset errors, as it would for voltage feedback am-
+10 +1.0
o \\\\
Vlo — mV
lBi/an — ”A
-55"C +25'C +125°C
DC Accuracy
plifiers. Typically, IBn is 5 " and VIO is +0.5 mV (1 sigma =
0.3 mV), which means that the dc output error can be reduced
by making Rs 'war 100 l Note that the offset drift will not
change significantly because the IBn TC is relatively small. (See
specification table.)
