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AD9561JR-AD9561JR-REEL
Pulse Width Modulator
REV.0
Pulse Width Modulator
FUNCTIONAL BLOCK DIAGRAM
FEATURES
60 MHz Pulse Rate
8-Bit Resolution
Center, Left or Right Justify
Low Power:700 mW typical
Minimum Pulse Width:<5 ns
Maximum PW:100 % Full-scale
APPLICATIONS
Laser Printers
Digital Copiers
Color Copiers
GENERAL DESCRIPTIONThe AD9561 is a second generation high speed, digitally
programmable pulse width modulator (PWM). Output pulse
width is proportional to an 8-bit DATA input value. Two
additional control inputs determine if the pulse is placed at the
beginning, middle or end of the clock period. Pulse width and
placement can be changed every clock cycle up to 60 MHz.
Pulse width modulation is a well proven method for controlling
gray scale and resolution enhancement in scanning laser print
engines. Modulating pulse width provides the most cost
effective method for continuous tone reproduction and resolu-
tion enhancement in low-to-moderate cost scanning electro-
photographic systems.
The AD9561 uses precision analog circuits to control dot size
so that near-photographic quality images are practical without
the high frequency clock signals required by all digital approaches.
The AD9561 has improved features and performance over its
predecessor, the AD9560. An improved ramp topology enables
control of pulse width through 100% of the dot clock period as
opposed to 95% for the AD9560. This enables smooth transi-
tion across dot boundaries for line screen applications.
Additionally, input data setup and hold time are symmetrical at
2 ns each, simplifying interface to the system bus.
Finally, chip design and pinout are optimized to decrease
sensitivity of analog circuits to digital coupling. (See layout
section for detailed recommendations for optimum results.)
Inputs are TTL or CMOS compatible, and outputs are CMOS
compatible. The AD9561JR is packaged in a 28-lead plastic
SOIC. It is rated over the commercial temperature range, 0°C
to +70°C.
HIGHLIGHTS60 MHz native printer clock rate.Single +5 V power supply.On-chip Autocalibration.Pulse placement flexibility.High resolution: 256 pulse widths.
AD9561–SPECIFICATIONS(+VS = +5 V; RSET = 715 V, CLOCK = 20 MHz unless otherwise noted)NOTESBest Fit between codes 25 and 230. INL is very layout sensitive.Due to linearity mismatch in dual ramps.Measured from rising edge of clock to transition of Codes 0 to 255.Minimum pulse width (at 20 MHz) limited by rise time. Pulse width for Code 25 will be greater when CLOCK < 20 MHz.Output load = 10 pF and 2 mA source/sink.Load conditions to test output drive capability. Linearity will degrade with either capacitive or current loading. Best linearity obtained driving a single CMOS input.All performance specifications valid when supply maintained at +5 V, ±5%.Tested from +4.75 V to +5.25 V.
Specification subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1Positive Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V
Digital Input Voltage Range . . . . . . . . . . . . . . .–0.5 V to VDD
Minimum RSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Ω
Digital Output Current (Sourcing)2 . . . . . . . . . . . . . . .10 mA
Digital Output Current (Sinking)2 . . . . . . . . . . . . . . . .10 mA
Operating Temperature Range3 . . . . . . . . . . . . .0°C to +70°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Lead Soldering Temperature (10 sec)4 . . . . . . . . . . . .+300°C
NOTESAbsolute maximum ratings are limiting values, to be applied individually, and
beyond which serviceability may be impaired. Functional operation under any of
these conditions is not necessarily implied.CAL OUT should drive a single TTL or CMOS input.Typical Thermal Impedance:
28-lead SOIC (plastic) θJA = 71.4 °C/W; θJC = 23°C/W.When soldering surface mount packages in vapor phase equipment, temperature
should not exceed 220°C for more than one minute.
ORDERING GUIDE*Tape and Reel ordered in multiples of 1000 ICs.
PIN CONFIGURATION
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000
AD9561
THEORY OF OPERATION
GeneralThe AD9561 is a mixed signal IC designed to provide high-
speed pulse width modulation in laser printers and copiers. It
uses high performance analog circuits to achieve high resolution
pulse control without requiring the excessively high clock rates
of an all digital solution.
Because of the sensitivity of analog circuits to digital crosstalk,
PCB layout is critical for achieving optimum results. Please read the
layout section at the end of this data sheet and follow suggestions
completely for best performance.
The AD9561 was designed to facilitate either higher effective
resolution or photo-realistic image reproduction on low cost
laser print platforms. Its 8-bit pulse width resolution and pulse
positioning capabilities combine to offer the highest level of gray
shading and resolution enhancement flexibility available. It
also includes an autocalibration circuit to minimize external
components, and eliminates an extra burden on the system
microprocessor.
The Functional Block Diagram illustrates the analog content,
comprising ramp generators, DACs and comparators that
generate a series of pulses. These pulses are combined in the
output logic to form PWM OUT pulses whose width is propor-
tional to the 8-bit DATA and whose position is determined by
the SEM/DEM and LEM/TEM inputs.
The AD9561 employs a proprietary ramp topology that
eliminates the loss of dynamic range at the ends of the ramp.
The Functional Block Diagram is shown for illustration purposes
only and does not represent the actual implementation.
Modulation ModesPositioning the width controlled pulses at the beginning, middle
or end of the CLOCK period, as shown in Figure 2, adds
significantly to the flexibility of the AD9561. This is accom-
plished through control bit SEM/DEM and LEM/TEM. These
acronyms represent Single-Edge Modulation/Dual-Edge
Modulation and Leading-Edge Modulation/Trailing-Edge
Modulation. SEM/DEM and LEM/TEM are collectively
identified as CONTROL.
Figure 2.Modulation Modes
Pulse positioning within the CLOCK period is defined by the
following table:
Table I.Truth TableSingle-Edge Modulation offers two options in which one edge is
modulated while the other remains fixed relative to the CLOCK.
For Leading-Edge Modulation, the rising edge of the pulse is
delayed from the leading edge of the CLOCK proportional to
DATA, and the falling edge remains fixed at the end of the
CLOCK period. This may also be called “right-hand justified.”
Similarly, Trailing-Edge Modulation has the rising edge fixed
on the beginning of the CLOCK period and the falling edge
delayed proportional to DATA. This can be called “left-hand
justified.”
Dual-Edge Modulation is often called “center justified” because
the delay of both edges varies relative to the CLOCK. With
increasing values for DATA, pulse width increases with its
center remaining constant proportional to the CLOCK.
Like DATA, modulation control inputs SEM/DEM, and
LEM/TEM can be updated at the CLOCK rate up to 60 MHz.
Figure 1.Pulse Pattern Example
N+1
CLOCK
DATA
CONTROL
OUTPUT
100%
DNC
DNC
75%
TEM
75%
DEM
87%
LEM
75%
DEM
75%
DEM
50%
DEM
25%
DEM
DNC
Pulse Pattern ExampleFigure 1 at the top of the previous page illustrates the PWM
OUT of the AD9561 with various DATA and CONTROL
inputs. The DATA format is Binary. In the Pulse Pattern
Example, the Hexadecimal format is used, i.e., FFH represents
decimal 255.
The top line shows the CLOCK; the second shows DATA and
CONTROL inputs, which are latched on the rising edge of
CLOCK. The third line shows the resulting pulse.
The AD9561 DATA and CONTROL inputs are double
latched. The OUTPUT pulse labeled “Pulse N” results from
DATA and CONTROL values latched in by the first CLOCK,
illustrating the one CLOCK period timing delay.
The CONTROL value number for pulse one is shown as xx.
This means the value is not important because a 100% pulse
will be output for any CONTROL value for DATA value 255 or
FFH. Likewise, OUTPUT Pulse N is noted as 100% DNC (do
not care), also noting that CONTROL value is unimportant.
The fourth DATA/CONTROL value is C0/0X. This indicates
that the level for LEM/TEM is unimportant when SEM/DEM is
logic Level “0”.
Selecting RSETBecause the AD9561 must provide full range coverage of the
CLOCK pulse period, the ramp time must be matched to the
CLOCK period. All components for the ramp generators, except
RSET, are integrated in the AD9561.
RSET, is selected by the user to set the ramp time close to the
CLOCK period. The ramps are generated by constant current
sources charging on-chip capacitors.
RSET can be chosen in the range from 226 Ω for 60 MHz
operation to 16.5 kΩ for 1 MHz. Because the absolute value of
the on-chip capacitor can vary by ±20%, the autocalibration
circuit is included to fine tune the matching of the ramp time to
the CLOCK period.
RSET – kΩ
CLOCK FREQUENCY – MHzFigure 3.RSET Values vs. CLOCK Frequency
Figure 3 shows approximate values for RSET over the operating
frequency range. The following equation should be used to
determine RSET:
where F is the CLOCK frequency in Hz. The resistor value
determined by the equation will generate a current near center-
range of the autocalibration circuit.
AutocalibrationThe AD9561 should be calibrated when power is applied to the
system or after a power reduce cycle.
Figure 4.Autocalibration Timing
Autocalibration is initiated by applying a pulse of 1 μs minimum
duration to Pin 17, CAL START. The CLOCK pulse should be
applied continuously during calibration. As Figure 4 shows, the
initial state of CAL OUT is not known.
During the CAL IN pulse, all internal logic is initialized for
calibration and proper synchronization once calibration is
complete; the falling edge of CAL IN initiates the Auto-CAL
cycle.
Auto-CAL is not affected by the code applied to the DATA or
CONTROL inputs. However, to assure that no pulses are
generated during calibration, it is suggested that all digital
inputs be held at Logic “0.”
On the falling edge of CAL IN, the ramp’s slope is set as slow as
possible for the current RSET. Figure 4 shows the RAMP slope
increasing as autocalibration adds small incremental currents,
until it crosses the internal REF LO before the end of the
CLOCK period.
RAMP
REF LO
RAMP
END OF CLOCK CYCLEFigure 5.Autocalibration Conceptual
The calibration current is incremented on each 32nd CLOCK
pulse until the full-scale ramp time is equal to the period of the
CLOCK. Cal Complete is detected and CAL OUT goes high
when the ramp crosses REF LO before it is reset by the next
CLOCK. With a maximum of 64 incremental increases, the
maximum autocalibration time, tAC, can be calculated by the
AD9561This yields the maximum time from the trailing edge of CAL IN
to the rising edge of CAL OUT. As an example, the maximum
time required for auto-calibration for a system with clock frequency
of 20 MHz is 102.4 ms plus the width of the CAL IN pulse.
Power ReduceThe POWER REDUCE function permits the user to power
down all nonessential circuits when the printer is not active.
Applying a Logic “0” to POWER REDUCE decreases the
power supply requirement by approximately half.
APPLICATIONS
DATA TimingInput DATA to the AD9561 is double latched. As a result of the
internal timing, the OUTPUT is delayed more than one clock
period from its corresponding DATA word. Figure 6 illustrates
timing of DATA and CONTROL inputs relative to the CLOCK.
SETUPHOLD
CLOCK
DATA
CONTROLFigure 6.DATA and CONTROL Timing
The DATA and CONTROL inputs to the AD9561 are stan-
dard master-slave latches. Inputs are latched in on the rising
edge of the CLOCK with 2 ns Set-Up time and 2 ns Hold time.
This is a design improvement over the AD9560 meant to
simplify interfacing the AD9561 to digital processing circuits.
A propagation delay exists between the CLOCK and OUTPUT
pulses. The minimum propagation delay can be observed when
alternating between codes 0 (00H hexadecimal) and 255 (FFH
hexadecimal). This delay is due in part to normal circuit
propagation; the remainder is due to time required to imple-
ment the proprietary ramp function. OUTPUT pulse transi-
tions will typically occur 22 ns after the rising edge of CLOCK.
It may vary from 10 ns–35 ns over temperature.
Transfer FunctionOutput pulse width increases with increasing DATA values. As
the heavy line of Figure 7 shows, the transfer function of the
AD9561 is slightly nonideal.
PULSE WIDTH – PercentageAn ideal transfer would give 0% (or 0 ns) pulse width for a Code 0.
As the code is incremented in steps of one, the pulse width would
increase by 0.39% until it reached 100% for Code 255.
When operating at high clock rates, several of the most narrow
pulses do not reach valid logic Level “1” because of finite rise
time. For example, at 20 MHz, a 1.95% pulse (code 5 or 05H)
would have an expected pulse width of 1 ns. Because the rise
time is typically 1.5 ns, this pulse will not reach a full output
level. Therefore, depending on the clock rate, the lowest set of
codes produces a series of triangle waves increasing in width
and amplitude until a pulse of approximately 3 ns–5 ns reaches
a proper logic level. Thus, the transfer is flat until about
3 ns–5 ns pulse width (number of codes varies as a function of
CLOCK frequency).
Because of the new ramp topology in the AD9561, the transfer
function extends slightly greater than 100% (typically 102%) of
the clock period. This has the effect of creating smooth transitions
at the CLOCK period boundaries instead of the discontinuities
produced by the AD9560.
tPD
TEM
(LEFT JUSTIFIED)
DEM
(CENTER JUSTIFIED)
LEM
(RIGHT JUSTIFIED)Figure 8.Dot Clock Period Transitions
As shown in Figure 8, a Leading Edge Modulated pulse followed
by a Trailing Edge Modulated pulse will stay high from the rising
edge of the first pulse to the falling edge of the second. This is
due to Code 255 being designed to be typically 102% of the
CLOCK period. (Dashed lines indicate where transitions
would occur if the code for the following or preceding period
were 0.) Likewise, no gap occurs for maximum width Trailing
Edge Modulation to max pulse width for Dual Edge Modula-
tion. Because the ending and starting characteristics of all
modes are symmetrical, any combination of pulses that ends at
the boundary of the first period and starts at the boundary of
the second period will produce a continuous pulse across the
boundary.
For the purposes of printing text, or any time absolute white or
black is required, 0 is decoded and a 100% LOW is output in
the next CLOCK cycle. Similarly, 255 is detected and the next
pulse is 100% HIGH.
RetraceThe RETRACE function permits driving the output to a
constant Logic High. For laser printer applications, applying a
logic “1” to RETRACE holds the laser on during the retrace
period so end of scan can be detected. Returning it to Logic
Low gives control back to the input data bits D0–D7.
