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AD9560KR
High Speed Monolithic Pulse Width Modulator
ANALOG
DEVICES
High Speed Monolithic
Pulse Width Modulator
A0956!)
FEATURES
Up to 50 MHz Pulse Rate
Autocalibration on Chip
8-Bit Resolution
Center, Leading, Trailing Edge Modulation
Low Power: 335 mW
Single +5 V Operation
APPLICATIONS
Laser Printers
Gray Scale Capability
Resolution Enhancement
Add-In Boards
Digital Copiers (Photo Mode)
Color Copiers
Optical Disk Drives
Precision Pulse Placement
GENERAL DESCRIPTION
The AD9560 is a high speed, digitally programmable pulse
width modulator (PWM). Output pulse width is proportional to
an 8-bit DATA input value. Two additional CONTROL inputs
determine if the pulse is placed at the beginning, middle, or end
of the clock period. Pulse width and placement can be changed
every clock cycle up to 50 MHz. All inputs and outputs are
CMOS compatible.
Pulse width modulation is a proven and increasingly popular
method for controlling gray scale and/or resolution enhancement
in laser printers. The AD9560 provides a one chip solution to
pixel-by-pixel control which yields much greater true resolution
than "super pixel" techniques that are in use in present genera-
tion printers. High resolution is possible without significant
increase in dot clock frequency which is necessary for "super
pixel" methods.
Super pixel graphics, in effect, "trick the eye" by scattering dif-
ferent size pixels in varying densities. At a distance, these
images appear to have high quality gray scale characteristics.
Upon close inspection, a similar graphic utilizing pixel-by-pixel
modulation demonstrates that resolution has been compromised
to obtain gray scale.
In a basic laser printer or copier, the laser diode is either "on"
or "off' for any pixel period. By utilizing the AD9560 ahead of
the laser diode, each pixel can be controlled to increments equal
to 1/256 of the pixel period. With the additional on-chip place-
ment control (i.e., center, leading, and trailing edge modula-
tion), 764 different pulse size/position options are theoretically
possible.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
CONTROL[ o-at''- 11i2 l PWM
PLA EMENT ' (
CONTROL OUT
OUTPUT
8 PULSE
DATA WIDTH V
, CONTROL
CLOCK AUTO
CAL IN CALIBRATION t CAL
SET OUT
AD9560
For images containing text and graphics, mixed-mode operation
may be required. The pulse width modulation feature of the
AD9560 is disabled simply by inputting the codes 00H and
FFH. The output will be logic zero and logic one respectively
for the entire clock cycle.
The AD9560 pulse width modulator is fully self-contained,
requiring only a single resistor (RSET) to match the nominal
full-scale range to the DOT CLOCK. An on-chip auto-
calibration circuit fine tunes the range and compensates for lot-
to-lot variation of on-chip timing circuits.
With autocalibration and SOIC packaging the AD9560 is well
suited for volume, automated assembly. In addition to 28-lead
SOIC (AD9560KR), 28-pin P-DIP (AD9560KN) is also avail-
able. Both devices are rated over the commercial temperature
range, 0°C to +70°C.
HIGHLIGHTS
l. Single -5 V power supply.
. Autocalibration on chip.
. Complete pulse placement flexibility.
. High-resolution: 256 pulse widths.
. Low power: 335 mW.
. Automatic 00n and FF,, decoding.
O\UI4>WN
One Technology Way, PO. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
1109550 "--SMlFltyrrl0lG
ELECTRICAL CHARACTERISTICS (+lls = +5 ll; Rm = 2.55 m, CLOCK = N MHz, unless otherwise indicated)
Test I AD9560KN AD9560KR
Parameter Temperature Level , Min Typ Max Min Typ Max Units
RESOLUTION 8 8 Bits
ACCURACY ((F 1 MHz)
Differential Linearity +25°C V 0.25 0.25 LSB
Integral Linearityl +25°C V 0.15 0.15 LSB
Ramp Misalignment +25°C V 1.5 1.5 LSB
ACCURACY (Gr 20 MHz)
Differential Linearity +25°C I 0.4 0.4 2.0 LSB
Integral Linearityl +25°C I . 1.5 4.0 LSB
Ramp Misalignment +25°C V 1.5 1.5 LSB
DIGITAL INPUTS
Logic "I'' Voltage Full 11 3.5 3.5 V
Logic "O" Voltage Full II 1.0 1.0 V
Input Current Full 11 tl t l "
Input Capacitance +25°C V 5 5 pF
Data Setup Time2, 3 +25°C IV - 11.9 -8 - 11.9 " ns
Data Hold Time3 +25°C IV 14.4 19.2 14.4 19.2 ns
Data Setup Timer 3, 4 Full IV 6 -6 ns
Data Hold Times, 4 Full IV 24 24 ns
Minimum Clock Pulse Widths Full V 7 7 ns
DYNAMIC PERFORMANCES
Maximum Trigger Rate Full IV 40 50 40 50 MHz
Minimum Propagation Delay (teo)6 Full II 24 34 44 24 34 44 ns
Minimum Propagation Delay TC Full V 98 98 ps/°C
Output Pulse Width C4 Code 25 Full V 5 5 ns
OutputPulse Width (ir Code 254 Full V 90 90 % Clock
Output Rise Time7 Full II 2.1 3.0 2.1 3.0 ns
Output Fall Time' Full 11 1.9 3.0 1.9 3.0 ns
DIGITAL OUTPUT
Logic "I'' Voltage7 Full II 4.6 4.6 V
Logic "O'' Voltage7 Full II 0.4 0.4 V
POWER SUPPLY5
Positive Supply Current (+5.0 V) Full II 67 87 67 87 mA
Power Dissipation Full 11 335 435 335 435 mW
Power Supply Rejection Ratio
(teo) Sensitivity (TEM)8 +25°C V 3.5 3.5 ns/V
'Measured at endpoints.
2When operating at or near maximum CLOCK rate, CLOCK edge should lead DATA change, making Data Setup Time negative. See Timing Diagram.
'Specified for CMOS logic driver.
4The time interval between Data Setup Time and Data Hold Time is relatively constant over the full temperature range. If an appropriate CMOS clock is used,
the temperature coefficient of the data window will track the temperature coefficient of the input clock.
5Power supply should be maintained at +5 V, t 10% during normal operation.
6Measured from rising edge of clock to transition of overdrive codes 00H and FF,,.
'Output load = 10 pF and 2 mA source/sink.
8Tested from +4.5 V to +5.5 V.
Specifications subject to change without notice.
-2- REV. o
ADS560
ABSOLUTE MAXIMUM RATINGS1
Positive Supply Voltage ...................... +7 V
Digital Input Voltage Range ............ -0.5 V to +5 V
Minimum Rswr ........................... 500 n
Digital Output Current (Sourcing)2 .............. 10 mA
Digital Output Current (Sinking)2 ............... 10 mA
Operating Temperature Range3
D9560KN, KR ..................... 0°C to +70°C
Storage Temperature Range ........... -65''C to +150°C
Junction Temperature ...................... + 150°C
Lead Soldering Temperature (10 sec)4 ........... +300°C
lAbsolute maximum ratings are limiting values, to be applied individually, and
beyond which serviceability may be impaired. Functional operability under
any of these conditions is not necessarily implied.
2CAL OUT should drive a single high impedance input.
'Typical thermal impedance:
28-Pin Plastic DIP "rs = 37"C/W; G: = 10°C/W
28-Pin SOIC (Plastic) em = 46°C/W; G: - 10°C/W
'When soldering surface mount packages in vapor phase equipment, tempera-
ture should not exceed 220°C for more than one minute.
EXPLANATION OF TEST LEVELS
Test Level
I - 100% production tested.
II - 100% production tested at +25°C, and sample tested at
specified temperatures.
m - Periodically sample tested.
IV - Parameter is guaranteed by design and characterization
testing.
V - Parameter is a typical value only.
VI _ All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for
extended temperature devices; sample tested at
temperature extremes for commercial/industrial devices.
ORDERING INFORMATION
Temperature I Package Package
Model Range Description Option
AD9560KN 0°C to +70°C 28-Pin P-DIP
AD956OKR 0°C to +70°C 28-Lead SOIC
REV. 0
PIN CONFIGURATION
(P-DIP or SOIC)
D7(MSB) E
COMP E
Van LE
CAL OUT It
GND 12
GND 13
(Not to Scale)
E Do (LSB)
24 LEM/TEM
23 SEM/DEM
AD9560 22 GND
TOP VIEW
21 Van
E CLOCK
El CAL IN
E RSET
PIN DESCRIPTIONS
00\IO\UI)—-
PWM OUT
CAL OUT
CAL IN
SEM/DEM
LEM/TEM
Digital Data Bits; D7 is MSB
Bias Supply Bypass (0.47 WF)
Ground Return
F5 V Supply
Pulse Width Modulated Output
Ground Return
+5 V Supply
Calibration Complete Signal
Ground Return
Ground Return
+5 V Supply
Ramp Current Set Resistor
Ground Return
Ground Return
+5 V Supply
Initiates Autocalibration
Dot Clock Input
+5 V Supply
Ground Return
Controls Single or Dual Edge
Modulation
Controls Leading or Trailing Edge
Modulation
Digital Data Inputs; D0 is LSB
CLOCKJ
l l ' l .
DATA-:X FF DATA oo DATAX co co ilr,ri i), 1 X40 I X00 1 "co X50 I FF I if
CONTROL xx N xx N+1 10 ox ox l ox I ox I xx I ox 11 L xx
I It I Size I121; 65517. I Em 3% I 'git, I I373; 5%. I EEK; I Iff
OUTPUT "li" 'ly," Li Ll Li l l ll l
Figure 1. Pulse Pattern Example
THEORY OF OPERATION
General
The AD9560 is a mixed signal IC designed to facilitate high
speed pulse width modulation in laser printers and copiers. In
order to deliver superior linearity and speed while maintaining
low power dissipation, it is fabricated in a BiCMOS process.
The AD9560's 8-bit pulse width resolution and pulse positioning
capabilities combine to offer a high level of gray shading flexibil-
ity in laser beam printers or copiers. In addition to its pulse
control, it also includes an autocalibration circuit to minimize
external components and eliminate extra burden on the system
microprocessor.
A parallel architecture comprising ramp generators, DACs, and
comparators creates a group of pulses. These are combined in
the output logic to form OUT pulses whose width and place-
ment are representative of the 8-bit pulse width DATA and the
pulse placement CONTROL inputs.
Modulation Modes
Positioning the width-controlled pulses at the beginning, mid-
dle, or end of the CLOCK period adds significantly to the flexi-
bility of the AD9560. This is accomplished through CONTROL
bits SEM/DEM and LEM/TEM. These acronyms represent
single-edge modulation/dual-edge modulation; and leading-edge
modulation/trailing-edge modulation. SEM/DEM and LEM/
TEM are collectively identified as CONTROL.
Pulse positioning within the DOT CLOCK period is defined by
the following CONTROL Truth Table:
SEM/DEM LEM/TEM Alignment
1 l LEM (RHJ)
1 0 TEM (LHJ)
0 X DEM (CJ)
Single-edge modulation offers two options in which one edge is
modulated while the other remains fixed relative to the DOT
CLOCK. For leading-edge modulation, the rising edge of the
pulse is delayed from the leading edge of the DOT CLOCK
proportional to DATA, and the falling edge remains fixed at the
end of the DOT CLOCK period. This may also be called
"right-hand justified" (RHJ).
Similarly, trailing-edge modulation has the rising edge fixed on
the beginning of the DOT CLOCK period, and the falling edge
delayed proportional to DATA. This can be called "left-hand
justified" (LHJ).
Dual-edge modulation is often called "center justified" (CI)
because the delay of both edges vary relative to the DOT
CLOCK. The rising edge is delayed from the leading edge of
the CLOCK, and the falling edge is delayed from the center of
the CLOCK period. Thus, with increasing values for DATA,
pulse width increases with its center remaining constant propor-
tional to the DOT CLOCK.
Like DATA, modulation control inputs SEM/DEM and LEM/
TEM can be updated at the DOT CLOCK rate, up to 50 MHz.
Pulse Pattern Example
The diagram at the top of the page illustrates the output of the
AD9560 with various DATA (Pins l-al, 25-28) and CONTROL
(Pins 23, 24) inputs. This does not take into account any delays,
which will be explained later, but assumes an ideal timing rela-
tionship for clarity.
The top line shows the DOT CLOCK; the second shows DATA
and CONTROL inputs being updated on the rising edge of
CLOCK. DATA and CONTROL values are shown near the
beginning of the DATA/CONTROL period. The third line
shows the resulting pulse with an explanation of the pulse
between the second and third lines.
The first DATA/CONTROL period is indicated as DATA N,
and the second as DATA N+ 1. The second and third pulses are
labeled as Pulse N and N+ 1, illustrating the one CLOCK
period pipeline delay. The vertical dashed lines show the rele-
vant point of reference of the CLOCK to each output pulse.
The CONTROL value number one is shown as XX; this means
the value is not important because a 100% pulse will be output
for any CONTROL value. Likewise, Pulse N is noted as 100%,
DNC (do not care) noting that CONTROL value is unimportant.
The fourth DATA/CONTROL value is CO/OX, indicating that
the level for LEM/TEM is unimportant when SEM/DEM is
logic level zero (LLO).
Selecting RSET
For the AD9560 to provide full range coverage of the CLOCK
pulse period, the ramp time must be matched to the CLOCK
period. All components for the ramp generators except RSET are
integrated in the AD9560. RSET is customer selected, depending
upon the DOT CLOCK frequency.
The ramps are generated by constant current sources charging
on-chip capacitors. RSET can be chosen in the range from
approximately 1 kft for 50 MHz operation to 50 kn for 1 MHz.
Because the absolute value of the on-chip capacitor can vary
substantially, an autocalibration circuit is included to fine tune
matching of ramp time to the DOT CLOCK period.
REV. 0
h0%iil
CLOCK FREQUENCY — MHz
1 10 100
RSET- "t
Figure 2. Rser vs. CLOCK Frequency
Figure 2 shows approximate values for RSET over the operating
frequency range. For more precise determination, the following
equation should be used:
RSET _ 10[10.951-1.033/0g1f1]
f = CLOCK Frequency in Hz.
The closest value of 1% metal-film resistor should be used. This
resistor will generate a current within the range of the auto-
calibration circuit. Thus, the value for RSET calculated for a
particular print engine will be correct for device-to-device timing
variations, even from different production lots.
where:
Autocalibration
The AD9560 should be calibrated on power-up and any time
normal operation is interrupted. The AD9560 will maintain its
accuracy over its rated temperature range as long as power is
applied.
Some high-precision printing applications may require periodic
calibration during normal operation to assure consistency of
print contrast from the lightest to the darkest shades. The fre-
quency of calibration depends upon sensitivity of the laser print
engine and/or significant ambient temperature variation.
CALIN - MIN -
CAL OUT
Figure 3. AutoCAL Timing
Autocalibration is initiated by applying a pulse of l ILS mini-
mum duration to Pin 19, CAL IN. The CLOCK pulse should
be applied continuously during calibration. CAL IN should
remain high for a minimum of 1 us to allow the calibration cur-
rent to settle to its lowest value. Also, during the CAL IN
pulse, all internal logic is initialized for calibration and proper
synchronization once calibration is complete; the falling edge of
CAL IN initiates the Auto-Cal cycle.
REV. O
Auto-Cal is not affected by the code applied to the DATA or
CONTROL inputs. However, to ensure that no OUT pulses are
generated during calibration, it is suggested that all digital
inputs be held at logic zero.
On the falling edge of CAL IN, the calibration circuit contrib-
utes no additional current to the primary charging current con-
trolled by RSET. The calibration current is incremented on each
32nd CLOCK pulse until the full-scale ramp time is equal to the
period of the CLOCK. With a maximum of 64 incremental
increases, the maximum autocalibration time, tac, can be calcu-
lated by the equation:
tac = l32/fc) . 64
[AC = 2048 . tc
fc = CLOCK frequency in hertz
tc = CLOCK period in seconds
This yields the maximum time from the trailing edge of CAL
IN to the rising edge of CAL OUT. As an example, the maxi-
mum time required for autocalibration for a system with clock
frequency of 10 MHz is 204.8 HS.
where:
APPLICATIONS
DATA Timing
Input DATA to the AD9560 is double buffered, resulting in a
one-CLOCK-period delay for a given DATA word until its
related output. Figure 4 illustrates timing of DATA relative to
the CLOCK for worst case conditions, operating at 50 MHz.
CO NTROL
Figure 4. DATA and CONTROL Timing
A longer delay exists from the CLOCK input to the latching
circuit than from the DATA inputs. Therefore, setup is a nega-
tive number, ranging from -6 ns to - 16 ns over temperature.
The DATA must remain valid from 12 ns to 24 ns after the
rising edge of CLOCK.
At 50 MHz, the CLOCK period is 20 ns. At room temperature,
with a worst case setup time of -8 ns, and worst case hold time
of 19.2 ns, DATA should be updated in the window from 0 ns
to 8 ns after the rising edge of CLOCK. Lower frequencies will
have greater tolerance to DATA timing.
OUTPUT Delay
A propagation delay exists between the CLOCK and OUT
pulses. The minimum propagation delay can be observed when
alternating between codes 00H and FFH. OUT pulse transitions
will typically occur 34 ns after the rising edge of CLOCK for
20 MHz operation. This delay is due to logic propagation and
may vary from 24-44 ns over temperature.
