AD9540BCPZ Fast Delivery |IC PHOENIX CO.,LIMITED

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AD9540BCPZ
655 MHz Low Jitter Clock Generator
655 MHz Low Jitter Clock GeneratorRev. 0
FEATURES
Excellent intrinsic jitter performance
25 Mb/s write-speed serial I/O control
200 MHz phase frequency detector inputs
655 MHz programmable input dividers for the phase fre-
quency detector (÷M, ÷N) {M, N = 1..16} (bypassable)
Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)
8 programmable internal clock rates
Programmable edge delay with 93 fS resolution
1.8 V supply for device operation
3.3 V supply for I/O, CML driver, and charge pump output
Software controlled power-down
48-lead LFCSP package
Programmable charge pump current (up to 4 mA)
Multichip synchronization
Dual-mode PLL lock detect
655 MHz CML-mode PECL-compliant driver
APPLICATIONS
Clocking high performance data converters
Base station clocking applications
Network (SONET/SDH) clocking
Gigabit Ethernet (GbE) clocking
Instrumentation clocking circuits
FUNCTIONAL BLOCK DIAGRAM
AVDDAGNDDVDDDGNDVCMLVCPCP_RSET
REFIN
REFIN
CLK1
CLK1
SYNC_IN/STATUS
SCLK
SDI/O
SDO
CLK2
CLK2
OUT0
OUT0
VCMLIOUT
IOUT
DAC_RSET
04947-001
Figure 1.
TABLE OF CONTENTS
Product Overview.............................................................................3
Specifications.....................................................................................4
Loop Measurement Conditions..................................................9
Absolute Maximum Ratings..........................................................10
ESD Caution................................................................................10
Pin Configuration and Function Descriptions...........................11
Typical Performance Characteristics...........................................13
Typical Application Circuits..........................................................18
Application Circuit Descriptions.............................................18
General Description.......................................................................19
PLL Circuitry..............................................................................19
CML Driver.................................................................................19
DDS and DAC............................................................................20
Modes of Operation.......................................................................21
Selectable Clock Frequencies and Selectable Edge Delay.....21
Synchronization Modes for Multiple Devices..............................21
Serial Port Operation.....................................................................22
Instruction Byte..........................................................................23
Serial Interface Port Pin Description.......................................23
MSB/LSB Transfers....................................................................23
Register Map and Description......................................................24
Control Function Register Descriptions.................................27
Outline Dimensions.......................................................................32
Ordering Guide..........................................................................32
REVISION HISTORY
7/04—Revision 0: Initial Version
PRODUCT OVERVIEW
The AD9540 is Analog Devices’ first dedicated clocking product
specifically designed to support the extremely stringent clock-
ing requirements of the highest performance data converters.
The device features high performance PLL circuitry, including a
flexible 200 MHz phase frequency detector and a digitally
controlled charge pump current. The device also provides a low
jitter, 655 MHz CML-mode, PECL-compliant output driver with
programmable slew rates. External VCO rates up to 2.7 GHz are
supported. Extremely fine tuning resolution (steps less than
2.33 µHz) is another feature supported by this device. Informa-
tion is loaded into the AD9540 via a serial I/O port that has a
device write-speed of 25 Mb/s. The AD9540 frequency
divider block can also be programmed to support a spread
spectrum mode of operation.
The AD9540 is specified to operate over the extended
automotive range of −40°C to +85°C.
SPECIFICATIONS
AVDD = DVDD = 1.8 V ± 5%; DVDD_I/O = CP_VDD = 3.3 V ± 5% (@ TA = 25°C), DAC_RSET = 3.92 kΩ, CP_RSET = 3.09 kΩ,
DRV_RSET = 4.02 kΩ, unless otherwise noted.
Table 1.

The SNR of a 14-bit ADC was measured with an ENCODE rate of 105 MSPS and an AIN of 170 MHz. The resultant SNR was known to be limited by the jitter of the clock,
not by the noise on the AIN signal. From this SNR value, the jitter affecting the measurement can be back calculated. Driving the PLLREF input buffer. The crystal oscillator section of this input stage performs up to only 30 MHz.
3 The charge pump output compliance range is functionally 0.2 V to (CPVDD − 0.2 V). The value listed here is the compliance range for 5% matching. The input impedance of the CLK1 input is 1500 Ω. However, to provide matching on the clock line, an external 50 Ω load is used.
5 Measured as peak-to-peak between DAC outputs. For a 4.02 kΩ resistor from DRV_RSET to GND.
7 IBIS models for the digital I/O pins available upon request. Assumes a 1 mA load.
LOOP MEASUREMENT CONDITIONS
622 MHz OC-12 Clock
VCO = Sirenza 190-640T
Reference = Wenzel 500-10116 (30.3 MHz)
Loop Filter = 10 kHz BW, 60° Phase Margin
C1 = 170 nF, R1 = 14.4 Ω, C2 = 5.11 µF, R2 = 89.3 Ω,
C3 Omitted
CP_OUT = 4 mA (Scaler = ×8)
÷R = 2, ÷M = 1, ÷N = 1
105 MHz Converter Clock
VCO = Sirenza 190-845T
Reference = Wenzel 500-10116 (30.3 MHz)
Loop Filter = 10 kHz BW, 45° Phase Margin
C1 = 117 nF, R1 = 28 Ω, C2 = 1.6 µF, R2 = 57.1 Ω, C3 = 53.4 nF
CP_OUT = 4 mA (Scaler = ×8)
÷R = 8, ÷M = 1, ÷N = 1
INPUTOUTPUT
04806-0-033
Figure 2. Generic Loop Filter
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprie-
tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AGND
AVDD
AGND
AVDD
IOUT
IOUT
AVDD
AGND
I/O_RESET
RESET
DVDD
DGND
VCP
AGND
OUT0
OUT0
VCML
AGND
CLK1
CLK1
AVDD
AGND
DVDD
DAC_
DRV
SET
AGNDCLK2CLK2RE
FIN
FIN
AGND
SDI/OSCCS
DD_
I/O
NC_
OUT
SYNC_IN/STATUS
I/O_UPDATES1S2
DGND
Figure 3. 48-Lead LFCSP Pin Configuration
NOTE: The exposed paddle on this package is an electrical connection (Pin 49) as well as a thermal enhancement. For the device to
function properly, the paddle must be attached to analog ground.
Table 3. 48-Lead LFCSP Pin Function Descriptions
NOTE: The exposed paddle on this package is an electrical connection (Pin 49) as well as a thermal enhancement. In order for the device
to function properly, the paddle must be attached to analog ground.
TYPICAL PERFORMANCE CHARACTERISTICS
CENTER 10.1MHz5kHz/SPAN 50kHz
REF LVL0dBm
DELTA 1 [T1]–85.94dB–2.10420842kHz
RBWVBWSWT
RF ATT
UNIT
100Hz100Hz25s
20dB
1 AP
–100
Figure 4. AD9540 DAC Performance: 400 MSPS Clock,
10 MHz FOUT, 50 kHz Span
CENTER 10.1MHz100kHz/SPAN 1MHz
REF LVL0dBm
DELTA 1 [T1]–86.03dB–368.73747495kHz
RBWVBWSWT
RF ATT
UNIT
500Hz500Hz20s
20dB
1 AP
–100
Figure 5. AD9540 DAC Performance: 400 MSPS Clock,
10 MHz FOUT, 1 MHz Span
START 0Hz20MHz/STOP 200MHz
REF LVL0dBm
DELTA 1 [T1]–64.54dB100.20040080MHz
RBWVBWSWT
RF ATT
UNIT
10kHz10kHz5s
20dB
1 AP
–100
CENTER 40.1MHz5kHz/SPAN 50kHz
REF LVL0dBm
DELTA 1 [T1]–84.94dB2.10420842kHz
RBWVBWSWT
RF ATT
UNIT
100Hz100Hz25s
20dB
1 AP
–100
Figure 7. AD9540 DAC Performance: 400 MSPS Clock,
40 MHz FOUT, 50 kHz Span
CENTER 40.1MHz100kHz/SPAN 1MHz
REF LVL0dBm
DELTA 1 [T1]–80.17dB–200.40080160kHz
RBWVBWSWT
RF ATT
UNIT
500Hz500Hz20s
20dB
1 AP
–100
Figure 8. AD9540 DAC Performance: 400 MSPS Clock,
40 MHz FOUT, 1 MHz Span
START 0Hz20MHz/STOP 200MHz
REF LVL0dBm
DELTA 1 [T1]–61.61dB100.20040080MHz
RBWVBWSWT
RF ATT
UNIT
10kHz10kHz5s
20dB
1 AP
–100
CENTER 100.1MHz5kHz/SPAN 50kHz
REF LVL0dBm
DELTA 1 [T1]–83.72dB–2.70541082kHz
RBWVBWSWT
RF ATT
UNIT
100Hz100Hz25s
20dB
1 AP
–100
Figure 10. AD9540 DAC Performance: 400 MSPS Clock,
100 MHz FOUT, 50 kHz Span
CENTER 100.1MHz100kHz/SPAN 1kHz
REF LVL0dBm
DELTA 1 [T1]–56.47dB–400.80160321kHz
RBWVBWSWT
RF ATT
UNIT
500Hz500Hz20s
20dB
1 AP
–100
Figure 11. AD9540 DAC Performance: 400 MSPS Clock,
100 MHz FOUT,1 MHz Span
START 0Hz20MHz/STOP 200MHz
REF LVL0dBm
DELTA 1 [T1]–48.71dB–400.80160321kHz
RBWVBWSWT
RF ATT
UNIT
10kHz10kHz5s
20dB
1 AP
–100
Figure 12. AD9540 DAC Performance: 400 MSPS Clock,
100 MHz FOUT, 200 MHz Span
CENTER 159.5MHz5kHz/SPAN 50kHz
REF LVL0dBm
DELTA 1 [T1]–85.98dB–2.90581162kHz
RBWVBWSWT
RF ATT
UNIT
100Hz100Hz25s
20dB
1 AP
–100
Figure 13. AD9540 DAC Performance: 400 MSPS Clock,
160 MHz FOUT, 50 kHz Span
CENTER 159.5MHz100kHz/SPAN 1MHz
REF LVL0dBm
DELTA 1 [T1]–82.83dB262.52505010kHz
RBWVBWSWT
RF ATT
UNIT
500Hz500Hz20s
20dB
1 AP
–100
Figure 14. AD9540 DAC Performance: 400 MSPS Clock,
160 MHz FOUT, 1 MHz Span
START 0Hz20MHz/STOP 200MHz
REF LVL0dBm
DELTA 1 [T1]–54.90dB–78.55711423MHz
RBWVBWSWT
RF ATT
UNIT
10kHz10kHz5s
20dB
1 AP
–100
Figure 15. AD9540 DAC Performance: 400 MSPS Clock,
160 MHz FOUT, 200 MHz Span
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k1M
Figure 16. AD9540 DDS/DAC Residual Phase Noise
400 MHz Clock, 19.7 MHz Output
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k10M1M
Figure 17. AD9540 DDS/DAC Residual Phase Noise
400 MHz Clock, 51.84 MHz Output
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k10M1M
Figure 18. AD9540 DDS/DAC Residual Phase Noise
400 MHz Clock, 105.3 MHz Output
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k10M1M
Figure 19. AD9540 DDS/DAC Residual Phase Noise
400 MHz Clock, 155.52 MHz Output
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k1M2M
Figure 20. RF Divider and CML Driver Residual
Phase Noise (81.92 MHz In, 10.24 MHz Out)
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k1M2M
Figure 21. RF Divider and CML Driver Residual
Phase Noise (157.6 MHz In, 19.7 MHz Out)
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k10M1M
Figure 22. RF Divider and CML Driver Residual
Phase Noise (410.4 MHz In, 51.3 MHz Out)
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k10M1M
Figure 23. RF Divider and CML Driver Residual
Phase Noise (842.4 MHz In, 105.3 MHz Out)
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k10M1M
Figure 24. RF Divider and CML Driver Residual
Phase Noise (983.04 MHz In, 122.88 MHz Out)
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k10M1M
Figure 25. RF Divider and CML Driver Residual
Phase Noise (1240 MHz In, 155 MHz Out)
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k10M1M
Figure 26. RF Divider and CML Driver Residual
Phase Noise (1680 MHz In, 210 MHz Out)
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k10M1M
Figure 27. RF Divider and CML Driver Residual
Phase Noise (1966.08 MHz In, 491.52 MHz Out)

Partno	Mfg	Dc	Qty	Available	Descript
AD9540BCPZ	AD	N/a	13	avai	655 MHz Low Jitter Clock Generator