AD9502AM ,Hybrid RS-170 Video Digitizercharacteristics
increase the tlexibility of the device by making it usable ovcr a
wide range of i ..
AD9502BM ,Hybrid RS-170 Video DigitizerFEATURES
a-Bit Gray Scale Rnsolntion
Screen Resolution m M2 x 512
Phttt-Lottkad Pixel Clock
..
AD9502CM ,Hybrid RS-170 Video DigitizerGENERAL DESCRIPTION
The Analog Devices' AD9502 is a video digitizer which converts
RS-170, NTSC ..
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ADS7853IRTER ,SAR ADC, Dual, 1 MSPS, 14 Bit, Simultaneous Sampling 16-WQFN -40 to 125Features 2 Applications1• 16-, 14-, and 12-Bit, Pin-Compatible Family • Motor Control:Position Meas ..
ADS7861E ,Dual/ 500kHz/ 12-Bit/ 2 2 Channel/ Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTERMAXIMUM RATINGSELECTROSTATICAnalog Inputs to AGND, Any Channel Input ........ –0.3V to (+V + 0.3V)D ..
ADS7861E/2K5G4 ,Dual, 500kHz, 12-Bit, 2+2 Ch, Simultaneous Sampling Analog-To-Digital Converter.TRUTH TABLEM0 M1 A0 TWO-CHANNEL/FOUR-CHANNEL OPERATION DATA ON SERIAL OUTPUTS CHANNELS CONVERTED0 ..
ADS7861EB ,Dual/ 500kHz/ 12-Bit/ 2 2 Channel/ Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTERFEATURESThe ADS7861 is a dual, 12-bit, 500kSPS, Analog-to-Digital* 4 INPUT CHANNELS(A/D) converter ..
ADS7861EG4 ,Dual, 500kHz, 12-Bit, 2+2 Ch, Simultaneous Sampling Analog-To-Digital Converter 24-SSOP -40 to 125FEATURESThe ADS7861 is a dual, 12-bit, 500kSPS, Analog-to-Digital* 4 INPUT CHANNELS(A/D) converter ..
ADS7861IRHBT ,Dual, 500kHz, 12-Bit, 2+2 Ch, Simultaneous Sampling Analog-To-Digital Converter 32-VQFN MAXIMUM RATINGSELECTROSTATICAnalog Inputs to AGND, Any Channel Input ........ –0.3V to (+V + 0.3V)D ..
AD9502AM-AD9502BM-AD9502CM
Hybrid RS-170 Video Digitizer
ANALOG
DEVICES
FEATURES
8-Bit Gray Scale Resolution
Screen Resolution to 512 x 512
Phase-Locked Pixel Clock
TTL Compatible
APPLICATIONS
Machine Vision Systems
Automatic Inspection
Image Processing
GENERAL DESCRIPTION
The Analog Devices' AD9502 is a video digitizer which converts
RS-l70, NTSC, or PAL camera signals directly into 8-bit digital
information and control signals.
All of the analog preprocessing functions needed to move from
the analog world of cameras to the digital world of signal processing
are contained in this single hybrid component.
Included are a video amplifier with dc restoration, sync detector
and separator, phase-locked pixel clock oscillator, and an 8-bit
analog-to-digital converter. The AD9502 is also extremely adapata-
ble by virtue of providing for A" 3dB gain control and offset
variations of 0 to 10 IRE units. These latter characteristics
increase the flexibility of the device by making it useable over a
wide range of input signal amplitudes and set up level outputs
from various types of cameras.
A pixel clock synchronized to the sync portion of the composite
signal is generated by the phase-locked oscillator and the sync
detector/separator circuit. Depending on model number, the
nominal frequency of this clock is 7.31MH2, 9.83MHz, or
12.85MH2. These frequencies correspond to 512 pixels per line
or 384 pixels per line, and aspect ratios of 4:3 or 1:1.
In addition to the pixel clock, AD9502 control signals also include
horizontal and vertical sync pulses. This combination of outputs
allows the user to manage frame memory efficiently; output data
can be precisely located for optimum support of complex digital
signal processing algorithms.
Information furnished by Analog Devices is believed to be accurate
and reliable. However, no responsibility is assumed by Analog Devices
for its use,' nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implica
tion or otherwise under any patent or patent rights of Analog Devices.
Hybrid RS-l Til
Video Digitizer
DttitTAt
PROCBSING
Six models of the AD9502 are available; all units operate over
case temperature ranges of - 25°C to + 85C. Models AD9502AM,
AD9502BM, and AD9502CM with pixel clock frequencies of
7.31MH2, 9.83MHz, and 12.85MHz, respectively, are tested at
+ 25°C. Models AD9502AMB, AD9502BMB, and AD9502CMB,
with the same clock frequencies, are tested at temperatures from
- 25°C to + 85°C. During their manufacturing, these latter
units also receive additional high-reliability processing.
AC I AD9502
SYNC VERT
DETECT0RS t 2 SYNC
YIMING
"lf to l AND
' be I CONTROL
I , HORIZ
I SYNC
I LOCK
I DETECTOR
AMP PHASE PIXEL
OUT DETECTOR VCO CLOCK
LOOP I our
FILTER I
GAIN u DIVIDE '
ADJUST m," l
, PIXEL
INPUY s DIGITALDATA
OFFSET
AD9502 Functional Block Diagram
One Technology Way; P. O. Bax 9106; Norwood, MA 02062-9106
Tel: 617/329-4700 wa: 710/394-6577
West Coast Texas
714/641-9391 214/231-5094
Midwest
312/980-0300
EEC IF I CATI 0 NS (typ1cal@ + KT with nomina1supplies,unle$ utherwise note11)
- 25''C to + 85°C - 25°C to + 85°C 1
Sub AD9502AM/BM/CM' 1 AD9502AMB/BMB/CMB2 1
Parameter" Group Temp Min Typ Max Min Typ Max Units
RESOLUTION I 1
(GS = Gray Scale) 8 8 1 Bits
(FS = FullScale) 0.4 _ 0.4 . 1 o/ofis,
' LSB WEIGHT3 8.4 8.4 mV
0.39 0.39 IRE Units
ACCURACY
J Integral Linearity 4 + 25°C tl 0 t 2.5 11.0 t 2.5 [ % FS
5,6 Full 115 13.0 11.5 13.0 %FS
J Differential Linearity'' 4 + 25°C t 2 t 3.0 1 t 2 1 t 3.0 1 LSB
5,6 Full t2 1 t3.0 1 1 t2 t3.0 LSB
J Initial Offsets 4 + LPC t. 50 1 t 200 t 50 1 t 200 mV
' Offset vs. Temperature 1 I Full 1 1 t 250 1 1 t 250 1 11V/°C
JGain6 1 4 +25%: 1.91 2.8 14 1 1.91 , 2.8 14 NN
' Gain vs. Temperature' 1 Full t 250 1 1 + 250 1 ppm/°C
DYNAMIC CHARACTERISTICS 1 1 1 1 1 i 1
Output Data Rate(PixeiClock)8 1 1 1
J AD9502AM/AMB 1 9, 10, 11 1 Full 7.31 1 7.31 1 MHz
J AD9502BM/BMB 9, 10, 11 1 Full 9.83 9.83 MHz
J AD9502CM/CMB 9, 10, 11 Full 12.85 12.85 1 MHz
' Sampling Jitter + LPC 1 1 l 5 l 5 ns, rms
' Digital Output Delay 1 + 25°C 11 20 30 50 20 30 50 ns
J Horizontal Sync Delay 9 1 + 25°C 1 - 0.4 0.3 0.7 - 0.4 0.3 0.7 115
J Horizontal Sync Delay 10, 11 Full - 0.4 1 0.3 0.7 -0.4 0.3 1 0.7 11.5
JHorizontal Sync Width 1 9 + 25°C 1 4.5 4.8 5.4 1 4.5 4.8 1 5.4 11.5
JHorizontal SyncWidth 10,11 1 Full 1 4.5 4.8 1 5.4 4.5 4.8 1 5.4 Fs
JVcrtical Sync Delay 9 1 + 25°C 1 5.5 6.0 1 6.7 1 5.6 6.0 [ 6.7 11.5
JVertical Sync Delay 10, 11 Full 1 5.5 1 6.0 1 6.7 1 5.6 6.0 6.7 'IS
JSample Delay 9 + 25°C 1 7.9 9.0 9.4 1 7.9 1 9.0 9.4 11.5
JSample Delay 10, 11 Full 7.9 1 9.0 9.4 , 7.9 9.0 I 9.4 ps
VIDEO INPUT 1 i 1 1 1
Signal Type RS-l70 1 RS-l70
J Impedance 1 1 + 25°C 1 67 1 75 1 83 1 67 75 1 83 n
J Impedance 2, 3 I Full 67 75 83 1 67 1 75 83 n
Input level for rated performance 1 I 1 I
#Amplitudc 1 +25°c 1 0.71 [ 1.0 1 1.41 0.71 1 1.0 1.41 Vp-p
#Amplitudc Full 0.71 1 1.0 1.41 1 0.71 1 1.0 1.41 Vp-p
' Dynamic Range 1 1 1 1 1
(back porch ref. to ground) 25°C - 0.83 1 + 1.5 1 - 0.83 + 1.5 V
' Dynamic Range 1 Full -0.83, 1 + 1.5 1 -0.83 1 + 1.5 V
' Bandwidth (3dB) + 25''C 5 7.5 5 7 5 1 MHz
' Bandwidth (3dB) 1 Full 1 5 1 7.5 1 5 7 5 1 MHz
AUXILIARY SYNC INPUT9 1 1 1
Comparator(Pin 10) 1 I 1 1 1 1
Width 1 1 1 1 I 6 l 1 1 6 'M'
Frequency' 1 1 1 15.75 _ 1 15.75 1 kHz
' Loading 1 1 1 <1 1 I <1 1 'I'I‘L Load
Input Current 1 1 1 1
J Irs High (VIN = 2.75V) 1 + 25°C 1 ' 50 1 50 "
J hNLow(Vis = 2.3V) 1 1 +25°c l 50 1 1 50 "
J Logic Level"l'' 1 +25°C +2.75 1 +2.75 V
J Logic Level "o'' l + 25°C 1 + 2.3 I + 2.3 1 V
J IINHigh(V1N = 2.75V) 2, 3 I Full 50 50 1 WA
J 1m Low (VIN = 2.3V) [ 2, 3 1 Full 50 50 WA
J Logic Level "l" 2, 3 I Full + 2.75 + 2.75 v
J Logic Level "o'' 1 2, 3 1 Full + 2 3 1 1 + 2.3 V
-- _1, - - -k
I I - 25°C to + 85''C - 25°C to + 85''C
Sub 1 AD9502AM/BM/CM' ADri02Nrp/BMp(CMB2 V
Parameter"2 Group I Temp 1 Min 1 tn, . Max I Min . Typ 1 Max Units
AUXILIARY SYNCH INPUT9 (Cont.) [
Comparator Enable (Pin 6)
' Loading <1 <1 TTL Load
Input Current
J 1|NLOW(V[N Ter. 0.0V) I 1 I +25°C $400 I 1 1400 wA
J 1.N High (vIN = 5.0V) 1 ( + LPC t 400 ( t 400 "
J Logic Level"l" 1 _ +25°C +3.15 +3.15 V
J Logic Level "o'' I 1 x + 25°C l l + 1.2 + 1.2 V
J Irs High (vIN = 0V) 1 2, 3 ( Full 1 ct: 400 ( t 400 WA
J 1m Low (VIN = 5.0V) l 2, 3 Full 1400 t 400 WA
JLogic Level"1" l 2,3 Full +3.15 +3.15 _ 1 V
J Logic Level "o'' 1 2, 3 l Full [ + 0.9 + 0.9 V
DIGITAL OUTPUTS i (
Coding"' l Comp'. Binary (CBN) Comp. Binary (CBN)
Logic Compatibility I TTL TTL
J Logic Level "I'' I 1 + LPC 1 + 2.4 _ + 2.4 V
J Logic Level "O'' 1 1 + 25°C + 0.5 + 0.5 v
J Logic Level "I" 1 2, 3 1 Full + 2.4 [ + 2.4 V
J Logic Level "o'' 2, 3 1 Full + 0.5 + 0.5 V
J Drive ‘ 1 1 + 25''C 22 22 TIt Loads
J Drive 2, 3 l Full >2 22 TTL Loads
' Time Skew l + 25°C I 10 10 ns
' Time Skew Full ( 10 I 10 ns
POWER REQUIREMENTS ' I I l 1
J +Vs(+12lo +15Vdc) 1 1 +25''C 50 75 l 50 75 mA
J -Vs( - 12to -15Vdc) 1 + 25°C , 30 45 30 45 mA
J +Vcc(+5Vdc ct:5%) 1 +25°C 110 150 110 150 mA
J Power Dissipation 1 + 25°C 1 1.75 2.55 1.75 2.55 W
J + Vs( + 12 to + 15V dc) 5 2,3 Full l 50 75 50 75 mA
J --Vs(-12to -15Vdc) I 2,3 l Full _ 30 ( 45 30 45 mA
JVCC(+5Vdc15°/o) 2,3 l Full 1 110 150 ( l 110 150 mA
J Power Dissipation 2, 3 1 Full 1 1.75 1 2.55 _ 1.75 2.55 w
THERMAL RESISTANCE r , ' " F ' " .
' Junction to Air (0ia) 1 18 l 18 °C/W
' Junction to Case (Oic) 4 4 "C/W
PRICES -(1-24) t 289 ' 508 1 '
J l00% tested (see Notes I and 2).
. Specirscation guaranteed by design; not tested.
'AD9502AM/BM/CM specifications preceded by a check (c0 are tested "
+ 25°C ambient temperature; performance is guaranteed over use
temperature mg: of - 25°C to 85'C.
2AD9502AMB/BMBCMB specifications preceded by a check (J) Me tested "
- 25'C case, + 25'C mbicnl, Ind + 85'C case temperatures unless otherwise
indicated (See Explanation of Group A Military Subgroups).
’lmemnl ADC reference = 2.15V = 100 IRE units.
'Specifications shown guaranteed over temperature on AD9502AMB/BMBCMB.
'otrset is difference betwcen voltage reference u OFFSET ADJUST (Pin 32) and
the dc restored voltage value ll AMP OUT (Pin 12). Offset is adjustable with
extemal potentiometer to accommodate 0 to 10 IRE units of setup level.
'Adjustable with external potentiometer. Compensates for MB variation from
nominal IV tFP cumposite signal.
'Gain tempco is equal to the voltage reference u OFFSET ADJUST (Pin 32).
'Pixel clock stability is directly related lo 15.75kHz input clock stability.
Frequency of pixel clock is set " factory for desired aspect ratio and
scmn resolution; consult Table l for available frequency selections.
“Auxiliary sync can be driven from TTL source and can be composite or
horizontal only. In horizontal. no output provided ll VERTICAL SYNC (Pin 2).
'oReference black level output code = Illl 1lll; reference white - 0000 0000.
EXPLANATION OF GROUP A MILITARY SUBGROUPS
1 - Static tests at + 25°C. (10% PDA calculated
against Subgroup 1 for high-rel versions.)
Subgroup
Subgroup 2 - Static tests at max rated operating temp.
Subgroup 3 - Static tests at min rated operating temp.
Subgroup 4 - Dynamic tests at + 25°C.
Subgroup 5 - Dynamic tests at max rated operating temp.
Subgroup 6 - Dynamic tests at min rated operating temp.
Subgroup 7 - Functional tests at + 25°C.
Subgroup 8 - Functional tests at max and min rated
operating temperatures.
Subgroup 9 - Switching tests at + 25''C.
Subgroup 10 - Switching tests at max rated operating temp.
Subgroup ll - Switching tests at min rated operating temp.
Subgroup 12 - Periodically sample tested.
ABSOLUTE MAXIMUM RATINGS
Logic Supply Voltage (tVs) ..............
Operating Temperature Range (Case)
AD9502AM/BM/CM ........... - LPC to + 85''C
AD902AMB/BMB/CMB ......... - 25°C to + 85°C
Junction Temperature ................. + 165°C
Storage Temperature Range ......... - 65°C to + 150°C
Lead Soldering Temperature (Soldering lOsec) . . . . +300°C
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
lllll HHHHHUUU
010° t2.54l tD BEAD (ON BOTTOM) AND
" PLACES -..--- DOT (ON TOP) DENOTE PIN ,
0,19 (4.83,
0.24 (8.03) ,
0.125 13 175)
-o-o-qt-o-q-tt-.--o-tp-o -0-0-q-tF-. o-et-tr-tt
1.145 (29.083) MAX—c—
0.900 (22.860) 2 0.020 —.—1
"r''-''-''-''-''-''-''-''-''-''-'-''-''-''-'"-'"-''-','
L_isoo [48160) 2 0.006
2145(54183lMAX
012511175)...
PIN DESIGNATIONS
PIN FUNCTION PIN FUNCTION
1 DO NOT CONNECT' 40 CASE GROUND
2 VERTICAL SYNC 39 GROUND
3 CASE GROUND 38 HORIZONTAL SYNC
4 GROUND 37 + SV de
5 + SV dc 36 GROUND
6 coMP_tRAToR-Et"ihTiLii' 35 + SV de
7 DO NOT CONNECT. M DO NOT CONNECT'
a + 5 v de 33 GROUND
9 VIDEO INPUT 32 OFFSET ADJUST
IO COMPARATORINPUT 31 em (MSB)
It DO NOT CONNECT. 30 BITZ
12 AMPLIFIER OUTPUT 29 BIT3
" GAIN ADJUST 28 BIT4
14 +V(+12Vto +15v1 27 BITS
15 -Vt-12Vto-15Vl 26 arm
" GROUND 25 BIT 7
" GROUND 24 BIT8 (LSB)
18 Do NOT CONNECT. 23 + SV de (ADC)
19 + SV de NCOI 22 ANALOG GROUND
20 PIXEL CLOCK OUT 21 PIXELCLOCK IN
'THESE PINS ARE USED FOR FACTORY TESTING AND
SHOULD NOT BE USED AS TIE POINTS OR CONNECTED
INTO EXTERNAL CIRCUITS.
THEORY OF OPERATION
The use of analog-to-digital converters (ADCs) for digitizing
Gray Scale picture information in a standard RS-l70 composite
signal is widespread throughout the video industry.
But digitizing only the picture information is not sufficient.
If a complete video frame is to be stored in memory (in a technique
generally called "frame grabbing"), the composite signal from
the camera must have additional processing steps applied. Among
others, these include dc restoration; sync detection and separation;
and synchronization to a pixel clock, often "slaved" to a master
system clock. Analog circuits for achieving these operations
must be combined, and interfaced to digital logic for subsequent
processing of the signal.
The principal functions of "front end" video processors which
receive the camera signal are to sychronize the frame memory
and digitize each pixel (smallest controllable picture element) of
video information.
Performing these functions is common in the video industry.
But the method of accomplishing them is eased considerably
with the AD9502 RS-l70 Video Digitizer.
Refer to the AD9502 Functional Block Diagram.
The unit consists of four major parts: a phase-locked loop (PLL),
dc restoration circuits, sync detector/timing circuits, and the
The PLL comprises a phase detector, loop filter/amplifier, voltage-
controlled oscillator (VCO), and a digital divider; monolithic
ICs are used for each section. The frequency of the pixel clock
output (at Pin 20) is an integer multiple of the horizontal line
frequency and is phase locked to the sync pulses of the incoming
composite signal.
A video amplifier and the sample/hold (S/H) establish a feedback
loop for dc restoration of the video input. Sync detection and
timing result from the combined actions of the blocks marked
AC, Lock Detector, Timing & Control, and the PLL.
Refer to Figure l, the AD9502 Timing Diagram.
As shown, the leading edge of the sync tip pulse serves as the
reference point for timing the actions of the AD9502. As part of
the composite signal, these pulses are amplified and inverted by
the video amplifier and drive the phase-locked loop within the
unit, but only after the pulses are detected and conditioned.
The PLL is unlocked during the power-up phase, or if the
input signal is missing. When it is, the comparator and all timing
pulses are disabled, creating an ac-coupled signal path for syn-
chronizing the PLL.
After the lock indicator detects a lock condition, the dc comparator
is enabled and the ac-coupled path is disabled. The threshold of
the comparator is set at slightly more than half the amplitude of
the sync pulse height in the dc-restored RS-l70 signal.
When the PLL is operating, the phase detector which is part of
the loop generates an error voltage proportional to the timing
error between the PLL's input signal (H Sync) and the VCO's
divided-by-N output. If a difference exists between the two, the
loop filter/amplifier shifts the VCO control voltage in the proper
direction to minimize the error. The result of these actions is
that the pixel clock output of the VCO is N times the horizontal
frequency of the input to the AD9502.
The integer of the Divide by N circuit is set at the factory for
the aspect ratio and resolution to be used by the customer and
causes the phase detector to operate at a constant frequency.
(Refer to ORDERING INFORMATION and Table I for details
on specifying the desired frequency of the VCO).
To insure a stable pixel clock, the loop filter must block feed-
through from the phase detector and noise. If it does not, the
VCO will be unable to provide the required phase-coherent
clock.
To some degree, clock stability and loop stability are conflicting
requirements. Clock stability can be affected by noise and feed-
