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AD9501JN-AD9501JP
Digitally Programmable Delay Generator
FUNCTIONAL BLOCK DIAGRAMREV.A
Digitally Programmable
Delay Generator
FEATURES
Single +5 V Supply
TTL and CMOS Compatible
10 ps Delay Resolution
2.5 ns to 10 ms Full-Scale Range
Maximum Trigger Rate 50 MHz
MIL-STD-883-Compliant Versions Available
APPLICATIONS
Disk Drive Deskewing
Data Communications
Test Equipment
Radar I & Q Matching
GENERAL DESCRIPTIONThe AD9501 is a digitally programmable delay generator which
provides programmed time delays of an input pulse. Operating
from a single +5 V supply, the AD9501 is TTL- or CMOS-
compatible, and is capable of providing accurate timing adjust-
ments with resolutions as low as 10 ps. Its accuracy and
programmability make it ideal for use in data deskewing and
pulse delay applications, as well as clock timing adjustments.
Full-scale delay range is set by the combination of an external
resistor and capacitor, and can range from 2.5 ns to 10 μs for a
single AD9501. An eight-bit digital word selects a time delay
within the full-scale range. When triggered by the rising edge of
an input pulse, the output of the AD9501 will be delayed by an
amount equal to the selected time delay (tD) plus an inherent
propagation delay (tPD).
The AD9501 is available for a commercial temperature range of
0°C to +70°C in a 20-pin plastic DIP, 20-pin ceramic DIP, and
a 20-lead plastic leaded chip carrier (PLCC). Devices fully
compliant to MIL-STD-883 are available in ceramic DIPs.
Refer to the Analog Devices Military Products Databook or current
AD9501/883B data sheet for detailed specifications.
AD9501–SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS1Positive Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V
Digital Input Voltage Range . . . . . . . . . . . . . . .–0.5 V to +VS
Trigger/Reset Input Volt. Range . . . . . . . . . . . .–0.5 V to +VS
Minimum RSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Ω
Digital Output Current (Sourcing) . . . . . . . . . . . . . . .10 mA
Digital Output Current (Sinking) . . . . . . . . . . . . . . . .50 mA
Operating Temperature Range
AD9501JN/JP/JQ . . . . . . . . . . . . . . . . . . . . . .0°C to +70°C
AD9501SQ . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature2 . . . . . . . . . . . . . . . . . . . . . . .+175°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . .+300°C
ELECTRICAL CHARACTERISTICS
[+VS = +5 V; CEXT = Open; RSET = 3090 Ω (Full-Scale Range =100 ns); Pin 8 grounded; and
device output connected to Pin 4 RESET input unless otherwise noted]
*N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip.
NOTESAbsolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability
is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.Typical thermal impedances: 20-lead plastic leaded chip carrier θJA= 73°C/W; θJC= 29°C/W. 20-pin ceramic DIP θJA= 65°C/W; θJC= 20°C/W. 20-pin plastic DIP
θJA= 65°C/W; θJC= 26°C/W.Digital data inputs must remain stable for the specified time prior to the positive transition of the LATCH signal.Digital data inputs must remain stable for the specified time after the positive transition of the LATCH signal.Programmed delay (tD) = 0 ns. Maximum self-resetting trigger rate is limited to 6.9 MHz with 100 ns programmed delay. If tD= 0 ns and external RESET signal is
used, maximum trigger rate is 23 MHz.Programmed delay (tD) = 0 ns. In operation, any programmed delays are in addition to the minimum propagation delay (tPD).Programmed delay (tD) = 0 ns. [Minimum propagation delay (tPD)].Measured from 50% transition point of the RESET signal input to the 50% transition point of the falling edge of the output.Minimum time from the falling edge of RESET to the triggering input to insure valid output pulse, using external RESET pulse.Minimum time from triggering event to rising edge of RESET to insure valid output event, using external RESET pulse. Extends to 125 ns when programmed delay
is 100 ns.When self-resetting with a full-scale programmed delay.Measured from +0.4 V to +2.4 V; source = 1 mA; sink = 4 mA.Measured from the data input to the time when the AD9501 becomes 8-bit accurate, after a full-scale change in the program delay data word.Measured from the RESET input to the time when the AD9501 becomes 8-bit accurate, after a full-scale programmed delay.Supply voltage should remain stable within ±5% for normal operation.Measured at +VS = +5.0 V ± 5%; specification shown is for worst case.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level–100% production tested.–100% production tested at +25°C, and sample tested at specified
temperatures.
III–Sample tested only.–Parameter is guaranteed by design and characterization testing.–Parameter is a typical value only.–All devices are 100% production tested at +25°C. 100% production
tested at temperature extremes for extended temperature devices;
sample tested at temperature extremes for commercial/industrial
devices.
ORDERING GUIDE
DIE LAYOUT AND MECHANICAL INFORMATIONMECHANICAL INFORMATIONDie Dimensions . . . . . . . . . . . . . . . . . .89 × 153 × 15 (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .Ground
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Oxynitride
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Gold Eutectic
Bond Wire . . . . . . . .1.25 mil, Aluminum; Ultrasonic Bonding
or 1 mil, Gold; Gold Ball Bonding
AD9501
AD9501 PIN DESCRIPTIONSAD9501 Equivalent Circuits
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9501 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Figure 1, the AD9501 Internal Timing diagram, illustrates in
detail how the delay is determined. Minimum Delay (tPD) is the
sum of Trigger Circuit delay, Ramp Generator delay, and
Comparator delay.
The Trigger Circuit delay and Comparator delay are fixed;
Ramp Generator delay is a variable affected by the rate of
change of the linear ramp and (to a lesser degree) the value of
the offset voltage described below.
Maximum Delay is the sum of Minimum Delay (tPD) and Full-
Scale Program Delay (tDFS).
Ramp Generator delay is the time required for the ramp to slew
from its reset voltage to the most positive DAC reference
voltage (00H). The difference in these two voltages is nominally
18 mV (with OFFSET ADJUST open) or 34 mV (OFFSET
ADJUST grounded).
THEORY OF OPERATIONThe AD9501 is a digitally programmable delay device. Its
function is to provide a precise incremental delay between input
and output, proportional to an 8-bit digital word applied to its
delay control port. Incremental delay resolution is 10 ps at the
minimum full-scale range of 2.5 ns. Digital delay data inputs,
latch, trigger and reset are all TTL/CMOS compatible. Output
is TTL-compatible.
Refer to the block diagram of the AD9501.
Inside the unit, there are three main subcircuits: a linear ramp
generator, an 8-bit digital-to-analog converter (DAC) and a
voltage comparator. The rising edge of the input (TRIGGER)
pulse initiates the delay cycle by triggering the ramp generator.
The voltage comparator monitors the ramp voltage and switches
the delayed output (Pin 10) HIGH when the ramp voltage
crosses the threshold set by the DAC output voltage. The DAC
threshold voltage is programmed by the user with digital inputs.
Figure 1.AD9501 Internal Timing
AD9501Offset between the two levels is necessary for three reasons.
First, offset allows the ramp to reset and settle without re-
entering the voltage range of the DAC. Second, the DAC may
overshoot as it switches to its most positive value (00H); this
could lead to false output pulses if there were no offset between
the ramp reset voltage and the upper reference. Overshoot on
the ramp could also lead to false outputs without the offset.
Finally, the ramp is slightly nonlinear for a short interval when it
is first started; the offset shifts the most positive DAC level
below this nonlinear region and maintains ramp linearity for
short programmed delay settings.
Pin 8 of the AD9501 is called OFFSET ADJUST (see block
diagram) and allows the user to control the amount of offset
separating the initial ramp voltage and the most positive DAC
reference. This, in turn, causes the Ramp Generator delay to
vary.
Figure 2 shows differences in timing which occur if OFFSET
ADJUST Pin 8 is grounded or open. The variable Ramp
Generator delay is the major component of the three
components which comprise Minimum Delay (tPD) and,
therefore, is affected by the connection to Pin 8.
It is preferable to ground Pin 8 because the smaller offset that
results from leaving it open increases the possibility of false out-
put pulses. When grounding the pin, it should be grounded
directly or connected to ground through a resistor or potentiom-
eter with a value of 10 kΩ or less.
Caution is urged when using resistance in series with Pin 8. The
possibility of false output pulses, as discussed above, is in-
creased under these circumstances. Using resistance in series
with Pin 8 is recommended only when matching minimum de-
lays between two or more AD9501 devices; it is not recom-
mended if using a single AD9501. Changing the resistance
between Pin 8 and ground from zero to 10 kΩ varies the Ramp
Generator Delay by approximately 35%.
The Full-Scale Delay Range (tDFS) can be calculated from the
equation: (tDFS)=RSET×(CEXT+8.5pF)×3.84
Whenever Full-Scale Delay Range is 326 ns or less, CEXT should
be left open. Additional capacitance and/or larger values of RSET
increase the Linear Ramp Settling Time, which reduces the
maximum trigger rate. When delays longer than 326 ns are
required, up to 500 pF can be connected from CEXT to +VS.
RSET should be selected in the range from 50 Ω to 10 kΩ. Graph
1 shows typical Full-Scale Delay Ranges for various values of
RSET and CEXT.
Figure 2.AD9501 Minimum Delay (tPD) vs. Full-Scale Delay Range (tDFS)
