AD9500TQ ,Digitally Programmable Delay GeneratorGENERAL DESCRIPTIONThe AD9500 is a digitally programmable delay generator, whichPIN CONFIGURATIONSp ..
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AD9501JP ,Digitally Programmable Delay GeneratorSPECIFICATIONS1ABSOLUTE MAXIMUM RATINGS Operating Temperature RangePositive Supply Voltage . . . . ..
AD9502AM ,Hybrid RS-170 Video Digitizercharacteristics
increase the tlexibility of the device by making it usable ovcr a
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a-Bit Gray Scale Rnsolntion
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..
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The Analog Devices' AD9502 is a video digitizer which converts
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ADS7852Y/250 ,12-Bit, 8-Channel, Parallel Output Analog-to-Digital Converterfeatures offered by the ADS7852. The ADS7852APPLICATIONSis available in an TQFP-32 package and is f ..
ADS7852Y/250 ,12-Bit, 8-Channel, Parallel Output Analog-to-Digital ConverterMAXIMUM RATINGSELECTROSTATICAnalog Inputs to AGND, Any Channel Input ..... –0.3V to (V + 0.3V)DDISC ..
ADS7852Y/250 ,12-Bit, 8-Channel, Parallel Output Analog-to-Digital ConverterMaximum Ratings” maymay be more susceptible to damage because very smallcause permanent damage to t ..
ADS7852Y/250 ,12-Bit, 8-Channel, Parallel Output Analog-to-Digital ConverterELECTRICAL CHARACTERISTICS At T = –40°C to +85°C, f = 500kHz, f = 16 • f , and V = +5V, using inter ..
ADS7852YB ,Brown Corporation - 12-Bit, 8-Channel, Parallel Output ANALOG-TO-DIGITAL CONVERTER
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AD9500BP-AD9500BQ-AD9500TQ
Digitally Programmable Delay Generator
REV.D
Digitally Programmable
Delay Generator
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe AD9500 is a digitally programmable delay generator, which
provides programmed delays, selected through an 8-bit digital
code, in resolutions as small as 10 ps. The AD9500 is con-
structed in a high performance bipolar process, designed to
provide high speed operation for both digital and analog circuits.
The AD9500 employs differential TRIGGER and RESET
inputs which are designed primarily for ECL signal levels but
function with analog and TTL input levels. An onboard ECL
reference midpoint allows both of the inputs to be driven by
either single ended or differential ECL circuits. The AD9500
output is a complementary ECL stage, which also provides a parallel output circuit to facilitate reset timing implementations.
The digital control data is passed to the AD9500 through a
transparent latch controlled by the LATCH ENABLE signal. In
the transparent mode, the internal DAC of the AD9500 will
attempt to follow changes at the inputs. The LATCH ENABLE
is otherwise used to strobe the digital data into the AD9500
latches.
The AD9500 is available as an industrial temperature range
device, –25°C to +85°C, and as an extended temperature range
device, –55°C to +125°C. Both grades are packaged in a 24-lead
cerdip (0.3" package width), as well as 28-leaded and leadless
surface mount packages. The AD9500 is available in versions
compliant with MIL-STD-883. Refer to the Analog Devices
Military Products Databook or current AD9500/883B data
sheet for detailed specifications.
FEATURES
10 ps Delay Resolution
2.5 ns to 10 ms Full-Scale Range
Fully Differential Inputs
Separate Trigger and Reset Inputs
Low Power Dissipation—310 mW
MIL-STD-883 Compliant Versions Available
APPLICATIONS
ATE
Pulse Deskewing
Arbitrary Waveform Generators
High Stability Timing Source
Multiple Phase Clock Generators
PIN CONFIGURATIONS
ELECTRICAL CHARACTERISTICS2(Supply Voltages +VS = +5.0 V, VS = –5.2 V; CEXT = 0 pF; RSET = 500 V unless otherwise noted)DIGITAL INPUT
DYNAMIC PERFORMANCE
ABSOLUTE MAXIMUM RATINGS1Positive Supply Voltage (+VS) . . . . . . . . . . . . . . . . . . . . .+7 V
Negative Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . .–7 V
ECL COMMON to Ground Differential . . . .–2.0 V to +5.0 V
Digital Input Voltage Range . . . . . . . . . . . . .–3.5 V to +5.0 V
Trigger/Reset Input Voltage Range . . . . . . . . . . . . . . .–5.0 V
Trigger/Reset Differential Voltage . . . . . . . . . . . . . . . . . .5.0 V
Minimum RSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 W
Digital Output Current (Q and Q) . . . . . . . . . . . . . . .30 mA
Digital Output Current ( . . . . . . . . . . . . . . . . . . . .2 mA
Offset Adjust Current (Sinking) . . . . . . . . . . . . . . . . . . .4 mA
Operating Temperature Range
AD9500BP/BQ . . . . . . . . . . . . . . . . . . . . .–25°C to +85°C
AD9500TE/TQ . . . . . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . .+300°C
AD9500–SPECIFICATIONS
DIGITAL OUTPUTS
POWER SUPPLY
NOTESAbsolute maximum ratings are limiting values, to be applied individually, and beyond which serviceability of the circuit may be impaired. Functional operability under
any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Typical thermal impedance
24-Lead CerdipqJA = 56°C/W; qJC = 16°C/W
28-Leadless PLCC (Plastic)qJA = 60°C/W; qJC = 22°C/W
28-Leaded Ceramic LCCqJA = 69°C/W; qJC = 25°C/WRSET = 10 kW (Full-scale delay = 100 ns).The digital data inputs must remain stable for the specified time prior to the LATCH ENABLE signal.The digital data inputs must remain stable for the specified time after the LATCH ENABLE signal.The TRIGGER and RESET inputs are differential and must be driven relative to one another. Both of these inputs are ECL compatible, but can also be used with
TTL logic families in a limited fashion.Outputs terminated through 50 W resistors to –2.0 V.Program Delay = 0.0 ps (Digital Data = 00H). In Operation, any programmed delays are in addition to the Minimum Propagation Delay.Change in total delay through AD9500, exclusive of changes in minimum propagation delay tPD.Measured from the 50% transition point of the reset signal input, to the 50% transition point of the resetting output.Minimum time from falling edge of RESET to triggering input, to ensure a valid output event.Minimum time from triggering event to rising edge of RESET, to ensure a valid output event.Measured from the LATCH ENABLE input to the point when the AD9500 becomes 8-bit accurate again, after a full-scale change in the programmed delay.Standard 10K and 10KH ECL families operate with a 1.1 mV/°C drift by design.Supply voltages should remain stable within –5% for normal operation.Measured at –5% of –VS and +VS.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELSTest Level–100% production tested.–100% production tested at +25°C, and sample tested at
specified temperatures.
III–Periodically sample tested.–Parameter is guaranteed by design and characterization
testing.–Parameter is a typical value only.–All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature ex-
tremes for commercial/industrial devices.
ORDERING GUIDEAD9500BQ
AD9500TE
AD9500TQ
AD9500
PIN FUNCTION DESCRIPTIONSD7 (MSB)
ECLREF
OFFSET ADJUST
TRIGGER
RESET
D0 (LSB)
Figure 1.System Timing Diagram
MECHANICAL INFORMATIONDie Dimensions . . . . . . . . . . . . . . .104 3 103 3 18 (max) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . .4 3 4 (min) mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Oxynitride
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Gold Eutectic
Bond Wire . . . . . . . .1.25 mil, Aluminum; Ultrasonic Bonding
or 1 mil, Gold; Gold Ball Bonding
DIE LAYOUT
AD9500Figure 2.Input/Output Circuits
