AD9483KS-100-AD9483KS-140 Fast Delivery |IC PHOENIX CO.,LIMITED

AD9483KS-100 ,Triple 8-Bit, 140 MSPS A/D ConverterSPECIFICATIONSTest AD9483KS-140 AD9483KS-100Parameter Temperature Level Min Typ Max Min Typ Max Uni ..
AD9483KS-140 ,Triple 8-Bit, 140 MSPS A/D ConverterGENERAL DESCRIPTION mode interleaves ADC data through two 8-bit channels at one-The AD9483 is a tri ..
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AD9500BQ ,Digitally Programmable Delay Generatorspecifications.+V 10 –V20SSTRIGGER11 19 ECL COMMON12 13 16 17 1814 15NC = NO CONNECTREV. DInformati ..
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ADS7846IRGVT ,4-wire Touch Screen Controller(1)ABSOLUTE
ADS7846N ,Touch Screen ControllerELECTRICAL CHARACTERISTICSAt T = –40°C to +85°C, +V = +2.7V, V = 2.5V internal voltage, f = 125kHz, ..
ADS7846N . ,Touch Screen Controller.ADS78462SBAS125H
ADS7846N/2K5G4 ,4-wire Touch Screen ControllerELECTRICAL CHARACTERISTICSAt T = –40°C to +85°C, +V = +2.7V, V = 2.5V internal voltage, f = 125kHz, ..
ADS7846NG4 ,4-wire Touch Screen Controller 16-TSSOP -40 to 85FEATURES* SAME PINOUT AS ADS7843The ADS7846 is a next-generation version to the industrystandard AD ..
ADS7852 ,12-Bit, 8-Channel, Parallel Output ANALOG-TO-DIGITAL CONVERTERfeatures both a nap mode and a sleep mode, further* ±1LSB: INL, DNL reducing the power consumption ..

AD9483KS-100-AD9483KS-140
Triple 8-Bit, 140 MSPS A/D Converter
REV.Ariple 8-Bit, 140 MSPS/D Converter
FUNCTIONAL BLOCK DIAGRAM
FEATURES
140 MSPS Guaranteed Conversion Rate
100 MSPS Low Cost Version Available
330 MHz Analog Bandwidth
1 V p-p Analog Input Range
Internal +2.5 V Reference
Differential or Single-Ended Clock Input
3.3 V/5.0 V Three-State CMOS Outputs
Single or Demultiplexed Output Ports
Data Clock Output Provided
Low Power: 1.0 W Typical
+5 V Converter Power Supply
APPLICATIONS
RGB Graphics Processing
High Resolution Video
LCD Monitors and Projectors
Micromirror Projectors
Plasma Display Panels
Scan Converters
GENERAL DESCRIPTION
The AD9483 is a triple 8-bit monolithic analog-to-digital
converter optimized for digitizing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode
rate capability and full-power analog bandwidth of 330 MHz
supports display resolutions of up to 1280 · 1024 at 75 Hz with
sufficient input bandwidth to accurately acquire and digitize
each pixel.
To minimize system cost and power dissipation, the AD9483
includes an internal +2.5 V reference and track-and-hold cir-
cuit. The user provides only a +5 V power supply and an en-
code clock. No external reference or driver components are
required for many applications. The digital outputs are three-
state CMOS outputs. Separate output power supply pins sup-
port interfacing with 3.3 V or 5 V logic.
The AD9483’s encode input interfaces directly to TTL, CMOS,
or positive-ECL logic and will operate with single-ended or
differential inputs. The user may select dual channel or single
channel digital outputs. The Dual Channel (demultiplexed)
mode interleaves ADC data through two 8-bit channels at one-
half the clock rate. Operation in Dual Channel mode reduces
the speed and cost of external digital interfaces while allowing
the ADCs to be clocked to the full 140 MSPS conversion rate.
In the Single Channel mode, all data is piped at the full clock
rate to the Channel A outputs and the ADCs conversion rate is
limited to 100 MSPS. A data clock output is provided at the
Channel A output data rate for both Dual-Channel or Single-
Channel output modes.
Fabricated in an advanced BiCMOS process, the AD9483 is
provided in a space-saving 100-lead MQFP surface mount plas-
tic package (S-100) and is specified over the 0°C to +85°C
temperature range.
AD9483–SPECIFICATIONS
(VCC = +5 V, VDD = +3.3 V, external reference, ENCODE = maximum conversion rate
differential PECL)
AD9483
NOTESGain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference).tV and tPDF are measured from the threshold crossing of the ENCODE input to valid TTL levels at the digital outputs. The output ac load during test is 5 pF.tCV and tCPD are measured from the threshold crossing of the ENCODE input to valid TTL levels at the digital outputs. The output ac load during test is 20 pF.Measured under the following conditions: analog input is –1 dBFS at 19.7 MHz.SNR/harmonics based on an analog input voltage of –1.0 dBFS referenced to a 1.024 V full-scale input range.
Typical thermal impedance for the S-100 (MQFP) 100-lead package: qJC = 10°C/W, qCA = 17°C/W, qJA = 27°C/W.
Specifications subject to change without notice.
AD9483
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9483 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6 V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .VCC to 0.0 V
VREF IN, VREF OUT . . . . . . . . . . . . . . . . . . . .VCC to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .VCC to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . .20 mA
Operating Temperature . . . . . . . . . . . . . . . . . . .0°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . .+175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . .+150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
EXPLANATION OF TEST LEVELS
Test Level–100% production tested.–100% production tested at +25°C and sample tested at
specified temperatures.
III–Periodically sample tested.–Parameter is guaranteed by design and characterization
testing.–Parameter is a typical value only.–100% production tested at +25°C; guaranteed by design
and characterization testing.
Table I.Output Coding
ORDERING GUIDE
AD9483KS-140
PIN FUNCTION DESCRIPTIONS
79, 82, 83, 93, 94, 98, 99
52–59
AD9483
PIN CONFIGURATION
Plastic Thin Quad Flatpack (S-100B)
GNDV
REF OUTGNDGNDV
B REF INB AINB AING REF ING AING AINR REF INR AINR AINV
GND
GND
GND
GND
VCC
GND
GND
I/P
OMS
GND
VDD
GND
DRA0
DRA1
DRA2
DRA3
DRA4
DRA5
DRA6
DRA7
VDD
GND
DRB0
DRB1
DRB2
DRB3
DRB4
DRB5
DRB6
DRB7
VDD
GND
ENCODE
ENCODE
GND
GND
DCO
DCO
GND
VDD
DBB7
DBB6
DBB5
DBB4
DBB3
DBB2
DBB1
DBB0
GND
VDD
DBA7
DBA6
DBA5
DBA4
DBA3
DBA2
DBA1
DBA0
GND
NC = NO CONNECT
TIMING
Figure 1.Timing—Single Channel Mode
SAMPLE N–2
ENCODE
ENCODE
CLKOUT
CLKOUT
SAMPLE N+1
SAMPLE NSAMPLE N+3SAMPLE N+4SAMPLE N–1
PORT B
D7–D0
PORT A
D7–D0
PORT B
D7–D0
PORT A
D7–D0
AIN
SAMPLE N+5
SAMPLE N+6
SAMPLE N+2
Figure 2.Timing—Dual Channel Mode
AD9483
EQUIVALENT CIRCUITS
VCC
AINAIN
Figure 3.Equivalent Analog Input Circuit
VCC
VREF IN
Figure 4.Equivalent Reference Input Circuit
VCC
ENCODEENCODE
Figure 5.Equivalent Encode and Data Select Input Circuit
VCC
DEMUX
Figure 6.Equivalent DEMUX Input Circuit
Figure 7.Equivalent Digital Output Circuit
VCC
VREF
OUT
Figure 8.Equivalent Reference Output Circuit
Figure 9.Equivalent Digital Input Circuit
fIN – MHz
100200350
Figure 10.Frequency Response: fS = 140 MSPS
fIN – MHz
–10501002002502.57.52575150
Figure 11.Crosstalk vs. fIN: fS = 140 MSPS
TEMPERATURE – 8C
–802030405060708090
Figure 12.Crosstalk vs. Temperature: fIN = 70 MHz

TEMPERATURE – 8C
VOLTS
Figure 13.Reference Voltage vs. Temperature
VCC – V
REF
2.1
Figure 14.Reference Voltage vs. Power Supply Voltage
Figure 15.Reference Voltage vs. Reference Load
AD9483
–Typical Performance Characteristics
LOAD CAPACITANCE – pF
4.5
Figure 16.Clock Output Delay vs. Capacitance
VDD – V3.3
3.63.94.24.54.7555.255.5
Figure 17.Output Delay vs. VDD
TEMPERATURE – 8C
8.5
Figure 18. Output Delay vs Temperature
IOH – mA
VOLTS2101620
4.58121418
Figure 19. Output Voltage HIGH vs. Output Current
IOL
VOLTS5101520
1.8
Figure 20. Output Voltage LOW vs. Output Current
VDD – V
1003.544.555.5
Figure 21. Output Power vs. VDD, CLOAD = 10 pF
fS – MSPS60140180
100
Figure 22.SNR vs. fS: fIN = 19.7 MHz
Figure 23.Harmonic Distortion vs. fS: fIN = 19.7 MHz
Figure 24.Spectrum: fS = 140 MSPS, fIN = 19.57 MHz
fS – MSPS1401806080100120160200
Figure 25.SNR vs fS: fIN = 71.7 MHz
Figure 26.Harmonic Distortion vs fS: fIN = 71.7 MHz
Figure 27.Spectrum: fS = 140 MSPS, fIN = 70.3 MHz
AD9483
25%
28%
31%
38%
45%
52%
59%
66%
ENCODE DUTY CYCLE – %
ENCODE PULSEWIDTH – ns
73%
76%
5.4
Figure 28.SNR vs. Clock Pulsewidth (tPWH): fS = 140 MSPS
fIN – MHz
100150200250
Figure 29.SNR vs. fIN: fS = 140 MSPS
TEMPERATURE – 8C
–40406080100
Figure 30.3rd Harmonic vs. Temperature, fS = 140 MSPS

TEMPERATURE – 8C
–25406080100
Figure 31.SNR vs. Temperature, fS = 140 MSPS

TEMPERATURE – 8C
–70
Figure 32.2nd Harmonic vs. Temperature, fS = 140 MSPS
Figure 33.Two Tone Intermodulation Distortion
APPLICATION NOTES
Theory of Operation
The AD9483 combines Analog Devices’ patented MagAmp bit-
per-stage architecture with flash converter technology to create a
high performance, low power ADC. For ease of use the part
includes an on board reference and input logic that accepts
TTL, CMOS or PECL levels.
Each of the three analog input signals is buffered by a high speed
differential amplifier and applied to a track-and-hold (T/H)
circuit. This T/H captures the value of the input at the sampling
instant and maintains it for the duration of the conversion. The
sampling and conversion process is initiated by a rising edge on
the ENCODE input. Once the signal is captured by the T/H,
the four Most Significant Bits (MSBs) are sequentially encoded
by the MagAmp string. The residue signal is then encoded by a
flash comparator string to generate the four Least Significant
Bits (LSBs). The comparator outputs are decoded and com-
bined into the 8-bit result.
If the user has selected Single Channel mode (OMS = HIGH)
the 8-bit data word is directed to an A output bank. Data are
strobed to the output on the rising edge of the ENCODE input
with four pipeline delays. If the user has selected Dual Channel
mode (OMS = LOW) the data are alternately directed between
the A and B output banks and the data has five pipeline delays.
At power-up, the N sample data can appear at either the A or B
Port. To align the data in a known state, the user must strobe
DATA SYNC (DS, DS) per the conditions described in the
Timing section.
Graphics Applications
The high bandwidth and low power of the AD9483 makes it
very attractive for applications that require the digitization of
presampled waveforms, wherein the input signal rapidly slews
from one level to another, then is relatively stable for a period of
time. Examples of these include digitizing the output of com-
puter graphic display systems, and very high speed solid state
imagers.
These applications require the converter to process inputs with
frequency components well in excess of the sampling rate (often
with subnanosecond rise times), after which the A/D must settle
and sample the input in well under one pixel time. The architec-
ture of the AD9483 is vastly superior to older flash architec-
tures, which not only exhibit excessive input capacitance (which
is very hard to drive), but can make major errors when fed a
very rapidly slewing signal. The AD9483’s extremely wide
bandwidth Track/Hold circuit processes these signals without
difficulty.
Using the AD9483
Good high speed design practices must be followed when using
the AD9483. Decoupling capacitors should be physically as
close as possible to the chip to obtain maximum benefit. We
recommend placing a 0.1 mF capacitor at each power ground
pin pair (14 total) for high frequency decoupling and including
one 10 mF capacitor for local low frequency decoupling. Each of
the three VREF IN pins should also be decoupled by a 0.1 mF
capacitor.
The part should be located on a solid ground plane and output
needs to be driven, which in turn minimizes on-chip noise due
to heavy current flow in the outputs. We have obtained opti-
mum performance on our evaluation board by tying all VCC pins
to a quiet analog power supply system and tying all GND pins
to a quiet analog system ground.
Minimum Encode Rate
The minimum sampling rate for the AD9483 is 10 MHz for the
140 MSPS and 100 MSPS versions. To achieve this sampling
rate, the Track/Hold circuit employs a very small hold capacitor.
When operated below the minimum guaranteed sampling rate,
the T/H droop becomes excessive. This is first observed as an
increase in offset voltage, followed by degraded linearity at even
lower frequencies.
Lower effective sampling rates may be easily supported by oper-
ating the converter in Dual Port output mode and using only
one output channel. A majority of the power dissipated by the
AD9483 is static (not related to conversion rate), so the penalty
for clocking at twice the desired rate is not high.
Digital Inputs
SNR performance is directly related to the sampling clock sta-
bility in A/D converters, particularly for high input frequencies
and wide bandwidths.
ENCODE and Data Select (DS) can be driven differentially or
single-ended. For single-ended operation, the complement
inputs (ENCODE, DS) are internally biased to VDD/3 (~1.5 V)
by a high impedance on-chip resistor divider (Figure 5), but
they may be externally driven to establish an alternate threshold
if desired. A 0.1 mF decoupling capacitor to ground is sufficient
to maintain a threshold appropriate for TTL or CMOS logic.
When driven differentially, ENCODE and DS will accommo-
date differential signals centered between 1.5 V and 4.5 V with a
total differential swing ‡800 mV (VID ‡400 mV).
Note the 6-diode clock input protection circuitry in Figure 5.
This limits the differential input voltage to –2.1 V. When the
diodes turn on, current is limited by the 300 W series resistor.
Exceeding 2.1 V across the differential inputs will have no im-
pact on the performance of the converter, but be aware of the
clock signal distortion that may be produced by the nonlinear
impedance at the converter.
Figure 34.Input Signal Level Definitions

Partno	Mfg	Dc	Qty	Available	Descript
AD9483KS-100 \|AD9483KS100	ADI	N/a	204	avai	Triple 8-Bit, 140 MSPS A/D Converter
AD9483KS-140 \|AD9483KS140	ADI	N/a	10	avai	Triple 8-Bit, 140 MSPS A/D Converter