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AD9481-AD9481BSUZ-250
8-Bit, 250 MSPS, 3.3 V A/D Converter
8-Bit, 250 MSPS
3.3 V A/D Converter
Rev. 0
FEATURES
DNL = ±0.35 LSB
INL = ±0.26 LSB
Single 3.3 V supply operation (3.0 V to 3.6 V)
Power dissipation of 439 mW at 250 MSPS
1 V p-p analog input range
Internal 1.0 V reference
Single-ended or differential analog inputs
De-multiplexed CMOS outputs
Power-down mode
Clock duty cycle stabilizer
APPLICATIONS
Digital oscilloscopes
Instrumentation and measurement
Communications
Point-to-point radios
Digital predistortion loops
FUNCTIONAL BLOCK DIAGRAM D7A TO D0A
VIN+
VIN–
CLK+
CLK–
VREFSENSE
DCO+
DCO–
AGNDDRGNDDRVDDAVDD
PDWNS1
DS+
DS–
D7B TO D0B
Figure 1.
GENERAL DESCRIPTION The AD9481 is an 8-bit, monolithic analog-to-digital converter
(ADC) optimized for high speed and low power consumption.
Small in size and easy to use, the product operates at a
250 MSPS conversion rate, with excellent linearity and dynamic
performance over its full operating range.
To minimize system cost and power dissipation, the AD9481
includes an internal reference and track-and-hold circuit. The
user only provides a 3.3 V power supply and a differential
encode clock. No external reference or driver components are
required for many applications.
The digital outputs are TTL/CMOS-compatible with an option
of twos complement or binary output format. The output data
bits are provided in an interleaved fashion along with output
clocks that simplifies data capture.
The AD9481 is available in a Pb-free, 44-lead, surface-mount
package (TQFP-44) specified over the industrial temperature
range (−40°C to +85°C).
PRODUCT HIGHLIGHTS 1. Superior linearity. A DNL of ±0.35 makes the AD9481
suitable for many instrumentation and measurement
applications
2. Power-down mode. A power-down function may be exercised
to bring total consumption down to 15 mW.
3. De-multiplexed CMOS outputs allow for easy interfacing
with low cost FPGAs and standard logic.
TABLE OF CONTENTS DC Specifications.............................................................................3
Digital Specifications........................................................................4
AC Specifications..............................................................................5
Switching Specifications..................................................................6
Timing Diagram...........................................................................7
Absolute Maximum Ratings............................................................8
Explanation of Test Levels...........................................................8
ESD Caution..................................................................................8
Pin Configuration and Function Descriptions.............................9
Terminology....................................................................................10
Typical Performance Characteristics...........................................12
Equivalent Circuits.........................................................................16
Applications.....................................................................................17
Analog Inputs..............................................................................17
Voltage Reference.......................................................................17
Clocking the AD9481.................................................................19
DS Inputs.....................................................................................19
Digital Outputs...........................................................................20
Interleaving Two AD9481s........................................................20
Data Clock Out...........................................................................20
Power-Down Input.....................................................................20
AD9481 Evaluation Board............................................................21
Power Connector........................................................................21
Analog Inputs..............................................................................21
Gain..............................................................................................21
Optional Operational Amplifier...............................................21
Clock............................................................................................21
Optional Clock Buffer...............................................................21
DS.................................................................................................21
Optional XTAL...........................................................................22
Voltage Reference.......................................................................22
Data Outputs...............................................................................22
Evaluation Board Bill of Materials (BOM).................................23
PCB Schematics..............................................................................24
PCB Layers......................................................................................26
Outline Dimensions.......................................................................28
Ordering Guide..........................................................................28
REVISION HISTORY
10/04—Revision 0: Initial Version DC SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V; TMIN = −40°C, TMAX = +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and
clock inputs, unless otherwise noted.
Table 1. 1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1 V external reference and 1 V p-p input range). Internal reference mode; SENSE = AGND.
3 External reference mode; VREF driven by external 1.0 V reference; SENSE = AVDD. In FS = 1 V, both analog inputs are 500 mV p-p and out of phase with each other.
5 Supply current measured with rated encode and a 20 MHz analog input. Power dissipation measured with dc input, see the T section for power vs. clock
rate.
erminology
DIGITAL SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V; TMIN = −40°C, TMAX = +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and
clock inputs, unless otherwise noted.
Table 2. The common mode for CLOCK inputs can be externally set, such that 0.9 V < CLK ± < 2.6 V.
2 Capacitive loading only.
AC SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V; TMIN = −40°C, TMAX = +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and
clock inputs, unless otherwise noted.
Table 3. DC and Nyquist bin energy ignored.
SWITCHING SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V; differential encode input, duty cycle stabilizer enabled, unless otherwise noted.
Table 4. 1 CLOAD equals 5 pF maximum for all output switching specifications. Valid time is approximately equal to minimum tPD.
3 TCPD equals clock rising edge to DCO (+ or −) rising edge delay. Data changing to (DCO+ or DCO−) rising edge delay.
5 TSKA, TSKB are both clock rate dependent delays equal to TCYCLE − (Data to DCO skew).
TIMING DIAGRAM INTERLEAVED DATA OUT
VIN
CLK+
CLK–
PORT A
D7B TO D0B
PORT B
DS+
DS–
DCO+
DCO–
Figure 2. Timing Diagram
ABSOLUTE MAXIMUM RATINGS Thermal impedance (θJA) = 46.4°C/W (4-layer PCB).
Table 5. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
Table 6.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CLK–
AVDD
AGND
D7A (MSB)
DRGND
DRVDD
CLK+
D6A
D5A
D4A
D3A
AGND
AVDD
AVDD
DRGND
PDWN
SENSE
D7B (MSB)
D6B
D5B
D4B
A (LS
DRGND
DCO–
DCO+
DRV
B (LS
PIN 1
AGND
VIN
VIN
AGND
AGND
AD9481
TOP VIEW(Not to Scale)Figure 3. Pin Configuration
Table 7. Pin Function Descriptions TERMINOLOGY
Analog Bandwidth The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay The delay between the 50% point of the rising edge of the
encode command and the instant the analog input is sampled.
Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay.
Clock Pulse-Width/Duty Cycle Pulse-width high is the minimum amount of time that the clock
pulse should be left in a Logic 1 state to achieve rated
performance; pulse-width low is the minimum time clock pulse
should be left in a low state. See timing implications of changing
tEH in the Clocking the AD9481 section. At a given clock rate,
these specifications define an acceptable clock duty cycle.
Crosstalk Coupling onto one channel being driven by a low level
(−40 dBFS) signal when the adjacent interfering channel is
driven by a full-scale signal.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating
the inputs phase 180° and taking the peak measurement again.
The difference is then computed between both peak
measurements.
Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB) ENOB is calculated from the measured SINAD based on the
equation (assuming full-scale input)
6.021.76−=MEASUREDSINADENOB
Full-Scale Input Power Expressed in dBm. Computed using the following equation ⎟⎟⎟⎟⎜⎜⎜⎜0.001log10INPUT
FULLSCALE2
FULLSCALEZ
rmsV
Power
Gain Error Gain error is the difference between the measured and ideal
full-scale input voltage range of the ADC.
Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Maximum Conversion Rate The encode rate at which parametric testing is performed.
Output Propagation Delay The delay between a differential crossing of CLK+ and CLK−
and the time when all output data bits are within valid logic
levels.
Noise (for Any Range within the ADC) This value includes both thermal and quantization noise. =noiseV
where:
Z is the input impedance.
FS is the full scale of the device for the frequency in question.
SNR is the value for the particular input level.
Signal is the signal level within the ADC reported in dB below
Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics, but excluding dc.
Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious
component may or may not be a harmonic. It also may be
reported in dBc (degrades as signal level is lowered) or dBFS
(always related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value
of the worst third-order intermodulation product, in dBc.
Two-Tone SFDR The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. It also may be reported in
dBc (degrades as signal level is lowered) or in dBFS (always
relates back to converter full scale).
Worst Other Spur The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic), reported in dBc.
Transient Response Time The time it takes for the ADC to reacquire the analog input
after a transient from 10% above negative full scale to 10%
below positive full scale.
Out-of-Range Recovery Time This is the time it takes for the ADC to reacquire the analog
input after a transient from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
TYPICAL PERFORMANCE CHARACTERISTICS AVDD, DRVDD = 3.3 V, T = 25°C, AIN differential drive, FS = 1, internal reference mode, unless otherwise noted.
040802060100120(MHz)
(dB)
Figure 4. FFT: fS = 250 MSPS, AIN = 10.3 MHz @ −1 dBFS
040802060100120(MHz)
(dB)
Figure 5. FFT: fS = 250 MSPS, AIN = 70 MHz @ −1 dBFS
040802060100120(MHz)
(dB)
Figure 6. FFT: fS = 250 MSPS, AIN = 70 MHz @ −1 dBFS, Single-Ended Input
040802060100120(MHz)
(dB)
Figure 7. FFT: fS = 250 MSPS, AIN = 170 MHz @ −1 dBFS
040035030025020015010050AIN (MHz)
(dB)
Figure 8. Analog Input Frequency Sweep,
AIN = −1 dBFS, FS = 1 V, fS = 250 MSPS
040035030025020015010050AIN (MHz)
(dB)
Figure 9. Analog Input Frequency Sweep,
AIN =−1 dBFS, FS = 0.75 V, fS = 250 MSPS, External VREF Mode
030025020015010050SAMPLE CLOCK (MHz)
(dB)
Figure 10. SNR, SINAD, SFDR vs. Sample Clock Frequency,
AIN = 70 MHz @ −1 dB
–700–10–20–30–40–50–60ANALOG INPUT DRIVE LEVEL (dBFS)
(dB)
Figure 11. SFDR vs. AIN Input Level; AIN = 70 MHz @ 250 MSPS
040802060100120(MHz)
(dB)
Figure 12. Two-Tone Intermodulation Distortion
(69.3 MHz and 70.3 MHz; fS = 250 MSPS)
10010020050150250300SAMPLE CLOCK (MSPS)
CURRE
NT (mA)
Figure 13. IAVDD and IDRVDD vs. Clock Rate, CLOAD = 5 pF
AIN = 70 MHz @ −1 dBFS
406030507080CLOCK POSITIVE DUTY CYCLE (%)
(dB)
Figure 14. SNR, SINAD vs. Clock Pulse-Width High,
AIN = 70 MHz @ −1 dBFS, 250 MSPS, DCS On/Off
0.51.10.91.50.71.31.71.9EXTERNAL VREF VOLTAGE (V)
NR, S
INAD (dB)
DR (dBc
Figure 15. SNR, SINAD, and SFDR vs. VREF in External Reference Mode, AIN =
70 MHz @ −1 dBFS, 250 MSPS
–40–20020406080TEMPERATURE (°C)
GAIN E
RROR (%)
Figure 16. Full-Scale Gain Error vs. Temperature,
AIN = 70.3 MHz @ −0.5 dBFS, 250 MSPS
–40–20020406080TEMPERATURE (°C)
(dB)
Figure 17. SINAD, SFDR vs. Temperature,
AIN = 70 MHz @ −1 dBFS, 250 MSPS
2.73.63.53.43.33.23.13.02.92.8AVDD (V)
CHANGE
IN V
(%)
Figure 18. VREF Sensitivity to AVDD
3.53.6AVDD (V)
(dB)
Figure 19. SNR, SINAD, and SFDR vs. Supply Voltage,
AIN = 70.3 MHz @ −1 dBFS, 250 MSPS
0.550100150200250CODE
LSB
Figure 20. Typical DNL Plot,
AIN = 10.3 MHz @ −0.5 dBFS, 250 MSPS
0.5050100150200250CODE
LSB
Figure 21. Typical INL Plot,
AIN = 10.3 MHz @ −0.5 dBFS, 250 MSPS
