AD9444BSVZ-80 ,14-Bit, 80 MSPS A/D ConverterGENERAL DESCRIPTION receivers. The AD9444 is a 14-bit monolithic, sampling analog-to-digital 2. Eas ..
AD9480 ,8-Bit, 250 MSPS, 3.3 V A/D Converterapplications. conversion rate, with excellent linearity and dynamic performance over its full opera ..
AD9480ASUZ-250 ,8-Bit, 250 MSPS, 3.3 V A/D ConverterFEATURES FUNCTIONAL BLOCK DIAGRAM DNL = ± 0.25 LSB INL = ± 0.5 LSB VREF SENSE AGND DrGND DRVDD AVD ..
AD9480BSUZ-250 ,8-Bit, 250 MSPS, 3.3 V A/D ConverterSpecifications subject to change without notice. No license is granted by implication www.analog.c ..
AD9481 ,8-Bit, 250 MSPS, 3.3 V A/D Converterapplications. 3. De-multiplexed CMOS outputs allow for easy interfacing with low cost FPGAs and st ..
AD9481BSUZ-250 ,8-Bit, 250 MSPS, 3.3 V A/D ConverterGENERAL DESCRIPTION package (TQFP-44) specified over the industrial temperature The AD9481 is an 8- ..
ADS7845E ,TOUCH SCREEN CONTROLLERMAXIMUM RATINGS 15 CS Chip Select Input. Controls conversion timing andenables the serial input/out ..
ADS7845E ,TOUCH SCREEN CONTROLLERFEATURESl 5-WIRE TOUCH SCREEN INTERFACEThe ADS7845 is a 12-bit sampling analog-to-digitalconverter ..
ADS7846 ,TOUCH-SCREEN CONTROLLER.ADS78462SBAS125H
ADS7846E ,TOUCH-SCREEN CONTROLLERPIN CONFIGURATIONTop View VFBGATop View SSOP, TSSOPDCLK CS DIN BUSY DOUT+V 1 16 DCLKCC1 2 3 4 5 6 7 ..
ADS7846E/2K5G4 ,TOUCH-SCREEN CONTROLLERFEATURES* SAME PINOUT AS ADS7843The ADS7846 is a next-generation version to the industrystandard AD ..
ADS7846EG4 ,4-wire Touch Screen Controller 16-SSOP -40 to 85PIN CONFIGURATIONTop View VFBGATop View SSOP, TSSOPDCLK CS DIN BUSY DOUT+V 1 16 DCLKCC1 2 3 4 5 6 7 ..
AD9444BSVZ-80
14-Bit, 80 MSPS A/D Converter
14-Bit, 80 MSPS, A/D ConverterRev. 0
FEATURES
80 MSPS guaranteed sampling rate
100 dB two-tone SFDR with 69.3 MHz and 70.3 MHz
73.1 dB SNR with 70 MHz input
97 dBc SFDR with 70 MHz input
Excellent linearity
DNL = ±0.4 LSB typical
INL = ±0.6 LSB typical
1.2 W power dissipation
3.3 V and 5 V supply operation
2.0 V p-p differential full-scale input
LVDS outputs (ANSI-644 compatible)
Data format select
Output clock available
APPLICATIONS
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar, infared imaging
Communications instrumentation
GENERAL DESCRIPTION The AD9444 is a 14-bit monolithic, sampling analog-to-digital
converter (ADC) with an on-chip, track-and-hold circuit and is
optimized for power, small size, and ease of use. The product
operates at up to an 80 MSPS conversion rate and is optimized
for multicarrier, multimode receivers, such as those found in
cellular infrastructure equipment.
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are LVDS-compatible (ANSI-
644) or CMOS-compatible and include the means to reduce
the overall current needed for short trace distances.
FUNCTIONAL BLOCK DIAGRAM
AGNDDRGNDDRVDD
VREF
CLK+
VIN+
VIN–
CLK–
DCOAVDD1AVDD2
DCS MODE
DFS
OUTPUT MODE
D13–D0
REFBSENSEREFT
Figure 1.
Optional features allow users to implement various selectable
operating conditions, including data format select and output
data mode.
The AD9444 is available in a 100-lead surface-mount plastic
package (100-lead TQFP/EP) specified over the industrial
temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS 1. High performance: Outstanding SFDR performance for mul-
ticarrier, multimode 3G and 4G cellular base station
receivers.
2. Ease of use: On-chip reference and track-and-hold. An
output clock simplifies data capture.
3. Packaged in a Pb-free, 100-lead TQFP/EP.
4. Clock DCS maintains overall ADC performance over a wide
range of clock pulse widths.
5. OR (out-of-range) outputs indicate when the signal is beyond
the selected input range.
TABLE OF CONTENTS DC Specifications.............................................................................3
AC Specifications..............................................................................4
Digital Specifications........................................................................5
Switching Specifications..................................................................6
Explanation of Test Levels...........................................................7
Absolute Maximum Ratings............................................................8
ESD Caution..................................................................................8
Definitions of Specifications...........................................................9
Pin Configurations and Function Descriptions.........................10
Equivalent Circuits.........................................................................14
Typical Performance Characteristics...........................................15
Theory of Operation......................................................................20
Analog Input and Reference Overview...................................20
Clock Input Considerations......................................................22
Power Considerations................................................................23
Digital Outputs...........................................................................23
Timing.........................................................................................23
Operational Mode Selection.....................................................23
Evaluation Board........................................................................24
LVDS Evaluation Board Schematics........................................25
LVDS Mode Evaluation Board Bill of Materials (BOM)......30
CMOS Evaluation Board Schematics......................................32
CMOS Mode Evaluation Board Bill of Materials (BOM).....37
Outline Dimensions.......................................................................39
Ordering Guide..........................................................................39
REVISION HISTORY
10/04—Revision 0: Initial Version
DC SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed
reference (1.0 V mode), AIN = −0.5 dBFS, DCS on, unless otherwise noted.
Table 1. 1 The internal voltage reference is trimmed at final test to minimize the gain error of the AD9444. Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
AC SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed
reference (1.0 V mode), AIN = −0.5 dBFS, DCS on, unless otherwise noted.
Table 2.
DIGITAL SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDSBIAS = 3.74 kΩ, unless otherwise noted.
Table 3. 1 Output voltage levels measured with 5 pF load on each output. LVDS RTERM = 100 Ω.
