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AD9433BSQ-105-AD9433BSQ-125
12-Bit, 105 MSPS/125 MSPS IF Sampling A/D Converter
REV.0
12-Bit, 105 MSPS/125 MSPS
IF Sampling A/D Converter
FUNCTIONAL BLOCK DIAGRAM
FEATURES
IF Sampling up to 350 MHz
SNR = 67.5dB, fIN up to Nyquist @ 105 MSPS
SFDR = 83 dBc, fIN 70 MHz @ 105 MSPS
SFDR = 72 dBc, fIN 150 MHz @ 105 MSPS
2 Vp-p Analog Input Range Option
On-Chip Clock Duty Cycle Stabilization
On-Chip Reference and Track/Hold
SFDR Optimization Circuit
Excellent Linearity:
DNL = �0.25 LSB (Typ)
INL = �0.5 LSB (Typ)
750 MHz Full Power Analog Bandwidth
Power Dissipation = 1.35 W Typical @ 125 MSPS
Two’s Complement or Offset Binary Data Format
5.0 V Analog Supply Operation
2.5 V to 3.3 V TTL/CMOS Outputs
APPLICATIONS
Cellular Infrastructure Communication Systems
3G Single and Multicarrier Receivers
IF Sampling Schemes
Wideband Carrier Frequency Systems
Point to Point Radios
LMDS, Wireless Broadband
MMDS Base Station Units
Cable Reverse Path
Communications Test Equipment
Radar and Satellite Ground Systems
GENERAL INTRODUCTIONThe AD9433 is a 12-bit monolithic sampling analog-to-digital
converter with an on-chip track-and-hold circuit and is designed
for ease of use. The product operates up to 125MSPS conver-
sion rate and is optimized for outstanding dynamic performance
in wideband and high IF carrier systems.
The ADC requires a 5 V analog power supply and a differential
encode clock for full performance operation. No external refer-
ence or driver components are required for many applications.
The digital outputs are TTL/CMOS compatible and a separate
output power supply pin supports interfacing with 3.3 V or
2.5 V logic.
A user-selectable, on-chip proprietary circuit optimizes spurious-
free dynamic range (SFDR) versus signal-to-noise-and-distortion
(SINAD) ratio performance for different input signal frequencies,
providing as much as 83dBc SFDR performance over the dc
to 70 MHz band.
The encode clock supports either differential or single-ended
input and is PECL-compatible. The output format is user-
selectable for binary or two’s complement and provides an
overrange (OR) signal.
Fabricated on an advanced BiCMOS process, the AD9433 is
available in a thermally enhanced 52-lead plastic quad flatpack
specified over the industrial temperature range (–40°C to
+85°C) and is pin-compatible with the AD9432.
PRODUCT HIGHLIGHTSIF Sampling
The AD9433 maintains outstanding ac performance up to
input frequencies of 350 MHz. Suitable for 3G Wideband
Cellular IF sampling receivers.Pin-Compatibility
This ADC has the same footprint and pin layout as the
AD9432, 12-Bit 80/105 MSPS ADC.SFDR Performance
A user-selectable on-chip circuit optimizes SFDR performance
as much at 85 dBc from dc to 70 MHz.Sampling Rate
At 125 MSPS, this ADC is ideally suited for current wireless
and wired broadband applications such as LMDS/MMDS
and cable reverse path.
AD9433–SPECIFICATIONS
(VDD = 3.3 V, VCC = 5 V; internal reference; differential encode input, unless otherwise noted.)THERMAL DRIFT
ENCODE INPUTS
NOTESGain error and gain temperature coefficients are based on the ADC only (with a fixed 2.5 V external reference and a 2 V p-p differential analog input).
DC SPECIFICATIONS
AD9433*SNR/Harmonics based on an analog input voltage of –0.5 dBFS referenced to a 2 V full-scale input range. Harmonics are specified with the SFDR active
(SFDR = +5 V). SNR/SINAD specified with SFDR disabled (SFDR = Ground).
Specifications subject to change without notice.
AC SPECIFICATIONS(VDD = 3.3 V, VCC = 5 V; differential encode input, unless otherwise noted.)
SWITCHING SPECIFICATIONSAperture Delay (tA)25�C
Output Fall Time (tF)
NOTES
(VDD = 3.3 V, VCC = 5 V; differential encode input, unless otherwise noted.)
AD9433
EXPLANATION OF TEST LEVELS
Test Level100% production tested.100% production tested at 25�C and guaranteed by design
and characterization at specified temperatures.
IIISample Tested OnlyParameter is guaranteed by design and characterization testing.Parameter is a typical value only.100% production tested at 25�C and guaranteed by design
and characterization for industrial temperature range.
THERMAL CHARCTERISTICS
Thermal Resitance52-Lead PowerQuad® 4 LQFP_ED
�JA = 25°C/W, Soldered Heat Sink,No Airflow
�JA = 33°C/W, Unsoldered Heat Sink,No Airflow
�JC = 2°C/W, Bottom of Package(Heat Sink)
Simulated typical performance for 4-layerJEDEC board, horizontal orientation.
ABSOLUTE MAXIMUM RATINGS**Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9433 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
(MSB) D11
D10D8D7D6
DGND
DGNDD4
GNDAINAINGNDV
VREFOUTVREFINV
GNDSFDR MODEDFSGND
GND
VCC
GND
GND
VCC
VCC
ENCODE
ENCODE
GND
VCC
GND
DGND
VDD
GND
GND
VCC
VCC
GND
GND
GND
VDD
DGND
D0 (LSB)
