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AD9432BST-105 |AD9432BST105ADIN/a70avai12-Bit, 80 MSPS/105 MSPS A/D Converter
AD9432BST-105 |AD9432BST105ADN/a25avai12-Bit, 80 MSPS/105 MSPS A/D Converter


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AD9432BST-105
12-Bit, 80 MSPS/105 MSPS A/D Converter
REV. B
12-Bit, 80 MSPS/105 MSPS
A/D Converter
FUNCTIONAL BLOCK DIAGRAM
FEATURES
On-Chip Reference and Track/Hold
On-Chip Input Buffer
850 mW Typical Power Dissipation at 105 MSPS
500 MHz Analog Bandwidth
SNR = 67 dB @ 49 MHz AIN at 105 MSPS
SFDR = 80 dB @ 49MHz AIN at 105 MSPS
2.0 V p-p Differential Analog Input Range
Single +5.0 V Supply Operation
+3.3 V CMOS/TTL Outputs
Two’s Complement Output Format
APPLICATIONS
Communications
Basestations and ‘Zero-IF’ Subsystems
Wireless Local Loop (WLL)
Local Multipoint Distribution Service (LMDS)
HDTV Broadcast Cameras and Film Scanners
GENERAL INTRODUCTION

The AD9432 is a 12-bit monolithic sampling analog-to-digital
converter with an on-chip track-and-hold circuit and is optimized
for high-speed conversion and ease of use. The product operates
at a 105 MSPS conversion rate with outstanding dynamic per-
formance over its full operating range.
The ADC requires only a single 5.0 V power supply and a
105MHz encode clock for full-performance operation. No
external reference or driver components are required for many
applications. The digital outputs are TTL/CMOS compatible
and a separate output power supply pin supports interfacing
with 3.3 V logic. The encode input supports either differential
or single-ended and is TTL/CMOS-compatible.
Fabricated on an advanced BiCMOS process, the AD9432 is
available in a 52-lead plastic quad flatpack package (LQFP)
specified over the industrial temperature range (–40°C to
+85°C).
AD9432–SPECIFICATIONS
(VDD = 3.3 V, VCC = 5.0 V; external reference; differential encode input, unless
otherwise noted)
AD9432
NOTESGain error and gain temperature coefficients are based on the ADC only (with a fixed 2.5 V external reference and a 2 V p-p differential analog input).tV and tPD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is
not to exceed an ac load of 10 pF or a dc current of ±40 µA. Rise and fall times measured from 10% to 90%.Power dissipation measured with encode at rated speed and a dc analog input. (Outputs Static, IVDD = 0.)SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 2V full-scale input range.
Typical θJA for LQFP package = 50°C/W.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*

VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6 V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
VREFIN . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . +150°C
CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may affect device reliability.
ORDERING GUIDE
AD9432
GND
GNDGND
GND
VCC
VCC
GND
GND
GND
VDD
DGND
D0 (LSB)
VCC
GND
GND
VCC
VCC
ENCODE
ENCODE
GND
VCC
GND
DGND
VDD
(MSB) D11
D10D8D7D6
DGND
DGNDD4
DNCV
GNDVREFINVREFOUTV
AINAINGNDGNDV
EXPLANATION OF TEST LEVELS
Test Level
100% production tested.100% production tested at +25°C and sample tested at
specified temperatures.
IIISample tested only.Parameter is guaranteed by design and characterization
testing.Parameter is a typical value only.100% production tested at +25°C; guaranteed by design
and characterization testing for industrial temperature
range.
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
DEFINITION OF SPECIFICATIONS
Analog Bandwidth (Small Signal)

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay

The delay between a differential crossing of ENCODE and
ENCODE and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.
Differential Nonlinearity

The deviation of any code from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle

Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic “1” state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. At a given clock
rate, these specs define an acceptable Encode duty cycle.
Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Maximum Conversion Rate

The encode rate at which parametric testing is performed.
Output Propagation Delay

The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise Plus Distortion (SINAD)

The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
Figure 1. Timing Diagram
Figure 2.Equivalent Voltage Reference Input Circuit
Figure 3.Equivalent Voltage Reference Output Circuit
Two-Tone SFDR

The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).
Worst Harmonic

The ratio of the rms signal amplitude to the rms value of the
worst harmonic component, reported in dBc.
Figure 4.Equivalent Encode Input Circuit
Figure 5.Equivalent Digital Output Circuit
AD9432
–Typical Performance Characteristics
ENCODE – MSPS
0206080100120140160

Figure 7.SNR/SINAD/SFDR vs. fS: fIN = 10.3 MHz

ENCODE – MSPS
dBc6080100120140160
–50

Figure 8.Harmonics vs. fS: fIN = 10.3 MHz
ANALOG INPUT FREQUENCY – MHz
180

Figure 9.SINAD vs. fIN: fS = 105 MSPS
AIN INPUT FREQUENCY – MHz (–0.5dBFS)
SNR
dB100150200250

Figure 10.SNR vs. AIN Input Frequency,
Encode = 105 MSPS
Figure 11.Harmonics vs. fIN: fS = 105 MSPS
Figure 12.Worst-Case Spur (Other than Second and
Third) vs. fIN: fS = 105 MSPS

Figure 13.Spectrum: fS = 105 MSPS, fIN = 10.3 MHz
Figure 14.Spectrum: fS = 105 MSPS, fIN = 27 MHz

Figure 15.Spectrum: fS = 105 MSPS, fIN = 40.9 MHz
Figure 16.Spectrum: fS = 105 MSPS, fIN = 50.3 MHz
Figure 17.Two-Tone Spectrum, Wideband: fS =
105 MSPS, AIN1 = 29.3 MHz, AIN2 = 30.3 MHz
Figure 18.Two-Tone Spectrum, Wideband: fS =
105 MSPS, AIN1 = 70.3 MHz, AIN2 = 71.3 MHz
AD9432
ANALOG INPUT POWER LEVEL – dBFS
WORST CASE SPURIOUS
dBc AND dBFS
–500

Figure 19.Single Tone SFDR
LSB
DNL
–1.00

Figure 20.Differential Nonlinearity: fS = 105 MSPS
Figure 21.Integral Nonlinearity: fS = 105 MSPS
CURRENT – mA
VOLTAGE 10
1.5

Figure 22.Voltage Reference Output vs. Current Load
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