AD9411BSV-200 ,10-Bit, 170/200 MSPS 3.3 V A/D ConverterSPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, internal r ..
AD9430BSV-170 ,12-Bit, 170 MSPS 3.3V A/D ConverterSPECIFICATIONS (AV = 3.3 V, DrV = 3.3V; ENCODE = Maximum Conversion Rate ; T = -40°C, T DD DD MIN M ..
AD9432BST-105 ,12-Bit, 80 MSPS/105 MSPS A/D ConverterSpecifications subject to change without notice.*Stresses above those listed under Absolute Maximum ..
AD9432BST-105 ,12-Bit, 80 MSPS/105 MSPS A/D ConverterSPECIFICATIONSTest AD9432BST-80 AD9432BST-105Parameter Temp Level Min Typ Max Min Typ Max UnitRESOL ..
AD9433BSQ-105 ,12-Bit, 105 MSPS/125 MSPS IF Sampling A/D ConverterSPECIFICATIONS (V = 3.3 V, V = 5 V; internal reference; differential encode input, unless otherwise ..
AD9433BSQ-125 ,12-Bit, 105 MSPS/125 MSPS IF Sampling A/D ConverterSPECIFICATIONS (V = 3.3 V, V = 5 V; differential encode input, unless otherwise noted.)DD CCTest AD ..
ADS7843E ,TOUCH SCREEN CONTROLLERTYPICAL CHARACTERISTICSAt T = +25°C, +V = +2.7V, V = +2.5V, f = 125kHz, and f = 16 • f = 2MHz, unle ..
ADS7843E/2K5G4 ,4-wire Touch Screen Controller 16-SSOP -40 to 85FEATURES* 4-WIRE TOUCH SCREEN INTERFACEThe ADS7843 is a 12-bit sampling Analog-to-Digital Con-verte ..
ADS7843EG4 ,4-wire Touch Screen Controller 16-SSOP -40 to 85ELECTRICAL CHARACTERISTICSAt T = –40°C to +85°C, +V = +2.7V, V = +2.5V, f = 125kHz, f = 16 • f = 2M ..
ADS7844 ,12-Bit, 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTERMaximum Ratings”may cause permanent damage to the device. Exposure to absolute maximumconditions fo ..
ADS7844E ,12-Bit/ 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTERSPECIFICATION: +5VAt T = –40°C to +85°C, +V = +5V, V = +5V, f = 200kHz, and f = 16 • f = 3.2MHz, u ..
ADS7844EB ,12-Bit/ 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTERSPECIFICATION: +2.7VAt T = –40°C to +85°C, +V = +2.7V, V = +2.5V, f = 125kHz, and f = 16 • f = 2MH ..
AD9411BSV-170-AD9411BSV-200
10-Bit, 170/200 MSPS 3.3 V A/D Converter
10-Bit, 170/200 MSPS
3.3 V A/D Converter
Rev. A
FEATURES
SNR = 60 dB @ fIN up to 70 MHz @ 200 MSPS
ENOB of 9.8 @ fIN up to 70 MHz @ 200 MSPS (–0.5 dBFS)
SFDR = 80 dBc @ fIN up to 70 MHz @ 200 MSPS (–0.5 dBFS)
Excellent linearity:
DNL = ±0.15 LSB (typical)
INL = ±0.25 LSB (typical)
LVDS output levels
700 MHz full-power analog bandwidth
On-chip reference and track-and-hold
Power dissipation = 1.25 W typical @ 200 MSPS
1.5 V input voltage range
3.3 V supply operation
Output data format option
Clock duty cycle stabilizer
Pin compatible to LVDS mode AD9430
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
FUNCTIONAL BLOCK DIAGRAM
SENSEVREF
VIN+
VIN–
CLK+
CLK–S5
DCO+
DCO–
DATA,OVERRANGEIN LVDS
AGNDDRGNDDRVDDAVDD04530-0-001
Figure 1.
Power amplifier linearization
GENERAL DESCRIPTION The AD9411 is a 10-bit monolithic sampling analog-to-digital
converter optimized for high performance, low power, and ease
of use. The product operates up to a 200 MSPS conversion rate
and is optimized for outstanding dynamic performance in
wideband carrier and broadband systems. All necessary
functions, including track-and-hold (T/H) and reference, are
included on the chip to provide a complete conversion solution.
The ADC requires a 3.3 V power supply and a differential
sample clock for full performance operation. The digital outputs
are LVDS compatible and support both twos complement and
offset binary format. A data clock output is available to ease
data capture.
Fabricated on an advanced BiCMOS process, the AD9411 is
available in a 100-lead surface-mount plastic package (e-PAD
TQFP-100) specified over the industrial temperature range
(–40°C to +85°C).
PRODUCT HIGHLIGHTS 1. High performance.
Maintains 60 dB SNR @ 200 MSPS with a 70 MHz input.
2. Low power.
Consumes only 1.25 W @ 200 MSPS.
3. Ease of use.
LVDS output data and output clock signal allow interface
to current FPGA technology. The on-chip reference and
sample-and-hold function provide flexibility in system
design. Use of a single 3.3 V supply simplifies system
power supply design.
4. Out-of-range (OR).
The OR output bit indicates when the input signal is
beyond the selected input range.
TABLE OF CONTENTS DC Specifications.............................................................................3
AC Specifications..............................................................................4
Digital Specifications........................................................................5
Switching Specifications..................................................................6
Explanation of Test Levels...........................................................6
Absolute Maximum Ratings............................................................7
ESD Caution..................................................................................7
Pin Configuration and Function Descriptions.............................8
Terminology....................................................................................10
Equivalent Circuits.........................................................................12
Typical Performance Characteristics...........................................13
Application Notes...........................................................................18
Clock Input..................................................................................18
Analog Input...............................................................................18
LVDS Outputs.............................................................................19
Clock Outputs (DCO+, DCO–)...............................................19
Voltage Reference.......................................................................19
Noise Power Ratio Testing (NPR)............................................19
Evaluation Board............................................................................21
Power Connector........................................................................21
Analog Inputs.............................................................................21
Gain..............................................................................................21
Clock............................................................................................21
Voltage Reference.......................................................................21
Data Format Select.....................................................................21
Data Outputs...............................................................................21
Clock XTAL.................................................................................21
Outline Dimensions.......................................................................27
Ordering Guide..........................................................................27
REVISION HISTORY
7/04—Data Sheet Changed from Rev. 0 to Rev. A Added 200 MSPS Grade....................................................Universal
Updated Outline Dimensions.......................................................27
Changes to Ordering Guide..........................................................27
Rev 0 : Initial Version
DC SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, unless
otherwise noted.
Table 1. Internal reference mode; SENSE = floats.
2 External reference mode; SENSE = DRVDD; VREF driven by external 1.23 V reference.
3 S5 (Pin 1) = GND. See the Analog Input section. S5 = GND in all dc, ac tests, unless otherwise specified IAVDD and IDRVDD are measured with an analog input of 10.3 MHz, –0.5 dBFS, sine wave, rated clock rate, and in LVDS output mode. See the
and sections for I
Typical Performance
CharacteristicsApplication NotesDRVDD. Power consumption is measured with a dc input at rated clock rate in LVDS output mode.
AC SPECIFICATIONS1AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, unless
otherwise noted.
Table 2. All ac specifications tested by driving CLK+ and CLK– differentially.
2 F1 = 30.5 MHz, F2 = 31 MHz.
DIGITAL SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 3. See the section. Equivalent Circuits All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+) – (CLK–)| > 200 mV.
3 Clock inputs’ common mode can be externally set, such that 0.9 V < CLK± < 2.6 V. LVDS RTERM = 100 Ω, LVDS output current set resistor (RSET) = 3.74 kΩ (1% tolerance).
SWITCHING SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 4. 1 All ac specifications tested by driving CLK+ and CLK– differentially.
EXPLANATION OF TEST LEVELS I. 100% production tested.
II. 100% production tested at 25°C and sample tested at specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100%
production tested at temperature extremes for military devices.
CLK+
AIN
tCPD
DCO+
DCO–
N–1
N+1
CLK–
DATA OUT04530-0-002
ABSOLUTE MAXIMUM RATINGS
Table 5. Typical θJA = 32°C/W (heat slug not soldered); typical θJA = 25°C/W (heat slug
soldered) for multilayer board in still air with solid ground plane.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions outside of those indicated in the operation
section of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DNC
AGND
AGND
AGNDAVDDAVDDAVDDAGNDAGNDAGNDAVDDAVDDAGND
CLK+CLK–
AGNDAVDDAVDDAGND
DNCDNCDNCDNCDNC
DRVDD
DRGND
DNCDNC
AGNDAVDDAVDDAGNDAGNDAVDDAVDDAGNDAGNDAGNDAVDDAVDDAVDDAGNDAGNDOR+OR–DVRDDDRGNDD9+D9–D8+D8–D7+D7–
AVDD
LVDSBIAS
AVDD
AGND
SENSE
VREF
AGND
AGND
AVDD
AVDD
AGND
AGND
AVDD
AVDD
AGND
VIN+
VIN–
AGND
AVDD
AGND
DRVDD
DRGND
D6+
D6–
D5+
D5–
D4+
D4–
DRGND
D3+
D3–
DCO+
DCO–
DRVDD
DRGND
D2+
D2–
D1+
D1–
D0+
D0–
DRVDD
DRGND
DNC
DNC04530-0-003
Figure 3. TQFP/EP Pinout
Table 6. Pin Function Descriptions TERMINOLOGY
Analog Bandwidth The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay The delay between the 50% point of the rising edge of the clock
command and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay.
Crosstalk Coupling onto one channel being driven by a low level (–40 dBFS)
signal when the adjacent interfering channel is driven by a full-
scale signal.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating
the input’s phase 180° and again taking the peak measurement.
The difference is then computed between both peak
measurements.
Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB) Calculated from the measured SNR based on the equation .676.1−=MEASUREDSNRENOB
Clock Pulse Width/Duty Cycle Pulse width high is the minimum amount of time the clock
pulse should be left in the Logic 1 state to achieve rated
performance; pulse width low is the minimum time the clock
pulse should be left in the low state. Refer to the timing
implications of changing tENCH in the Application Notes, Clock
Input section. At a given clock rate, these specifications define
an acceptable CLOCK duty cycle.
Full-Scale Input Power Expressed in dBm. Computed using the following equation: ⎟⎟⎟⎜⎜⎜
log10
INPUT
RMSFULLSCALE
FULLSCALEZPower
Gain Error The difference between the measured and ideal full-scale input
voltage range of the ADC.
Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate The CLOCK rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Maximum Conversion Rate The CLOCK rate at which parametric testing is performed.
Output Propagation Delay The delay between a differential crossing of CLK+ and CLK–
and the time when all output data bits are within valid logic
levels.
Noise (for Any Range within the ADC) Calculated as follows: =NOISEV
where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value of the particular
input level, and Signal is the signal level within the ADC reported
in dB below full scale. This value includes both thermal and
quantization noise.
Power Supply Rejection Ratio (PSRR) The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics but excluding dc.
Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered) or dBFS (always related
back to converter full scale).
Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of
the worst third-order intermodulation product, reported in dBc.
Two-Tone SFDR The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered) or in dBFS (always
related back to converter full scale).
Worst Other Spur The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonics) reported in dBc.
Transient Response Time The time it takes for the ADC to reacquire the analog input
after a transient from 10% above negative full scale to 10%
below positive full scale.
Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input
after a transient from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.
EQUIVALENT CIRCUITS CLK+
AVDD
CLK–
Figure 4. Clock Inputs
VIN+04530-0-005
Figure 5. Analog Inputs
S1,S504530-0-006
Figure 6. S1 to S5 Inputs
Figure 7. VREF, SENSE I/O
DX+
DRVDD
DX–
Figure 8. Data Outputs
TYPICAL PERFORMANCE CHARACTERISTICS
MHzFigure 9. FFT: fS = 170 MSPS, AIN = 10.3 MHz @ −0.5 dBFS
301020050607080–120
MHzFigure 10. FFT: fS = 170 MSPS, AIN = 65 MHz @ –0.5 dBFS
301020050607080–120
MHzFigure 11. FFT: fS = 170 MSPS, AIN = 10.3, MHz @ –0.5 dBFS,
Single-Ended Input, 0.76 V Input Range
04530-A
MHz
–120
Figure 12. FFT: fS = 200 MSPS, AIN = 10.3 MHz @ −0.5 dBFS
04530-A
MHz
–110
Figure 13. FFT: fS = 200 MSPS, AIN = 65 MHz @ −0.5 dBFS
04530-A
MHz
–110
Figure 14. FFT: fS = 200 MSPS, AIN = 70 MHz @ −0.5 dBFS,
Single-Ended Drive, 1.5 V Input Range
AIN (MHz)Figure 15. Harmonic Distortion (Second and Third) and SFDR vs. AIN
Frequency @ 170 MSPS
04530-A
(MHz)
(dB)
100
Figure 16. Harmonic Distortion (Second and Third) and SFDR vs. AIN
Frequency @ 200 MSPS
04530-A
(MHz)
(dB)
Figure 17. SNR and SINAD vs. AIN Frequency; fS = 170/200 MSPS,
AIN @ –0.5 dBFS Full Scale = 1.536 V
MHzFigure 18. Two-Tone Intermodulation Distortion
(30.5 MHz and 31.0 MHz; fS = 170 MSPS)
04530-A
(MHz)
(dB)
–120
Figure 19. Two-Tone Intermodulation Distortion
(69.3 MHz and 70.3 MHz; fS = 200 MSPS)
04530-A
(MSPS)
(dB)
Figure 20. SINAD and SFDR vs. Clock Rate
(AIN = 10.3 MHz @ –0.5 dBFS) 170/200 grade
