AD9410BSQ Fast Delivery |IC PHOENIX CO.,LIMITED

AD9410BSQ ,10-Bit, 210 MSPS A/D ConverterSPECIFICATIONSATestParameter Temp Level Min Typ Max UnitRESOLUTION 10 BitsDC ACCURACY1No Missing Co ..
AD9411BSV-170 ,10-Bit, 170/200 MSPS 3.3 V A/D ConverterGENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9411 is a 10-bit monolithic sampling analog-to-digital ..
AD9411BSV-200 ,10-Bit, 170/200 MSPS 3.3 V A/D ConverterSPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, internal r ..
AD9430BSV-170 ,12-Bit, 170 MSPS 3.3V A/D ConverterSPECIFICATIONS (AV = 3.3 V, DrV = 3.3V; ENCODE = Maximum Conversion Rate ; T = -40°C, T DD DD MIN M ..
AD9432BST-105 ,12-Bit, 80 MSPS/105 MSPS A/D ConverterSpecifications subject to change without notice.*Stresses above those listed under Absolute Maximum ..
AD9432BST-105 ,12-Bit, 80 MSPS/105 MSPS A/D ConverterSPECIFICATIONSTest AD9432BST-80 AD9432BST-105Parameter Temp Level Min Typ Max Min Typ Max UnitRESOL ..
ADS7842EB ,12-Bit/ 4-Channel Parallel Output Sampling ANALOG-TO-DIGITAL CONVERTERELECTRICAL CHARACTERISTICS: +2.7VAt T = –40°C to +85°C, +V = +2.7V, V = +2.5V, f = 125kHz, and f = ..
ADS7843E ,TOUCH SCREEN CONTROLLERTYPICAL CHARACTERISTICSAt T = +25°C, +V = +2.7V, V = +2.5V, f = 125kHz, and f = 16 • f = 2MHz, unle ..
ADS7843E/2K5G4 ,4-wire Touch Screen Controller 16-SSOP -40 to 85FEATURES* 4-WIRE TOUCH SCREEN INTERFACEThe ADS7843 is a 12-bit sampling Analog-to-Digital Con-verte ..
ADS7843EG4 ,4-wire Touch Screen Controller 16-SSOP -40 to 85ELECTRICAL CHARACTERISTICSAt T = –40°C to +85°C, +V = +2.7V, V = +2.5V, f = 125kHz, f = 16 • f = 2M ..
ADS7844 ,12-Bit, 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTERMaximum Ratings”may cause permanent damage to the device. Exposure to absolute maximumconditions fo ..
ADS7844E ,12-Bit/ 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTERSPECIFICATION: +5VAt T = –40°C to +85°C, +V = +5V, V = +5V, f = 200kHz, and f = 16 • f = 3.2MHz, u ..

AD9410BSQ
10-Bit, 210 MSPS A/D Converter
REV.0
10-Bit, 210 MSPS
A/D Converter
FUNCTIONAL BLOCK DIAGRAM
AIN
AIN
ENCODE
ENCODE
DFSI/P
REFINREFOUT
VDDDGNDVDAGNDVCC
ORA
D9A–D0A
DCO
ORB
D9B–D0B
DCO
FEATURES
SNR = 54 dB with 99 MHz Analog Input
500 MHz Analog Bandwidth
On-Chip Reference and Track/Hold
1.5 V p-p Differential Analog Input Range
5.0 V and 3.3 V Supply Operation
3.3 V CMOS/TTL Outputs
Power: 2.1 W Typical at 210 MSPS
Demultiplexed Outputs Each at 105 MSPS
Output Data Format Option
Data Sync Input and Data Clock Output Provided
Interleaved or Parallel Data Output Option
APPLICATIONS
Communications and Radar
Local Multipoint Distribution Service (LMDS)
High-End Imaging Systems and Projectors
Cable Reverse Path
Point-to-Point Radio Link
GENERAL DESCRIPTION
The AD9410 is a 10-bit monolithic sampling analog-to-digital
converter with an on-chip track-and-hold circuit and is opti-
mized for high-speed conversion and ease of use. The product
operates at a 210 MSPS conversion rate, with outstanding
dynamic performance over its full operating range.
The ADC requires a 5.0 V and 3.3 V power supply and up to a
210 MHz differential clock input for full performance operation.
No external reference or driver components are required for many
applications. The digital outputs are TTL/CMOS-compatible,
and separate output power supply pins also support interfacing
with 3.3 V logic.
The clock input is differential and TTL/CMOS-compatible. The
10-bit digital outputs can be operated from 3.3 V (2.5 V to 3.6 V)
supplies. Two output buses support demultiplexed data up to
105 MSPS rates, and binary or two’s complement output coding
format is available. A data sync function is provided for timing-
dependent applications. An output clock simplifies interfacing to
external logic. The output data bus timing is selectable for parallel
or interleaved mode, allowing for flexibility in latching output data.
Fabricated on an advanced BiCMOS process, the AD9410
is available in an 80-lead surface-mount plastic package
(PowerQuad®2) specified over the industrial temperature range
(–40°C to +85°C).
PowerQuad is a registered trademark of Amkor Electronics, Inc.
PRODUCT HIGHLIGHTS
High Resolution at High Speed—The architecture is specifically
designed to support conversion up to 210 MSPS with outstand-
ing dynamic performance.
Demultiplexed Output—Output data is decimated by two and
provided on two data ports for ease of data transport.
Output Data Clock—The AD9410 provides an output data
clock synchronous with the output data, simplifying the timing
between data and other logic.
Data Synchronization—A DS input is provided to allow for
synchronization of two or more AD9410s in a system, or
to synchronize data to a specific output port in a single
AD9410 system.
AD9410–SPECIFICATIONS
DC SPECIFICATIONS
NOTES
1Package heat slug should be attached when operating at greater than 70°C ambient temperature.
2Encode = 210 MSPS, AIN = –0.5 dBFS 10 MHz sine wave, IVDD = 31 mA typical at CLOAD = 5 pF.
3Encode = 210 MSPS, AIN = dc, outputs not switching.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
(VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = –0.5 dBFS; Clock
input = 210 MSPS; TA = 25�C; unless otherwise noted.)
(VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = –0.5 dBFS; Clock input = 210 MSPS;
TA = 25�C; unless otherwise noted.)
AD9410
DIGITAL SPECIFICATIONS
NOTESI/P pin Logic “1” = 5 V, Logic “0” = GND. It is recommended to place a series 2.5 kΩ (±10%) resistor to VDD when setting to Logic “1” to limit input current.See Encode Input section in Applications section.
Specifications subject to change without notice.
AC SPECIFICATIONS
(VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = –0.5 dBFS;
Clock input = 210 MSPS; TA = 25�C; unless otherwise noted.)
(VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = –0.5 dBFS; Clock input = 210 MSPS;
TA = 25�C; unless otherwise noted.)
AD9410
ORDERING GUIDE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9410 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
EXPLANATION OF TEST LEVELS
Test Level100% production tested.
II.100% production tested at 25°C and sample tested at
specified temperatures.
III.Sample tested only.
IV.Parameter is guaranteed by design and characterization
testing.Parameter is a typical value only.
VI.100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range.
ABSOLUTE MAXIMUM RATINGS1
VD, VCC, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . 0 V to VCC + 0.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . 0 V to VDD + 0.5 V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VD + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature2 . . . . . . . . . . . . . . . . 150°C
NOTESAbsolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability. Stresses
above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions outside of those indicated in the operation sections
of this specification is not implied.Typical θJA = 22°C/W (heat slug not soldered), typical θJA = 16°C/W (heat slug
soldered), for multilayer board in still air with solid ground plane.
AD9410
PIN FUNCTION DESCRIPTIONS
25, 26, 31, 32, 69, 70, 75, 76
61–65
PIN CONFIGURATION
AGND
AGND
VCC
REFOUT
REFIN
DNC
VCC
AGND
AGND
AIN
AIN
AGND
AGND
VCC
VCC
AGND
AGND
ENCODE
ENCODE
AGND
AGNDDS
AGND
AGNDAGNDAGNDAGND
DGND
(LSB) D
DGND
VDD
DB5
DB6
DB7
DB8
DB9 (MSB)
ORB
VDD
DGND
DCO
DCO
DGND
VDD
DA0 (LSB)
DA1
DA2
DA3
DA4
DGND
VDD
A9
(MSB)
DGNDV
AGNDAGNDAGNDAGNDV
AGNDAGNDDFSI/P
DNC � DO NOT CONNECT
AD9410
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog
input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci-
tance and differential input impedances are measured with a
network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to the
converter to generate a full-scale response. Peak differential voltage
is computed by observing the voltage on a single pin and subtract-
ing the voltage from the other pin, which is 180 degrees out of
phase. Peak-to-peak differential is computed by rotating the
inputs phase 180 degrees and taking the peak measurement
again. The difference is then computed between both peak
measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits
The effective number of bits (ENOB) is calculated from the
measured SINAD based on the equation.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic 1 state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. See timing implica-
tions of changing tENCH in text. At a given clock rate, these specs
define an acceptable ENCODE duty cycle.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog
signal frequency drops by no more than 3 dB below the
guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Out-of-Range Recovery Time
Out-of-range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.
Noise (For Any Range Within the ADC)
Where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value for the particular
input level, and SIGNAL is the signal level within the ADC
reported in dB below full scale. This value includes both thermal
and quantization noise.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 0.5 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics, but excluding dc.
Signal-to-Noise Ratio (Without Harmonics)
The ratio of the rms signal amplitude (set at 0.5 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered), or dBFS (always
related back to converter full scale).
Transient Response Time
Transient response time is defined as the time it takes for the
ADC to reacquire the analog input after a transient from 10%
above negative full scale to 10% below positive full scale.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).
Figure 2.Equivalent Analog Input Circuit
Figure 3.Equivalent Reference Input Circuit
Figure 4Equivalent Encode Input Circuit
Table I.Output Coding (VREF = 2.5 V)
Figure 6.Equivalent Reference Output Circuit
Figure 7.Equivalent DFS Input Circuit
Figure 8.Equivalent DS Input Circuit
AD9410
TPC 1.Single Tone at 40 MHz, Encode = 210 MSPS
TPC 2.Single Tone at 100 MHz, Encode = 210 MSPS
TPC 3.Single Tone at 160 MHz, Encode = 210 MSPS
–Typical Performance Characteristics
TPC 4.SNR/SINAD vs. AIN Encode = 210 MSPS
MHz
SNR
SINAD
180220
TPC 5.SNR/SINAD vs. FS AIN = 70 MHz
TPC 6.SNR/SINAD vs. Encode Positive Pulsewidth
(FS = 210 MSPS, AIN = 70 MHz)

Partno	Mfg	Dc	Qty	Available	Descript
AD9410BSQ	ADI	N/a	40	avai	10-Bit, 210 MSPS A/D Converter