AD9300KQ ,4 x 1 Wideband Video Multiplexerapplications. This part is also available pro-high-impedance state when the chip is not enabled; wh ..
AD9381KSTZ-150 , HDMI Display Interface
AD9389B ,High Performance HDMI®/DVI TransmitterFEATURES FUNCTIONAL BLOCK DIAGRAM SCL SDA MCL MDA INTGeneral HDMI/DVI transmitter compatible with H ..
AD9389BBSTZ-165 , High Performance HDMI/DVI Transmitter
AD9410BSQ ,10-Bit, 210 MSPS A/D ConverterSPECIFICATIONSATestParameter Temp Level Min Typ Max UnitRESOLUTION 10 BitsDC ACCURACY1No Missing Co ..
AD9411BSV-170 ,10-Bit, 170/200 MSPS 3.3 V A/D ConverterGENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9411 is a 10-bit monolithic sampling analog-to-digital ..
ADS7835EB ,Brown Corporation - 12-Bit, High-Speed, Low Power Sampling ANALOG-TO-DIGITAL CONVERTER
ADS7841 ,12-Bit, 4-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTERELECTRICAL CHARACTERISTICS: +5VAt T = T to T , +V = +5V, V = +5V, f = 200kHz, and f = 16 • f = 3.2 ..
ADS7841E ,12-Bit/ 4-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTERMaximum Ratings”may cause permanent damage to the device. Exposure to absolute maximumto complete d ..
ADS7841E . ,12-Bit/ 4-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTERELECTRICAL CHARACTERISTICS: +5VAt T = T to T , +V = +5V, V = +5V, f = 200kHz, and f = 16 • f = 3.2 ..
ADS7841E/2K5G4 ,12-Bit, 4-Channel Serial Output Sampling Analog-to-Digital Converter 16-SSOP -40 to 85FEATURES* SINGLE SUPPLY: 2.7V to 5VThe ADS7841 is a 4-channel, 12-bit sampling Analog-to-Digital Co ..
ADS7841EB ,12-Bit/ 4-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTERMaximum Ratings”may cause permanent damage to the device. Exposure to absolute maximumto complete d ..
AD9300-AD9300KP-AD9300KQ
4 x 1 Wideband Video Multiplexer
REV.A
4 × 1 Wideband
Video Multiplexer
FUNCTIONAL BLOCK DIAGRAM
(Based on Cerdip)
FEATURES
34 MHz Full Power Bandwidth60.1 dB Gain Flatness to 8 MHz
72 dB Crosstalk Rejection @ 10 MHz
0.038/0.01% Differential Phase/Gain
Cascadable for Switch Matrices
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Video Routing
Medical Imaging
Electro Optics
ECM Systems
Radar Systems
Data Acquisition
GENERAL DESCRIPTIONThe AD9300 is a monolithic high speed video signal multiplexer
usable in a wide variety of applications.
Its four channels of video input signals can be randomly
switched at megahertz rates to the single output. In addition,
multiple devices can be configured in either parallel or cascade
arrangements to form switch matrices. This flexibility in using
the AD9300 is possible because the output of the device is in a
high-impedance state when the chip is not enabled; when the
chip is enabled, the unit acts as a buffer with a high input im-
pedance and low output impedance.
An advanced bipolar process provides fast, wideband switching
capabilities while maintaining crosstalk rejection of 72 dB at
10 MHz. Full power bandwidth is a minimum 27 MHz. The
device can be operated from ±10 V to ±15 V power supplies.
PIN DESIGNATIONS
DIPLCC and PLCCThe AD9300K is available in a 16-pin ceramic DIP and a
20-pin PLCC and is designed to operate over the commercial
temperature range of 0°C to +70°C. The AD9300TQ is a
hermetic 16-pin ceramic DIP for military temperature range
(–55°C to +125°C) applications. This part is also available pro-
cessed to MIL-STD-883. The AD9300 is available in a 20-pin
LCC as the model AD9300TE, which operates over a tempera-
ture range of –55°C to +125°C.
The AD9300 Video Multiplexer is available in versions compli-
ant with MIL-STD-883. Refer to the Analog Devices Military
Products Databook or current AD9300/883B data sheet for de-
tailed specifications.
POWER SUPPLY
AD9300–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS(6VS = 612 V 6 5%; CL = 10 pF; RL = 2 kV, unless otherwise noted)
NOTESPermanent damage may occur if any one absolute maximum rating is exceeded. Functional operation is not implied, and device reliability may be impaired by
exposure to higher-than-recommended voltages for extended periods of time.Measured at extremes of temperature range.Measured as slope of VOUT versus VIN with VIN = ±1 V.Measured as worst deviation from endpoint fit with VIN = ±1 V.Full Power Bandwidth (FPBW) based on Slew Rate (SR). FPBW = SR/2π VPEAKMeasured between 20% and 80% transition points of ±1 V output.T-Step = Sin2 × Step, when Step between 0 V and +700 mV points has 10% to 90% risetime = 125 ns.Measured with a pulse input having slew rate >250 V/μs.Measured at output between 0.28 V dc and 1.0 V dc with VIN = 284 mV p-p at 3.58 MHz and 4.43 MHz.This specification is critically dependent on circuit layout. Value shown is measured with selected channel grounded and 10 MHz 2 V p-p signal applied to remaining
three channels. If selected channel is grounded through 75 Ω, value is approximately 6 dB higher.This specification is critically dependent on circuit layout. Value shown is measured with selected channel grounded and 10 MHz 2 V p-p signal applied to one other
channel. If selected channel is grounded through 75 Ω, value is approximately 6 dB higher. Minimum specification in ( ) applies to DIPs.Consult system timing diagram.Measured from address change to 90% point of –2 V to +2 V output LOW-to-HIGH transition.Measured from address change to 90% point of +2 V to –2 V output HIGH-to-LOW transition.Measured from 50% transition point of ENABLE input to 90% transition of 0 V to –2 V and 0 V to +2 V output.Measured from 50% transition point of ENABLE input to 10% transition of +2 V to 0 V and –2 V to 0 V output.Measured while switching between two grounded channels.Maximum power dissipation is a package-dependent parameter related to the following typical thermal impedances:
16-Pin CeramicθJA = 87°C/W; θJC = 25°C/W
20-Pin LCCθJA = 74°C/W; θJC = 10°C/W
20-Pin PLCCθJA = 71°C/W; θJC = 26°C/W
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGSlSupply Voltages (±VS) . . . . . . . . . . . . . . . . . . . . . . . . . .±16 V
Analog Input Voltage Each Input
(IN1 thru IN4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.5 V
Differential Voltage Between Any Two
Inputs (IN1 thru IN4) . . . . . . . . . . . . . . . . . . . . . . . . . . .5 V
Digital Input Voltages (A0, A1, ENABLE) . . .–0.5 V to +5.5 V
Output Current
Sinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.0 mA
Sourcing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.0 mA
Operating Temperature Range
AD9300KQ/KP . . . . . . . . . . . . . . . . . . . . . . .0°C to +70°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Lead Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . .+300°C
EXPLANATION OF TEST LEVELSTest Level I–100% production tested.
Test Level II–100% production tested at +25°C, and
sample tested at specified temperatures.
Test Level III–Sample tested only.
Test Level IV–Parameter is guaranteed by design and
characterization testing.
Test Level V–Parameter is a typical value only.
Test Level VI–All devices are 100% production tested at
+25°C. 100% production tested at tempera-
ture extremes for military temperature de-
vices; sample tested at temperature extremes
for commercial/industrial devices.
AD9300
ORDERlNG GUlDENOTESE = Ceramic Leadless Chip Carrier; P = Plastic Leaded Chip Carrier; Q = Cerdip.For specifications, refer to Analog Devices Military Products Databook.
WARNING!
ESD SENSITIVE DEVICE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9300 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
AD9300
SUGGESTED LAYOUT OF AD9300
PC BOARD
AD9300 BURN-IN DIAGRAM
METALIZATION PHOTOGRAPH
MECHANICAL INFORMATIONDie Dimensions . . . . . . . . . . . . . . . . .84 × 104 × 18 (max) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . .4 × 4 (min) mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Oxynitride
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Gold Eutectic
Bond Wire . . . . . . . .1.25 mil, Aluminum; Ultrasonic Bonding
or 1 mil, Gold; Gold Ball Bonding
LOGIC TRUTH TABLE
FUNCTIONAL DESCRIPTIONIN1–IN4Four analog input channels.
GROUNDAnalog input shielding grounds, not internally con-
nected. Connect each to external low-impedance
ground as close to device as possible.One of two TTL decode control lines required for
channel selection. See Logic Truth Table.One of two TTL decode control lines required for
channel selection. See Logic Truth Table.
ENABLETTL-compatible chip enable. In enabled mode
(logic HIGH), output signal tracks selected input
channel; in disabled mode (logic LOW), output is
high impedance and no signal appears at output.
–VSNegative supply voltage; normally –10 V dc to
–15 V dc.
+VSPositive supply voltage; normally +10 V dc to
+15 V dc.
OUTPUTAnalog output. Tracks selected input channel when
enabled.
BYPASSBypass terminal for internal bias line; must be
decoupled externally to ground through 0.1 μF
capacitor.
GROUNDAnalog signal and power supply ground return.
RETURN
THEORY OF OPERATIONRefer to the functional block diagram of the AD9300.
As shown in the drawing, this diagram is based on the pinouts of
the DIP packaging of the models AD9300KQ and AD9300TQ.
The AD9300KP and AD9300TE are packaged in 20-pin surface
mount packages. The extra pins are used for ground connections;
the theory of operation remains the same.
The AD9300 Video Multiplexer allows the user to connect any
one of four analog input channels (IN1–IN4) to the output of the
device and to switch between channels at megahertz rates.
The input channel, which is connected to the output is deter-
mined by a 2-bit TTL digital code applied to A0 and A1. The se-
lected input will not appear at the output unless a digital “1” is
also applied to the ENABLE input pin; unless the output is
enabled, it is a high impedance. Necessary combinations to ac-
complish channel selection are shown in the Logic Truth Table.
Figure 1.Input and Output Equivalent Circuits
Bipolar construction used in the AD9300 ensures that the input
impedance of the device remains high and will not vary with
power supply voltages. This characteristic makes the AD9300,
in effect, a switchable-input buffer. An onboard bias network
makes the performance of the AD9300 independent of applied
supply voltages, which can have any nominal value from
±10 V dc to ±15 V dc.
Although the primary application for the AD9300 is the routing
of video signals, the harmonic and dynamic attributes of the
device make it appropriate for other applications. The AD9300
has exceptional performance when switching video signals and
can also be used for switching other analog signals requiring
greater dynamic range and/or precision than those in video.
As shown in Figure 1, each analog input is connected to the
base of a bipolar transistor. If Channel 1 is selected, a current
switch is closed and routes current through the input transistor
for Channel 1.
If Channel 2 is then selected by the digital inputs, the current
switch for Channel 1 is opened and the current switch for Chan-
nel 2 is closed. This causes current to be routed away from the
Channel 1 transistor and into the Channel 2 input transistor.
Whenever a channel’s input device is carrying current, the ana-
log input applied to that channel is passed to the output stage.
The operation of the output stage is similar to that of the input
stages. Whenever the output stage is enabled with a HIGH digi-
tal “1” signal at the ENABLE pin, the output transistor will
carry current and pass the selected analog input.
When the output stage is disabled (by virtue of the ENABLE
pin being driven LOW with a digital “0”), the output current
switch is opened. This routes the current to other circuits within
the AD9300 that keep the output transistor biased “off.” These
circuits require approximately 1 μA of bias current from the load
connected to the output of the multiplexer. In the absence of a
terminating load and the resulting dc bias, the output of the
AD9300 “floats” at –2.5 V.
In summary, when the AD9300 is enabled by the ENABLE pin
being driven HIGH with a digital “1,” the selected analog input
channel acts as a buffer for the input and the output of the mul-
tiplexer is a low impedance. When the AD9300 is disabled with
a digital “0” LOW signal, the selected channel acts as an open
switch for the input, and the output of the unit becomes a high
impedance. This characteristic allows the user to wire-or several
AD9300 Analog Multiplexers together to form switch matrices.
AD9300
AD9300 APPLICATIONSTo ensure optimum performance from circuits using the AD9300,
it is important to follow a few basic rules that apply to all high
speed devices.
A large, low-impedance ground plane under the AD9300 is
critical. Generally, GROUND and GROUND RETURN con-
nections should be connected solidly to this plane. GROUND
pin connections are signal isolation grounds that are not
Figure 2.4 x 1 AD9300 Multiplexer with Buffered Output
Driving 75 Ω Coaxial Cable
Figure 4.Output vs. FrequencyFigure 3.Harmonic Distortion vs.
Frequency
Figure 5.Crosstalk vs. Frequency
connected internally; they can be left unconnected, but there
may be some degradation in crosstalk rejection. GROUND RE-
TURN, on the other hand, serves as the internal ground refer-
ence for the AD9300 and, without exception, should be
connected to the ground plane.
The output stage of the unit is capable of driving a 2 kΩi10 pF
load. Larger capacitive loads may limit full power bandwidth
and increase tOFF (the interval between the 50% point of the
ENABLE high-to-low transition and the instant the output
becomes a high impedance).
For applications such as driving cables (see Figure 2), output
buffers are recommended.
It is recommended that the AD9300 be soldered directly into
circuit boards rather than using socket assemblies. If sockets
must be used, individual pin sockets are preferred rather than a
socket assembly. A second requirement for proper high speed
design involves decoupling the power supply and
internal bias supply lines from ground to improve noise immu-
nity. Chip capacitors are recommended for connecting 0.1 μF
and 0.01 μF capacitors between ground and the ±VS supplies
(Pins 9 and 14) and the BYPASS connection (Pin 15).
