AD9281ARS ,Dual Channel 8-Bit Resolution CMOS ADCSPECIFICATIONS unless otherwise noted)Parameter Symbol Min Typ Max Units ConditionRESOLUTION 8 Bits ..
AD9281ARSZ , Dual Channel 8-Bit Resolution CMOS ADC
AD9283BRS-100 ,8-Bit, 50 MSPS/80 MSPS/100 MSPS 3 V A/D ConverterSPECIFICATIONS (V = 3.0 V, V = 3.0 V; single-ended input; external reference, unless otherwise note ..
AD9283BRS-100 ,8-Bit, 50 MSPS/80 MSPS/100 MSPS 3 V A/D ConverterGENERAL DESCRIPTION The encoder input is TTL/CMOS compatible. A power-downThe AD9283 is an 8-bit mo ..
AD9283BRS-50 ,8-Bit, 50 MSPS/80 MSPS/100 MSPS 3 V A/D ConverterSpecifications subject to change without notice.*Stresses above those listed under Absolute Maximum ..
AD9283BRS-80 ,8-Bit, 50 MSPS/80 MSPS/100 MSPS 3 V A/D ConverterFEATURES FUNCTIONAL BLOCK DIAGRAM8-Bit, 50, 80 and 100 MSPS ADCLow Power: 90 mW at 100 MSPS V PWRDW ..
ADS7828EB/250 ,12-Bit 50 kSPS ADC I2C Low Power 8-Channel MUX Int 2.5V Ref®ADS7828ADS7828SBAS181C – NOVEMBER 2001 - REVISED MARCH 200512-Bit, 8-Channel SamplingANALOG-TO-DIG ..
ADS7828EB/250G4 ,12-Bit, 8-Channel SAR ADC with Internal Reference and I2C Interface 16-TSSOP -40 to 85ELECTRICAL CHARACTERISTICS: +2.7VAt T = –40°C to +85°C, +V = +2.7V, V = +2.5V, SCL Clock Frequency ..
ADS7828EB/2K5 ,12-Bit 50 kSPS ADC I2C Low Power 8-Channel MUX Int 2.5V Ref.PIN DESCRIPTIONSPIN CONFIGURATIONPIN NAME DESCRIPTIONTop View TSSOP1 CH0 Analog Input Channel 02 C ..
ADS7828EIPWRQ1 ,Automotive 12-Bit 50 kSPS ADC I2C Low Power 8-Channel MUX Int 2.5V Ref 16-TSSOP -40 to 85 SBAS456B–DECEMBER 2008–REVISED JANUARY 20165 Pin Configuration and FunctionsPW Package16-Pin TSSOP ..
ADS7828EIPWRQ1 ,Automotive 12-Bit 50 kSPS ADC I2C Low Power 8-Channel MUX Int 2.5V Ref 16-TSSOP -40 to 85features a sample-and-holdamplifier and internal asynchronous clock. The• No Missing Codes2combinat ..
ADS7829IBDRBR ,12-Bit High Speed 2.7V microPower Sampling Analog-to-Digital ConverterSLAS388JUNE 2003These devices have limited built-in ESD protection. The leads should be shorted to ..
AD9281ARS
Dual Channel 8-Bit Resolution CMOS ADC
REV.E
Dual Channel 8-Bit
Resolution CMOS ADC
FEATURES
Complete Dual Matching ADC
Low Power Dissipation: 225 mW (+3 V Supply)
Single Supply: 2.7 V to 5.5 V
Differential Nonlinearity Error: 0.1 LSB
On-Chip Analog Input Buffers
On-Chip Reference
Signal-to-Noise Ratio: 49.2 dB
Over Seven Effective Bits
Spurious-Free Dynamic Range: –65 dB
No Missing Codes Guaranteed
28-Lead SSOP
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTIONThe AD9281 is a complete dual channel, 28 MSPS, 8-bit
CMOS ADC. The AD9281 is optimized specifically for applica-
tions where close matching between two ADCs is required (e.g.,
I/Q channels in communications applications). The 28 MHz
sampling rate and wide input bandwidth will cover both narrow-
band and spread-spectrum channels. The AD9281 integrates
two 8-bit, 28 MSPS ADCs, two input buffer amplifiers, an internal
voltage reference and multiplexed digital output buffers.
Each ADC incorporates a simultaneous sampling sample-and-
hold amplifier at its input. The analog inputs are buffered; no
external input buffer op amp will be required in most applica-
tions. The ADCs are implemented using a multistage pipeline
architecture that offers accurate performance and guarantees no
missing codes. The outputs of the ADCs are ported to a multi-
plexed digital output buffer.
The AD9281 is manufactured on an advanced low cost CMOS
process, operates from a single supply from 2.7 V to 5.5 V, and
consumes 225 mW of power (on 3 V supply). The AD9281
input structure accepts either single-ended or differential signals,
providing excellent dynamic performance up to and beyond
14 MHz Nyquist input frequencies.
PRODUCT HIGHLIGHTSDual 8-Bit, 28 MSPS ADC
A pair of high performance 28 MSPS ADCs that are opti-
mized for spurious free dynamic performance are provided for
encoding of I and Q or diversity channel information.Low Power
Complete CMOS Dual ADC function consumes a low
225 mW on a single supply (on 3 V supply). The AD9281
operates on supply voltages from 2.7 V to 5.5 V.On-Chip Voltage Reference
The AD9281 includes an on-chip compensated bandgap
voltage reference pin programmable for 1 V or 2 V.On-chip analog input buffers eliminate the need for external
op amps in most applications.Single 8-Bit Digital Output Bus
The AD9281 ADC outputs are interleaved onto a single
output bus saving board space and digital pin count.Small Package
The AD9281 offers the complete integrated function in a
compact 28-lead SSOP package.Product Family
The AD9281 dual ADC is pin compatible with a dual 10-bit
ADC (AD9201).
AD9281–SPECIFICATIONS
(AVDD = +3 V, DVDD = +3 V, FSAMPLE = 28 MSPS, VREF = 2 V, INB = 0.5 V, TMIN to TMAX
unless otherwise noted)
AD9281DIGITAL INPUTS
NOTESSE is single ended input, REFT = 1.5 V, REFB = –0.5 V.AIN differential 2 V p-p, REFT = 1.5 V, REFB = –0.5 V.IMD referred to larger of two input signals.
Specifications subject to change without notice.
CLOCK
INPUT
SELECT
INPUT
DATA
OUTPUT
ADC SAMPLE
ADC SAMPLE
SAMPLE #1-1
SAMPLE #1
Q CHANNEL
OUTPUT
SAMPLE #1
SAMPLE #2
Q CHANNEL
OUTPUT
tOD
AD9281
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
PIN CONFIGURATION
NC = NO CONNECT
ABSOLUTE MAXIMUM RATINGS**Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
ORDERING GUIDE*RS = Shrink Small Outline.
PIN FUNCTION DESCRIPTIONS
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale.” The
point used as “zero” occurs 1/2 LSB before the first code transi-
tion. “Full scale” is defined as a level 1 1/2 LSBs beyond the last
code transition. The deviation is measured from the center of
each particular code to the true straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of the resolution for which no missing codes
(NMC) are guaranteed.
DRVDD
AVSS
DRVSS
DRVSS
AVDD
AVDD
AVSS
AVSS
AVDD
REFBS
REFBF
AVDD
AVDD
AVSS
AVDD
AVSS
AVDD
AVSS
AVDD
AVSS
AVSS
AVDD
AVDD
AVSS
AVDD
AVSSINA, INBe.Referencef.REFSENSEg.VREF
Figure 2.Equivalent Circuits
OFFSET ERRORThe first transition should occur at a level 1 LSB above “zero.”
Offset is defined as the deviation of the actual first code transi-
tion from that point.
OFFSET MATCHThe change in offset error between I and Q channels.
EFFECTIVE NUMBER OF BITS (ENOB)For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
It is possible to get a measure of performance expressed as N,
the effective number of bits.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
TOTAL HARMONIC DISTORTION (THD)THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and
is expressed as a percentage or in decibels.
SIGNAL-TO-NOISE RATIO (SNR)SNR is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
scale. Gain error is the deviation of the actual difference be-
tween first and last code transitions and the ideal difference
between the first and last code transitions.
GAIN MATCHThe change in gain error between I and Q channels.
PIPELINE DELAY (LATENCY)The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every rising clock edge.
MUX SELECT DELAYThe delay between the change in SELECT pin data level and
valid data on output pins.
POWER SUPPLY REJECTIONThe specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
APERTURE JITTERAperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
APERTURE DELAYAperture delay is a measure of the Sample-and-Hold Amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIOS/N+D is the ratio of the rms value of the measured input sig-
nal to the rms sum of all other spectral components below
a.D0–D9 b.Three-State Standby c.CLK
AD9281
–Typical Characteristic Curves
(AVDD = +3 V, DVDD = +3 V, FS = 28 MHz (50% duty cycle), 2 V input span from –0.5 V to +1.5 V, 2 V internal reference unless otherwise noted)
CODE OFFSET0
LSB03248648096112128144160176192208224240Figure 3.Typical INL
CODE OFFSET0
LSB03248648096112128144160176192208224240Figure 4.Typical DNL
Figure 5.Input Bias Current vs. Input Voltage
INPUT FREQUENCY – Hz
1.0E+05
SNR – dB
1.0E+061.0E+071.0E+08Figure 6.SNR vs. Input Frequency
INPUT FREQUENCY – Hz
1.0E+05
SNR – dB
1.0E+061.0E+071.0E+08Figure 7.SINAD vs. Input Frequency
INPUT FREQUENCY – Hz
1.0E+05
THD – dB
1.0E+061.0E+071.0E+08
–70Figure 8.THD vs. Input Frequency
CLOCK FREQUENCY – Hz
1.00E+061.00E+081.00E+07
THD – dBFigure 9.THD vs. Clock Frequency
TEMPERATURE – 8C
REF
– Volts
1.009Figure 10.Voltage Reference Error vs. Temperature
CLOCK FREQUENCY – MHz
POWER CONSUMPTION – mW1216202428
195Figure 11.Power Consumption vs. Clock Frequency
CODE
1.20E+07
1.00E+07
0.00E+00
N+1N–1
HITS
8.00E+06
6.00E+06
4.00E+06
2.00E+06Figure 12.Grounded Input Histogram
Figure 13.Full Power Bandwidth
INPUT FREQUENCY – Hz
1.00E+05
SNR – dB
1.00E+061.00E+071.00E+08Figure 14.SNR vs. Input Frequency (Single-Ended)
AD9281
THEORY OF OPERATIONThe AD9281 integrates two A/D converters, two analog input
buffers, an internal reference and reference buffer, and an out-
put multiplexer. For clarity, this data sheet refers to the two
converters as “I” and “Q.” The two A/D converters simulta-
neously sample their respective inputs on the rising edge of the
input clock. The two converters distribute the conversion opera-
tion over several smaller A/D sub-blocks, refining the conversion
with progressively higher accuracy as it passes the result from
stage to stage. As a consequence of the distributed conversion,
each converter requires a small fraction of the 256 comparators
used in a traditional flash-type 8-bit ADC. A sample-and-hold
function within each of the stages permits the first stage to oper-
ate on a new input sample while the following stages continue to
process previous samples. This results in a “pipeline processing”
latency of three clock periods between when an input sample is
taken and when the corresponding ADC output is updated into
the output registers.
The AD9281 integrates input buffer amplifiers to drive the
analog inputs of the converters. In most applications, these
input amplifiers eliminate the need for external op amps for the
input signals. The input structure is fully differential, but the
SHA common-mode response has been designed to allow the
converter to readily accommodate either single-ended or differ-
ential input signals. This differential structure makes the part
capable of accommodating a wide range of input signals.
The AD9281 also includes an on-chip bandgap reference and
reference buffer. The reference buffer shifts the ground-referred
reference to levels more suitable for use by the internal circuits
of the converter. Both converters share the same reference and
reference buffer. This scheme provides for the best possible gain
match between the converters while simultaneously minimizing
the channel-to-channel crosstalk.
Each A/D converter has its own output latch, which updates on
the rising edge of the input clock. A logic multiplexer, con-
trolled through the SELECT pin, determines which channel is
passed to the digital output pins. The output drivers have their
own supply, allowing the part to be interfaced to a variety of
logic families. The outputs can be placed in a high impedance
state using the CHIP SELECT pin.
The AD9281 has great flexibility in its supply voltage. The
analog and digital supplies may be operated from 2.7 V to 5.5 V,
independently of one another.
ANALOG INPUTFigure 16 shows an equivalent circuit structure for the analog
input of one of the A/D converters. PMOS source-followers
buffer the analog input pins from the charge kickback problems
normally associated with switched capacitor ADC input struc-
tures. This produces a very high input impedance on the part,
allowing it to be effectively driven from high impedance sources.
This means that the AD9281 could even be driven directly by a
passive antialias filter.
Figure 16.Equivalent Circuit for AD9281 Analog Inputs
The source followers inside the buffers also provide a level-shift
function of approximately 1 V, allowing the AD9281 to accept
inputs at or below ground. One consequence of this structure is
that distortion will result if the analog input comes within 1.4 V
of the positive supply. For optimum high frequency distortion
performance, the analog input signal should be centered accord-
ing to Figure 27.
The capacitance load of the analog input pin is 4 pF to the
analog supplies (AVSS, AVDD).
Full-scale setpoints may be calculated according to the following
algorithm (VREF may be internally or externally generated):
0.0E+0
SNR – dB
2.0E+64.0E+66.0E+68.0E+610.0E+612.0E+614.0E+6Figure 15a.Simultaneous Operation of I and Q Channels
0.0E+0
SNR – dB
2.0E+64.0E+66.0E+68.0E+610.0E+612.0E+614.0E+6Figure 15b.Simultaneous Operation of I and Q Channels
The AD9281 can accommodate a variety of input spans be-
tween 1 V and 2 V. For spans of less than 1 V, expect a propor-
tionate degradation in SNR. Use of a 2 V span will provide the
best noise performance. 1 V spans will provide lower distortion
when using a 3 V analog supply. Users wishing to run with larger
full-scales are encouraged to use a 5 V analog supply (AVDD).
Single-Ended Inputs: For single-ended input signals, thesignal is applied to one input pin and the other input pin is tied
to a midscale voltage. This midscale voltage defines the center
of the full-scale span for the input signal.
EXAMPLE: For a single-ended input range from 0 V to 1 V
applied to IINA, we would configure the converter for a 1 V
reference (see Figure 17) and apply 0.5 V to IINB.
Figure 17.Example Configuration for 0 V–1 V Single-
Ended Input Signal
Note that since the inputs are high impedance, this reference
level can easily be generated with an external resistive divider
with large resistance values (to minimize power dissipation). A
decoupling capacitor is recommended on this input to minimize
the high frequency noise-coupling onto this pin. Decoupling
should occur close to the ADC.
Differential InputsUse of differential input signals can provide greater flexibility in
input ranges and bias points, as well as offering improvements in
distortion performance, particularly for high frequency input
signals. Users with differential input signals will probably want
to take advantage of the differential input structure of the AD9281.
Performance is still very good for single-ended inputs. Convert-
ing a single-ended input to a differential signal for application to
the converter is probably only worth considering for very high
frequency input signals.
AC-Coupled InputsIf the signal of interest has no dc component, ac coupling can be
easily used to define an optimum bias point. Figure 18 illustrates
one recommended configuration. The voltage chosen for the dc
bias point (in this case the 1 V reference) is applied to both
IINA and IINB pins through 1 kΩ resistors (R1 and R2). IINA
is coupled to the input signal through Capacitor C1, while IINB is
decoupled to ground through Capacitor C2.
Figure 18.Example Configuration for 0.5 V–1.5 V ac
Coupled Single-Ended Inputs
Transformer Coupled InputsAnother option for input ac coupling is to use a transformer.
This not only provides dc rejection, but also allows truly differ-
ential drive of the AD9281’s analog inputs, which will provide
the optimal distortion performance. Figure 19 shows a recom-
mended transformer input drive configuration. Resistors R1 and
R2 define the termination impedance of the transformer cou-
pling. The center tap of the transformer secondary is tied to the
common-mode voltage, establishing the dc bias point for the
analog inputs.
Figure 19.Example Configuration for Transformer
Coupled Inputs
Crosstalk: The internal layout of the AD9281, as well as itspinout, was configured to minimize the crosstalk between the
two input signals. Users wishing to minimize high frequency
crosstalk should take care to provide the best possible decoupling
for input pins (see Figure 20). R and C values will make a pole
dependant on antialiasing requirements. Decoupling is also
required on reference pins and power supplies (see Figure 21).
Figure 20.Input Loading
AD9281
REFERENCE AND REFERENCE BUFFERThe reference and buffer circuitry on the AD9281 is configured
for maximum convenience and flexibility. An illustration of the
equivalent reference circuit is show in Figure 26. The user can
select from five different reference modes through appropriate
pin-strapping (see Table I below). These pin strapping options
cause the internal circuitry to reconfigure itself for the appropri-
ate operating mode.
Table I.Table of Modes
1 V Mode (Figure 22)—provides a 1 V reference and 1 V inputfull scale. Recommended for applications wishing to optimize
high frequency performance, or any circuit on a supply voltage
of less than 4 V. The part is placed in this mode by shorting the
REFSENSE pin to the VREF pin.
Figure 22.0 V to 1 V Input
2 V Mode (Figure 23)—provides a 2 V reference and 2 V inputfull scale. Recommended for noise sensitive applications on 5 V
supplies. The part is placed in 2 V reference mode by ground-
ing (shorting to AVSS) the REFSENSE pin.
Figure 23.0 V to 2 V Input
Externally Set Voltage Mode (Figure 24)—this mode usesthe on-chip reference, but scales the exact reference level though
the use of an external resistor divider network. VREF is wired to
the top of the network, with the REFSENSE wired to the tap
point in the resistor divider. The reference level (and input full
scale) will be equal to 1 V · (R1 + R2)/R1. This method can be
used for voltage levels from 0.7 V to 2.5 V.
0.1mF
0.1mF
1mF
VREF = 1 +Figure 24.Programmable Reference
External Reference Mode (Figure 25)—in this mode, the on-chip reference is disabled, and an external reference applied to
the VREF pin. This mode is achieved by tying the REFSENSE
pin to AVDD.
Figure 25.External Reference
Reference Buffer—The reference buffer structure takes thevoltage on the VREF pin and level-shifts and buffers it for use
by various sub-blocks within the two A/D converters. The two
converters share the same reference buffer amplifier to maintain
the best possible gain match between the two converters. In the
interests of minimizing high frequency crosstalk, the buffered
references for the two converters are separately decoupled on
the IREFB, IREFT, QREFB and QREFT pins, as illustrated in
Figure 26.
