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AD9269
16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
ANALOG
DEVICES
IB-Bit, 20/40/65/80 MSPS,
1.8V Dual Analog-to-Digital Converter
A08289
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Integrated quadrature error correction (QEC)
77.6 dBFS at 9.7 MHz input
71 dBFS at 200 MHz input
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input
Low power
44 mW per channel at 20 MSPS
100 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = -0.5/+T .1 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer (DCS)
lnteger1-to-6input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock output (DCO) with programmable clock and
data alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX,TD-SCDMA
l/Q demodulation systems
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
Rev. 0
Information furnished by Analog Devics is believed to be accurate and reliable. However, no
msponsibilityisassumedbyAnalog Devkesfbritsustsnorfbranyinhingememsofpatentsorather
rights of third partiesthat may result from itsusa Spedfiotions subject to thangewithout notice No
license is granted by implication or otherwise under any patent or patent rights of Analog Davies.
Trademarks and registered trademarks arethe prrapertyaf their respective owners.
FUNCTIONAL BLOCK DIAGRAM
AVDD GND SDIO SCLK CSB
AD9269
VIN+A . PROGRAMMING DATA ”,5
VIN-A 1 i! 's
VREF O I
QUADRATURE
SENSE T, ERROR
MUX OPTION
CORRECTION
VCM . SELECT 1
OUTPUT BUFFER
DIVIDE DUTY CYCLE M D
1 TO 6 STABILIZER CONTROLS
CLK+ CLK- SYNC DCS PDWN DFS OEB
Figure l.
PRODUCT HIGHLIGHTS
1. The AD9269 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2. The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
3. An optional SPI selectable dc correction and quadrature
error correction (QEC) feature corrects for dc offset, gain,
and phase mismatches between the two channels.
4. A standard serial port interface (SP1) supports various
product features and functions, such as data output format-
ting, internal clock divider, power-down, DCO/data timing
and offset adjustments, and voltage reference modes.
5. The AD9269 is packaged in a 64-lead RoHS-compliant
LFCSP that is pin compatible with the AD9268 16-bit
ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC
the AD9231 12-bit ADC, the AD6659 12-bit baseband
diversity receiver, and the AD9204 IO-bit ADC, enabling a
simple migration path between IO-bit and l6-bit converters
sampling from 20 MSPS to 125 MSPS.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781 .329.4700
Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.
h08288
TABLE OF CONTENTS
Features m............................................................................................. 1
Applications _...................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights w.......................................................................... 1
Revision History F.............................................................................. 2
General Description P........................................................................ 3
Specifications F.................................................................................... 4
DC Specifications w........................................................................ 4
AC Specifications w......................................................................... 6
Digital Specifications B.................................................................. 7
Switching Specifications _............................................................. 8
Timing Specifications F................................................................. 9
Absolute Maximum Ratings _......................................................... 10
Thermal Characteristics M........................................................... 10
ESD Caution P............................................................................... 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 13
AD9269-80 _................................................................................. 13
AD9269-65 B................................................................................. 15
AD9269-40 _................................................................................. 16
AD9269-20 B................................................................................. 17
Equivalent Circuits W........................................................................ 18
Theory of Operation _..................................................................... 19
ADC Architecture ...................................................................... 19
Analog Input Considerations w................................................... 19
Voltage Reference F...................................................................... 21
REVISION HISTORY
1/ IO-Revision 0: Initial Version
Clock Input Considerations ...................................................... 22
Power Dissipation and Standby Mode .................................... 24
Digital Outputs ........................................................................... 25
Timing w........................................................................................ 25
Built-In Self-Test (BIST) and Output Test .................................. 26
Built-In Self-Test (BIST) w........................................................... 26
Output Test Modes F.................................................................... 26
Channel/Chip Synchronization V................................................... 27
DC and Quadrature Error Correction (QEC) ............................ 28
Serial Port Interface (SPI) .............................................................. 29
Configuration Using the SPI _.................................................... 29
Hardware Interface F.................................................................... 29
Configuration Without the SP1 w............................................... 30
SPI Accessible Features Q............................................................. 30
Memory Map _................................................................................. 31
Reading the Memory Map Register Table ............................... 31
Open Locations .......................................................................... 31
Default Values _............................................................................ 31
Memory Map Register Table B.................................................... 32
Memory Map Register Descriptions ........................................ 34
Applications Information T............................................................. 36
Design Guidelines B..................................................................... 36
Outline Dimensions W...................................................................... 37
Ordering Guide .......................................................................... 37
Rev. 0 I Page 2 of 40
ADQZBQ
GENERAL DESCRIPTION
The AD9269 is a monolithic, dual-channel, 1.8 V supply, 16-bit,
20/40/ 65/ 80 MSPS analog-to-digital converter (ADC). It features
a high performance sample-and-hold circuit and on-chip voltage
reference.
The product uses multistage differential pipeline architecture with
output error correction logic to provide I6-bit accuracy at 80 MSPS
data rates and to guarantee no missing codes over the full operating
temperature range.
The AD9269 incorporates an optional integrated dc correction and
quadrature error correction block (QEC) that corrects for dc
offset, gain, and phase mismatch between the two channels.
This functional block can be very beneficial to complex signal
processing applications such as direct conversion receivers.
The ADC also contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom
user-defined test patterns entered via the serial port interface (SP1).
A differential clock input controls all internal conversion cycles.
An optional duty cycle stabilizer (DCS) compensates for wide
variations in the clock duty cycle while maintaining excellent
overall ADC performance.
The digital output data is presented in offset binary, gray code,
or twos complement format. A data output clock (DCO) is pro-
vided for each ADC channel to ensure proper latch timing with
receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported,
and output data can be multiplexed onto a single output bus.
The AD9269 is available in a 64-lead RoHS-compliant LFCSP
and is specified over the industrial temperature range (-40''C to
+85°C).
Rev. 0 l Page 3 of 40
AD9269
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = -1.0 dBFS, DCS disabled,
unless otherwise noted.
Table 1.
AD9269-20/AD9269-40 AD9269-65 AD9269-80
Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full 16 16 16 Bits
ACCURACY
No Missing Codes Full Guaranteed Guaranteed Guaranteed
Offset Error Full 10.05 10.40 10.05 10.50 10.05 10.50 % FSR
Gain Error1 Full -2.0 -2.0 -2.0 % FSR
Differential Full -0.9/+1.2 -0.9/+1.4 -0.9/+1.65 LSB
Nonlinearity
(DNL)2
25°C -0.5/+0.6 -0.5/+I .1 -0.5/+1 .1 LSB
Integral Nonlinearity Full 15.50 16.50 16.50 LSB
(INL)2
25°C 12.0 12.2 13.3 LSB
MATCHING
CHARACTERISTICS
Offset Error 25°C 10.0 10.50 10.0 10.55 10.0 10.65 % FSR
Gain Error1 25°C 10.2 10.2 10.2 % FSR
TEMPERATURE DRIFT
Offset Error Full 12 12 12 ppm/°C
INTERNAL VOLTAGE
REFERENCE
Output Voltage Full 0.981 0.993 1.005 0.981 0.993 1.005 0.981 0.993 1.005 V
(1 V Mode)
Load Regulation Full 2 2 2 mV
Error at 1.0 mA
INPUT-REFERRED NOISE
VREF = 1.0 v 25°C 2.8 2.8 2.8 LSB
ANALOG INPUT
Input Span, Full 2 2 2 V p-p
VREF = 1.0 V
Input Capacitance3 Full 6.5 6.5 6.5 pF
Input Common- Full 0.9 0.9 0.9 V
Mode Voltage
Input Common- Full 0.5 1.3 0.5 1.3 0.5 1.3 V
Mode Range
REFERENCE INPUT Full 7.5 7.5 7.5 kn
RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
DRVDD Full 1.7 3.6 1.7 3.6 1.7 3.6 V
Supply Current
IAVDD2 Full 50.0/69.3 52.5/72.6 96.6 101.2 113 119 mA
IDRVDD2 (1.8 V) Full 3.9/6.4 9.6 11.8 mA
IDRVDD2 (3.3 V) Full 7.4/12.4 18.7 23 mA
Rev. 0 I Page 4 of 40
