AD9260AS ,High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word RateSPECIFICATIONS unless otherwise noted, R = 2 k)BIAS Parameter—Decimation Factor (N) AD9260 (8) AD9 ..
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AD9269 ,16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converterfeatures user-defined test patterns entered via the serial port interface (SPI). a high performance ..
AD9271BSVZ-50 , Octal LNA/VGA/AAF/ADC and Crosspoint Switch
AD9280ARS ,Complete 8-Bit, 32 MSPS, 95 mW CMOS A/D ConverterSPECIFICATIONS Span from 0.5 V to 2.5 V, External Reference, T to T unless otherwise noted)MIN MAXP ..
AD9281ARS ,Dual Channel 8-Bit Resolution CMOS ADCSPECIFICATIONS unless otherwise noted)Parameter Symbol Min Typ Max Units ConditionRESOLUTION 8 Bits ..
ADS7825UB ,4 Channel/ 16-Bit Sampling CMOS A/D ConverterADS7825ADS7825®ADS7825www.burr-brown.com/databook/ADS7825.html4 Channel, 16-Bit Sampling CMOS A/D C ..
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ADS7826IDRBR ,5.25V-2.7V, 10 bit, 200KSPS, Synchronous Serial ADCSLAS388JUNE 2003These devices have limited built-in ESD protection. The leads should be shorted to ..
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ADS7827IDRBR ,5.25V-2.7V, 8 bit, 250KSPS, Synchronous Serial ADCSLAS388JUNE 2003These devices have limited built-in ESD protection. The leads should be shorted to ..
AD9260AS
High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate
REV.B
High-Speed Oversampling CMOS
ADC with 16-Bit Resolution
at a 2.5 MHz Output Word Rate
FUNCTIONAL BLOCK DIAGRAMFEATURES
Monolithic 16-Bit, Oversampled A/D Converter
8� Oversampling Mode, 20 MSPS Clock
2.5 MHz Output Word Rate
1.01 MHz Signal Passband w/0.004 dB Ripple
Signal-to-Noise Ratio:88.5 dB
Total Harmonic Distortion:–96 dB
Spurious Free Dynamic Range:100 dB
Input Referred Noise: 0.6 LSB
Selectable Oversampling Ratio:1�, 2�, 4�, 8�
Selectable Power Dissipation:150 mW to 585 mW
85 dB Stopband Attenuation
0.004 dB Passband Ripple
Linear Phase
Single +5 V Analog Supply, +5 V/+3 V Digital Supply
Synchronize Capability for Parallel ADC Interface
Twos-Complement Output Data
44-Lead MQFP
PRODUCT DESCRIPTIONThe AD9260 is a 16-bit, high-speed oversampled analog-to-
digital converter (ADC) that offers exceptional dynamic range
over a wide bandwidth. The AD9260 is manufactured on an
advanced CMOS process. High dynamic range is achieved with
an oversampling ratio of 8× through the use of a proprietary
technique that combines the advantages of sigma-delta and
pipeline converter technologies.
The AD9260 is a switched-capacitor ADC with a nominal full-
scale input range of 4 V. It offers a differential input with 60 dB
of common-mode rejection of common-mode signals. The sig-
nal range of each differential input is ±1 V centered on a 2.0 V
common-mode level.
The on-chip decimation filter is configured for maximum per-
formance and flexibility. A series of three half-band FIR filter
stages provide 8× decimation filtering with 85 dB of stopband
attenuation and 0.004 dB of passband ripple. An onboard digi-
tal multiplexer allows the user to access data from the various
stages of the decimation filter.
The on-chip programmable reference and reference buffer am-
plifier are configured for maximum accuracy and flexibility. An
external reference can also be chosen to suit the user’s specific
dc accuracy and drift requirements.
The AD9260 operates on a single +5 V supply, typically con-
suming 585 mW of power. A power scaling circuit is provided
allowing the AD9260 to operate at power consumption levels as
low as 150 mW at reduced clock and data rates. The AD9260 is
available in a 44-lead MQFP package and is specified to operate
over the industrial temperature range.
PRODUCT HIGHLIGHTSThe AD9260 is fabricated on a very cost effective CMOS
process. High-speed, precision mixed-signal analog circuits are
combined with high-density digital filter circuits.
The AD9260 offers a complete single-chip 16-bit sampling
ADC with a 2.5 MHz output data rate in a 44-lead MQFP.
Selectable Internal Decimation Filtering—The AD9260provides a high-performance decimation filter with 0.004 dB
passband ripple and 85 dB of stopband attenuation. The filter
is configurable with options for 1×, 2×, 4×, and 8× decimation.
Power Scaling—The AD9260 consumes a low 585 mW of powerat 16-bit resolution and 2.5 MHz output data rate. Its power
can be scaled down to as low as 150 mW at reduced clock rates.
Single Supply— Both of the analog and digital portions of theAD9260 can operate off of a single +5 V supply simplifying
system power supply design. The digital logic will also accom-
modate a single +3 V supply for reduced power.
AVDDAVSSRESET/
SYNC
DRVDD
DRVSSDVSSDVDD
AVDDAVSSAVDDAVSS
OTR
BIT1–BIT16
DAV
READMODECLKBIAS ADJUST
REFCOM
SENSE
VREF
COMMON
MODE
REF
BOTTOM
REF TOP
VINB
VINA
AD9260–SPECIFICATIONS
CLOCK INPUT FREQUENCY RANGESpecifications subject to change without notice
DC SPECIFICATIONS
(AVDD = +5 V, DVDD = +3 V, DRVDD = +3 V, fCLOCK = 20 MSPS, VREF = +2.5 V, Input CML = 2.0 V TMIN to TMAX
unless otherwise noted, RBIAS = 2 k�)
AD9260NOTESVINA and VINB Connect to DUT CML.Including Internal 2.5 V reference.Excluding Internal 2.5 V reference.Load regulation with 1 mA load Current (in addition to that required by AD9260).
Specifications subject to change without notice.
AC SPECIFICATIONS
(AVDD = +5 V, DVDD = +3 V, DRVDD = +3 V, fCLOCK = 20 MSPS, VREF = +2.5 V, Input CML = 2.0 V TMIN to TMAX
unless otherwise noted, RBIAS = 2 k�)
AD9260–SPECIFICATIONS
AC SPECIFICATIONS (Continued)Specifications subject to change without notice.
AD9260
DIGITAL FILTER CHARACTERISTICSNOTESTo determine “overall” Absolute Group Delay and/or Settling Time inclusive of delay from the sigma-delta modulator, add Absolute Group Delay and/or Settling
Time pertaining to specific decimation mode to the Absolute Group Delay specified in 1× decimation.
Specifications subject to change without notice.
Figure 1a.8× FIR Filter Frequency Response
Figure 2a.4× FIR Filter Frequency Response
Figure 3a.2× FIR Filter Frequency Response
Figure 1b.8× FIR Filter Impulse Response
CLOCK PERIODS – RELATIVE TO CLK
NORMALIZED OUTPUT RESPONSE
1.01001102030405060708090Figure 2b.4× FIR Filter Impulse Response
Figure 3b.2× FIR Filter Impulse Response
AD9260–Digital Filter Characteristics
Table I.Integer Filter Coefficients for First Stage Decimation
Filter (23-Tap Halfband FIR Filter)H(2)
H(3)
H(4)
H(5)
H(6)
H(7)
H(8)
H(9)
H(10)
H(11)
Table II.Integer Filter Coefficients for Second Stage Decima-
tion Filter (43-Tap Halfband FIR Filter)H(4)
H(5)
H(6)
H(7)
H(8)
H(9)
H(10)
H(11)
H(12)
H(13)
H(14)
H(15)
H(16)
H(17)
H(18)
H(19)
H(20)
H(21)
NOTE:The composite filter undecimated coefficients (i.e.,
impulse response) in the 4× decimation mode can be determined
by convolving the first stage filter taps with a “zero stuffed”
version of the second stage filter taps (i.e., insert one zero be-
tween samples). Similarly, the composite filter coefficients in the
8× decimation mode can be determined by convolving the taps
of the composite 4× decimation mode (as previously deter-
mined) with a “zero stuffed” version of the third stage filter taps
(i.e., insert three zeros between samples).
Table III.Integer Filter Coefficients for Third Stage Decima-
tion Filter (107-Tap Halfband FIR Filter)
AD9260–SPECIFICATIONS
DIGITAL SPECIFICATIONSNOTESSince CLK is referenced to AVDD, +5 V logic input levels only apply.The AD9260 is not guaranteed to meet VOL = 0.4 V max for standard TTL load of IOL = 1.6 mA.
Specifications subject to change without notice.
Figure 4a.Timing Diagram
Figure 4b.RESET Timing Diagram
(AVDD = +5 V, DVDD = +5 V, TMIN to TMAX unless otherwise noted)
AD9260
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9260 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE*S = Metric Quad Flatpack.
THERMAL CHARACTERISTICSThermal Resistance
44-Lead MQFP
θJA = 53.2°C/W
θJC = 19°C/W
ABSOLUTE MAXIMUM RATINGS**Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
SWITCHING SPECIFICATIONSSpecifications subject to change without notice.
(AVDD = +5 V, DVDD = +5 V, CL = 20 pF, TMIN to TMAX unless otherwise noted)
AD9260
DEFINITIONS OF SPECIFICATION
INTEGRAL NONLINEARITY (INL)INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as “negative full scale” occurs 1/2 LSB before
the first code transition. “Positive full scale” is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16384
codes, respectively, must be present over all operating ranges.
NOTE: Conventional INL and DNL measurements don’t really
apply to Σ∆ converters: the DNL looks continually better if
longer data records are taken. For the AD9260, INL and DNL
numbers are given as representative.
ZERO ERRORThe major carry transition should occur for an analog value
1/2 LSB below VINA = VINB. Zero error is defined as the
deviation of the actual transition from that point.
GAIN ERRORThe first code transition should occur at an analog value
1/2LSB above negative full scale. The last transition should
occur at an analog value 1 1/2 LSB below the nominal full scale.
Gain error is the deviation of the actual difference between first
and last code transitions and the ideal difference between first
and last code transitions.
TEMPERATURE DRIFTThe temperature drift for zero error and gain error specifies the
maximum change from the initial (+25°C) value to the value at
TMIN or TMAX.
POWER SUPPLY REJECTIONThe specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value with
the supply at its maximum limit.
APERTURE JITTERAperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIOS/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
The value for S/N+D is expressed in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N,
the effective number of bits.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
TOTAL HARMONIC DISTORTION (THD)THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and
is expressed as a percentage or in decibels.
SIGNAL-TO-NOISE RATIO (SNR)SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
TWO-TONE SFDRThe ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).
PIN CONFIGURATION
REFCOM
VREF
SENSE
RESET
AVSS
AVDD
DVSS
AVSS
DVDD
AVDD
DRVSS
DRVDD
CLK
READ
(LSB) BIT16
BIT15
BIT14
DAV
OTR
BIT1 (MSB)
BIT2
BIT13
BIT12
AVDDNC
VINB
VINANCCML
AVSS
BIT8
CAPT
CAPB
BIAS
BIT11
MODE
BIT10
BIT9BIT7
BIT6
BIT5BIT4BIT3
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS40, 43
AD9260
–Typical Performance CharacteristicsFigure 5.Spectral Plot of the AD9260 at 100 kHz Input,
20 MHz Clock, 8× OSR (2.5 MHz Output Data Rate)
Figure 6.Spectral Plot of the AD9260 at 100 kHz Input,
20 MHz Clock, 4× OSR (5 MHz Output Data Rate)
Figure 7.Spectral Plot of the AD9260 at 100 kHz Input,
Figure 8.Spectral Plot of the AD9260 at 100 kHz Input,
20 MHz Clock, Undecimated (20 MHz Output Data Rate)
Figure 9.Dual Tone SFDR vs. Input Frequency (F1 = F2,
(F1 – F2, Span = 10% Center Frequency, Mode = 8×)
Figure 10.Two-Tone Spectral Performance of the
(AVDD = DVDD = DRVDD = +5.0 V, 4 V Input Span, Differential DC Coupled Input with CML = 2.0 V, fCLOCK = 20 MSPS, Full Bias)
Typical AC Characterization Curves vs. Decimation Mode
(AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, AIN = 0.5 dBFS Full Bias)Figure 11.SINAD vs. Input Frequency (fCLOCK = 20 MSPS)1
Figure 12.THD vs. Input Frequency (fCLOCK = 20 MSPS)
Figure 14.SINAD vs. Input Frequency (fCLOCK = 10 MSPS)1
Figure 15.THD vs. Input Frequency (fCLOCK = 10 MSPS)
AD9260
Typical AC Characterization Curves for 8� Mode
(AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, Full Bias)Figure 17.SINAD vs. Input Frequency (fCLOCK = 20 MSPS)1
Figure 18.THD vs. Input Frequency (fCLOCK = 20 MSPS)
Figure 20.SINAD vs. Input Frequency (fCLOCK = 10 MSPS)1
Figure 21.THD vs. Input Frequency (fCLOCK = 10 MSPS)
Typical AC Characterization Curves for 4� Mode
(AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, Full Bias)Figure 23.SINAD vs. Input Frequency (fCLOCK = 20 MSPS)
Figure 24.THD vs. Input Frequency (fCLOCK = 20 MSPS)
Figure 26.SINAD vs. Input Frequency (fCLOCK = 10 MSPS)
Figure 27.THD vs. Input Frequency (fCLOCK = 10 MSPS)
AD9260
Typical AC Characterization Curves for 2� Mode
(AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, Full Bias)Figure 29.SINAD vs. Input Frequency (fCLOCK = 20 MSPS)
Figure 30.THD vs. Input Frequency (fCLOCK = 20 MSPS)
Figure 31.SFDR vs. Input Frequency (fCLOCK = 20 MSPS)
Figure 32.SINAD vs. Input Frequency (fCLOCK = 10 MSPS)
Figure 33.THD vs. Input Frequency (fCLOCK = 10 MSPS)
Figure 34.SFDR vs. Input Frequency (fCLOCK = 10 MSPS)
Typical AC Characterization Curves for 1� Mode
(AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, Full Bias)Figure 35.SINAD vs. Input Frequency (fCLOCK = 20 MSPS)
Figure 36.THD vs. Input Frequency (fCLOCK = 20 MSPS)
Figure 38.SINAD vs. Input Frequency (fCLOCK = 10 MSPS)
Figure 39.THD vs. Input Frequency (fCLOCK = 10 MSPS)
AD9260
Typical AC Characterization Curves
(AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, AIN = –0.5 dBFS, Differential DC Coupled Input with CML = 2 V)Figure 41.SFDR vs. Clock Rate (fIN = 100 kHz in 8× Mode)
Figure 42.SFDR vs. Clock Rate (fIN = 500 kHz in 4× Mode)
Figure 44. THD vs. Common-Mode Input Level (CML)
Figure 45.CMR vs. Input Frequency (VCML = 2 V p-p, 1×
Mode)
