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AD9248BST-40-AD9248BST-65
14-Bit/ 20/40/65 MSPS Dual A/ D Converter
14-Bit, 20/40/65 MSPS
FEATURES
Integrated Dual 14-Bit A-to-D Converters
Single 3 V Supply Operation (2.7 V to 3.6 V)
SNR = 73 dBc (to Nyquist, AD9248-65)
SFDR = 83 dBc (to Nyquist, AD9248-65)
Low Power: 600 mW at 65 MSPS
Differential Input with 500 MHz 3 dB Bandwidth
Exceptional Cross Talk Immunity > 85dB
Flexible Analog Input: 1 V p-p to 2 V p-p Range
Offset Binary or Twos Complement Data Format
Clock Duty Cycle Stabilizer
APPLICATIONS
Ultrasound Equipment
IF Sampling in Communications Receivers:
IS-95, CDMA One, IMT-2000
Battery-Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
GENERAL DESCRIPTION The AD9248 is a dual, 3 V, 14-bit, 20/40/65 MSPS analog-to-
digital converter. It features dual high performance sample-and hold amplifiers and an integrated voltage reference. The
AD9248 uses a multistage differential pipelined architecture
with output error correction logic to provide 14-bit accuracy
and guarantee no missing codes over the full operating
temperature range at up to 65 MSPS data rates. The wide
bandwidth, differential SHA allows for a variety of user
selectable input ranges and offsets including single-ended
applications. It is suitable for various applications including
multiplexed systems that switch full-scale voltage levels in
successive channels and for sampling inputs at frequencies well beyond the Nyquist rate.
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available on the AD9248-65 and can compensate for wide variations in the
clock duty cycle, allowing the converters to maintain excellent
performance. The digital output data is presented in either
straight binary or twos complement format. Out-of-range
signals indicate an overflow condition, which can be used with
the most significant bit to determine low or high overflow.
Fabricated on an advanced CMOS process, the AD9248 is
available in a space saving 64-lead LQFP and is specified over the industrial temperature range (–40C to +85C). D13A-D0A
AGND
VIN- _A
CLK_A
VIN+_A
DCSSENSE
REFT_A
AVDDVIN-_BVIN+_B
D13B-D0B
MUX_SELECT
CLK_B
AGND
DRGND
SHARED_REF
PWDN_A
DFS
REFB_A
REFT_B
REFB_B
PWDN_B
OTR_B
OEB_B
OEB_A
OTR_A
VREF
DRVDD
Figure 1. Functional Block Diagram
PRODUCT HIGHLIGHTS 1. Pin compatible with AD9238, 12-bit 20/40/65MSPS
ADC.
2. Speed grade options of 20 MSPS, 40 MSPS, and 65
MSPS allow flexibility between power, cost, and performance to suit an application.
3. Low power consumption:
AD9248-65: 65 MSPS = 600 mW. AD9248-40: 40 MSPS = 330 mW.
AD9248-20: 20 MSPS = 180 mW.
4. The patented SHA input maintains excellent
performance for input frequencies up to 100 MHz and can be configured for single-ended or differential
operation.
5. Typical channel isolation of 85 dB @ fIN = 10 MHz.
6. The clock duty cycle stabilizer (AD9248-65 only)
maintains performance over a wide range of clock duty cycles.
7. The OTR output bits indicate when either input signal
is beyond the selected input range.
8. Multiplexed data output option enables single-port
operation from either data port A or data port B.
TABLE OF CONTENTS General Description..............................................................1
Product Highlights................................................................1
DC Specifications (Continued).............................................5
Switching Specifications.......................................................6
AC Specifications.................................................................7
Absolute Maximum Ratings.....................................................9
ESD Caution.........................................................................9
Terminolgy..........................................................................12
Typical Performance CharacteristiC.......................................14
Equivalent Circuits.................................................................15
Theory of Operation............................................................15
Analog Input.......................................................................15
Clock Input and Considerations..........................................17
Power Dissipation and Standby Mode................................17
Digital Outputs....................................................................17
Timing................................................................................18
Data Format........................................................................18
Voltage Reference...............................................................19
Evaluation Board Diagrams....................................................21
Outline Dimensions.................................................22
REVISION HISTORY PrA: Initial Version
PrB: Included Spec tables, pin out configuration and assignments
PrC: Updated Ordering guide to designate Pb Free part numbers
PrD: Corrected Ordering guide
PrE: Corrected package pin-out error (pins10,11,14,15), corrected product highlights typo (p1)
AD9248–SPECIFICATIONS
DC SPECIFICATIONS
Table 1. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = -0.5 dBFS Differential Input, 1.0 V
Internal Reference, TMIN to TMAX, unless otherwise noted.) Typ ±0.5 ±0.5 ±0.5 ±0.7 ±0.7 ±0.7 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±1.4 ±1.4 ±1.4 ±1.4 ±1.4 ±1.4 ±10 ±10 ±10 ±12 ±12 ±12 ±5 ±5 ±5 0.8 0.8 0.8 ±2.5 ±2.5 ±2.5 0.1 0.1 0.1 1.8 1.8 1.8 1.2 1.2 1.2 1 1 1 2 2 2 7 7 7 7 7 7 3.0 3.0 3.0 3.0 3.0 3.0 60 110 200 4 10 14 ±0.01 ±0.01 ±0.01 180 330 600 190 360 640
Gain error and gain temperature coefficient are based on the A/D converter only (with a fixed 1.0 V external reference). 2 Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit. Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure for the equivalent analog input structure. 4 Measured with dc input at maximum clock rate. 5 Standby power is measured with the CLK_A and CLK_B pins inactive (i.e., set to AVDD or AGND). Specifications subject to change without notice.
DC SPECIFICATIONS (CONTINUED)
Table 2. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = -0.5 dBFS Differential Input, 1.0 V Internal Reference, TMIN to TMAX, unless otherwise noted.) 2 2 2
Output Voltage Levels measured with 5 pF load on each output.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Table 3. Switching Specifications 3.5 3.5 3.5 7 7 7 1.0 1.0 1.0 0.5 0.5 0.5 2.5 2.5 2.5
The AD9248-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see TPC 20). 2 Output delay is measured from CLOCK 50% transition to DATA 50% transition, with a 5 pF load on each output. 3 Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
Specifications subject to change without notice.
AC SPECIFICATIONS Table 4. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = –0.5 dBFS Differential Input, 1.0 V
Internal Reference, TMIN to TMAX, unless otherwise noted.) Min Typ 73 73 73 73 73 72 72 72 72 70 70 70 72.8 72.8 72.6 72 72 71.9 71.6 71.5 71 69.6 69.5 69.4 11.8 11.8 11.8 11.7 11.7 11.7 11.7 11.6 11.5 11.4 11.4 11.3 -83.0 -83.0 -83.0 -81.0 -83.0 -81.0 -83.0 -78.0 -80.0 -77.0 -79.0 -74.0 -84.0 -85.0 -80.0
86.0 86.0 86.0 dBc 84.0 86.0 85.0 86.0 83.0 83.0 75.0 Specifications subject to change without notice.
Figure 2. Timing Diagram
ABSOLUTE MAXIMUM RATINGS
Table 5. AD9248 Absolute Maximum Ratings1
Parameter Unit
Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedances (64-lead LQFP); JA = 54°C/W. These measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7.
EXPLANATION OF TEST LEVELS 100% production tested.
II 100% production tested at 25°C and sample tested at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing. Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
D4_A
D3_A
D2_A
D1_A
D0_A
DRGND
OTR_B
D11_B
D10_B
D9_B
D8_B
D7_BD6_B
AGND
AVDD
REFT_A
REFB_A
VREF
SENSE
REFB_B
AGND
VIN–_B
VIN+_B
VIN+_A
VIN–_A
AVDD
REFT_B
CLK_A
OEB_A
D9_AD8_A
D7_A
D6_A
D5_A
CLK_B
DFS
PDWN_B
OEB_B
D0_BD1_BD2_B
DRGND
D3_BD4_BD5_B
AGND
AGND
AVDD
DRVDD
DRVDD
AVDDPDWN_AOTR_ADRVDD
D12_A
D13_A (MSB)
D13_B (MSB)
D12_B
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Table 7. ORDERING GUIDE
TERMINOLGY
Aperture Delay
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
Aperture Jitter
The variation in aperture delay for successive samples, which is manifested as noise on the input to the A/D converter.
Integral Nonlinearity (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs 1/2 LSB before the first
code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured
from the middle of each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 8192 codes must be present over all operating ranges.
Offset Error
The major carry transition should occur for an analog value 1/2
LSB below VIN+ = VIN-. Offset error is defined as the deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2
LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale.
Gain error is the deviation of the actual difference between first
and last code transitions and the ideal difference between first
and last code transitions.
Temperature Drift
The temperature drift for zero error and gain error specifies the
maximum change from the initial (25°C) value to the value at TMIN or TMAX.
Power Supply Rejection
The specification shows the maximum change in full scale
from the value with the supply at the minimum limit to the value with the supply at its maximum limit.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal, expressed as a
Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio
The ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels relative to the peak carrier
signal (dBc).
Effective Number of Bits (ENOB)
Using the following formula:
effective number of bits for a
device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD.
Signal-to-Noise Ratio (SNR)
The ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels relative to the peak carrier signal (dBc).
Spurious Free Dynamic Range (SFDR)
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
Nyquist Sampling
When the frequency components of the analog input are below
the Nyquist frequency (fCLOCK/2), this is often referred to as
Nyquist sampling.
IF Sampling
Due to the effects of aliasing, an ADC is not necessarily limited
to Nyquist sampling. Higher sampled frequencies will be aliased down into the first Nyquist zone (DC - fCLOCK/2) on the
output of the ADC. Care must be taken that the bandwidth of
the sampled signal does not overlap Nyquist zones and alias onto itself. Nyquist sampling performance is limited by the
bandwidth of the input SHA and clock jitter (jitter adds more noise at higher input frequencies).
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component may or may not be an IMD product.
Out-of-Range Recovery Time
Out-of-range recovery time is the time it takes for the A/D
converter to reacquire the analog input after a transient from
10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive 026761ENOB..
