AD9245BCPZ-80 ,14-Bit, 80 MSPS, 3 V A/D Converterapplications in communications, imaging, and to 14 bits and 20 MSPS to 80 MSPS. medical ultrasound. ..
AD9246BCPZ-105 , 14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter
AD9248BCPZ-20 ,Dual 14-Bit, 20/40/65 MSPS, 3 V ADCFEATURES OTR_A14Integrated Dual 14-Bit A-to-D Converters VIN+_ASHA ADC D13 -DA 0AVIN- _ASingle 3 V ..
AD9248BCPZ-40 ,Dual 14-Bit, 20/40/65 MSPS, 3 V ADCfeatures dual high performance sample-and performance to suit an application. hold amplifiers and a ..
AD9248BCPZ-40 ,Dual 14-Bit, 20/40/65 MSPS, 3 V ADCSpecifications .. 7 Data Format 18 Absolute Maximum Ratings ........9 Voltage Reference 19 ESD Cau ..
AD9248BCPZ-65 ,Dual 14-Bit, 20/40/65 MSPS, 3 V ADCfeatures dual high performance sample-and performance to suit an application. hold amplifiers and a ..
ADS7822U/2K5G4 ,12-Bit, 200kSPS Micro Power Sampling Analog-To-Digital Converter 8-SOIC -40 to 85.(2) Performance grade information is marked on the reel.(1)ABSOLUTE
ADS7822UB ,12-Bit High Speed 2.7V Micro Power Sampling Analog-To-Digital ConverterMAXIMUM RATINGSover operating free-air temperature range (unless otherwise noted)ADS7822 UNITV +6 V ..
ADS7822UC ,12-Bit High Speed 2.7V Micro Power Sampling Analog-To-Digital ConverterADS7822ADS7822 ADS7822 SBAS062C–JANUARY 1996–REVISED AUGUST 2007 ..
ADS7822UC ,12-Bit High Speed 2.7V Micro Power Sampling Analog-To-Digital ConverterSBAS062C–JANUARY 1996–REVISED AUGUST 2007
ADS7823E/250 ,12-Bit Low Power,I2C Serial, Sampling Analog-To-Digital ConverterELECTRICAL CHARACTERISTICS: +5VAt T = –40°C to +85°C, +V = +5.0V, V = +5.0V, SCL Clock Frequency = ..
ADS7823E/250G4 ,12-Bit Low Power,I2C Serial, Sampling Analog-To-Digital Converter 8-VSSOP -40 to 85ELECTRICAL CHARACTERISTICS: +2.7V (Cont.)At T = –40°C to +85°C, +V = +2.7V, V = +2.5V, SCL Clock Fr ..
AD9245BCPZ-80
14-Bit, 80 MSPS, 3 V A/D Converter
14-Bit, 80 MSPS, 3 V A/D ConverterFEATURES
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 72.7 dBc to Nyquist
SFDR = 87.6 dBc to Nyquist
Low power: 366 mW
Differential input with 500 MHz bandwidth
On-chip reference and sample-and-hold
DNL = ± 0.5 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
APPLICATIONS
High end medical imaging equipment
IF sampling in communications receivers:
WCDMA, CDMA-One, CDMA-2000, TDS-CDMA
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
Power sensitive military applications
GENERAL DESCRIPTION The AD9245 is a monolithic, single 3 V supply, 14-bit, 80 MSPS
analog-to-digital converter featuring a high performance
sample-and-hold amplifier (SHA) and voltage reference. The
AD9245 uses a multistage differential pipelined architecture
with output error correction logic to provide 14-bit accuracy at
80 MSPS and guarantee no missing codes over the full operat-
ing temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and common modes, including
single-ended applications. It is suitable for multiplexed systems
that switch full-scale voltage levels in successive channels, and
for sampling single-channel inputs at frequencies well beyond
the Nyquist rate. Combined with power and cost savings over
previously available analog-to-digital converters, the AD9245 is
suitable for applications in communications, imaging, and
medical ultrasound.
A single-ended clock input is used to control all internal con-
version cycles. A duty cycle stabilizer (DCS) compensates for
wide variations in the clock duty cycle while maintaining
FUNCTIONAL BLOCK DIAGRAM 03583-B-001
DRVDDAVDD
AGND
CLKPDWNMODEDGND
OTR
VIN+
VIN–
REFT
REFB
VREF
SENSE
D13 (MSB)
D0 (LSB)Figure 1. Functional Block Diagram
excellent overall ADC performance. The digital output data is
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow. Fabricated on an advanced CMOS process, the
AD9245 is available in a 32-lead LFCSP and is specified over
the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS 1. The AD9245 operates from a single 3 V power supply and
features a separate digital output driver supply to accommo-
date 2.5 V and 3.3 V logic families.
2. Operating at 80 MSPS, the AD9245 consumes a low 366 mW.
3. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz, and can be configured for
single-ended or differential operation.
4. The AD9245 is pin compatible with the AD9215, AD9235,
and AD9236. This allows a simplified migration from 10 bits
to 14 bits and 20 MSPS to 80 MSPS.
5. The clock DCS maintains overall ADC performance over a
wide range of clock pulsewidths.
6. The OTR output bit indicates when the signal is beyond the
selected input range.
Rev.B
TABLE OF CONTENTS AD9245–DC Specifications............................................................3
AD9245–AC Specifications.............................................................4
AD9245–Digital Specifications.......................................................5
AD9245–Switching Specifications.................................................6
Explanation of Test Levels...........................................................6
Absolute Maximum Ratings............................................................7
Thermal Resistance......................................................................7
ESD Caution..................................................................................7
Definitions of Specifications...........................................................8
Pin Configuration and Functional Descriptions..........................9
Equivalent Circuits.........................................................................10
Typical Performance Characteristics...........................................11
Theory of Operation......................................................................14
Analog Input and Reference Overview...................................14
Clock Input Considerations......................................................15
Jitter Considerations..................................................................16
Power Dissipation and Standby Mode....................................16
Digital Outputs...........................................................................16
Timing.........................................................................................17
Voltage Reference.......................................................................17
Internal Reference Connection................................................17
External Reference Operation..................................................18
Operational Mode Selection.....................................................18
Evaluation Board........................................................................18
Outline Dimensions.......................................................................25
Ordering Guide..........................................................................25
REVISION HISTORY Revision B
10/03—Data Sheet Changed from REV. A to REV. B
Changes to Figure 33 .....................................................................17
5/03—Data Sheet Changed from REV. 0 to REV. A
Changes to Figure 30 .................................................................... 15
Changes to Figure 37 .....................................................................19
Changes to Figure 38..................................................................... 20
Changes to Figure 39......................................................................21
Changes to Table 10 .......................................................................24
Changes to the ORDERING GUIDE...........................................25
AD9245–DC SPECIFICATIONS
Table 1. AVDD = 3 V, DRVDD = 2.5 V, Sample Rate = 80 MSPS, 2 V p-p Differential Input, 1.0 V External Reference, unless
otherwise noted With a 1.0 V internal reference.
2 Measured at the maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
AD9245–AC SPECIFICATIONS
Table 2. AVDD = 3 V, DRVDD = 2.5 V, Sample Rate = 80 MSPS, 2 V p-p Differential Input, 1.0 V External Reference,
AIN = –0.5 dBFS, DCS Off, unless otherwise noted AD9245–DIGITAL SPECIFICATIONS
Table 3. AVDD = 3 V, DRVDD = 2.5 V, 1.0 V External Reference, unless otherwise noted Output voltage levels measured with 5 pF load on each output.
AD9245–SWITCHING SPECIFICATIONS
Table 4. AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted With duty cycle stabilizer (DCS) enabled.
2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. Wake-up time is dependant on the value of the decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
2.0ns MIN03583-B-002
ANALOG
INPUT
CLK
DATA
OUTN+1
N+2Figure 2. Timing Diagram
EXPLANATION OF TEST LEVELS
Test Level Definitions 100% production tested.
II 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing. Parameter is a typical value only.
VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
ABSOLUTE MAXIMUM RATINGS
Table 5. AD9245 Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE θJA is specified for the worst-case conditions on a 4-layer board
in still air, in accordance with EIA/JESD51-1.
Table 6. Thermal Resistance Airflow increases heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA. It is recommended that the exposed paddle be
soldered to the ground plane for the LFCSP package. There is an
increased reliability of the solder joints, and maximum thermal
capability of the package is achieved with the exposed paddle
soldered to the customer board.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth (Full Power Bandwidth)—The analog input frequency at which the spectral power of the fundamental
frequency (as determined by the FFT analysis) is reduced by 3 dB.
Aperture Delay (tA)—The delay between the 50% point of the rising edge of the clock and the instant at which the analog
input is sampled.
Aperture Uncertainty (Jitter, tJ)—The sample-to-sample varia-tion in aperture delay.
Integral Nonlinearity (INL)—The deviation of each individual code from a line drawn from negative full scale through positive
full scale. The point used as negative full scale occurs ½ LSB
before the first code transition. Positive full scale is defined as a
level 1½ LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
Differential Nonlinearity (DNL, No Missing Codes)—An ideal ADC exhibits code transitions that are exactly 1 LSB apart.
DNL is the deviation from this ideal value. Guaranteed no miss-
ing codes to 14-bit resolution indicates that all 16384 codes
must be present over all operating ranges.
Offset Error—The major carry transition should occur for an analog value ½ LSB below VIN+ = VIN–. Offset error is
defined as the deviation of the actual transition from that point.
Gain Error—The first code transition should occur at an analog value ½ LSB above negative full scale. The last transition
should occur at an analog value 1½ LSB below the positive
full scale. Gain error is the deviation of the actual difference
between first and last code transitions and the ideal difference
between first and last code transitions.
Temperature Drift—The temperature drift for offset error and gain error specifies the maximum change from the initial
(25°C) value to the value at TMIN or TMAX.
Power Supply Rejection Ratio—The change in full scale from the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
Total Harmonic Distortion (THD)1—The ratio of the rms input signal amplitude to the rms value of the sum of the first
six harmonic components.
Signal-to-Noise and Distortion (SINAD)1—The ratio of the rms input signal amplitude to the rms value of the sum of all
other spectral components below the Nyquist frequency, includ-
ing harmonics but excluding dc.
Effective Number of Bits (ENOB)—The effective number of bits for a sine wave input at a given input frequency can be cal-
culated directly from its measured SINAD using the following
formula: ).6.1−=ENOB
Signal-to-Noise Ratio (SNR)1 —The ratio of the rms input signal amplitude to the rms value of the sum of all other spec-
tral components below the Nyquist frequency, excluding the
first six harmonics and dc.
Spurious-Free Dynamic Range (SFDR)1—The difference in dB between the rms input signal amplitude and the peak spurious
signal. The peak spurious component may or may not be a
harmonic.
Two-Tone SFDR1—The ratio of the rms value of either input tone to the rms value of the peak spurious component. The
peak spurious component may or may not be an IMD product.
Clock Pulsewidth and Duty Cycle—Pulsewidth high is the minimum amount of time that the clock pulse should be left in
the Logic 1 state to achieve rated performance. Pulsewidth low
is the minimum time the clock pulse should be left in the
Logic 0 state. At a given clock rate, these specifications define an
acceptable clock duty cycle.
Minimum Conversion Rate—The clock rate at which the SNR of the lowest analog signal frequency drops by no more than
3 dB below the guaranteed limit.
Maximum Conversion Rate—The clock rate at which para-metric testing is performed.
Output Propagation Delay (tPD)—The delay between the clock rising edge and the time when all bits are within valid logic
levels.
Out-of-Range Recovery Time—The time it takes for the ADC to reacquire the analog input after a transition from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.
AC specifications may be reported in dBc (degrades as signal levels are
lowered) or in dBFS (always related back to converter full scale).
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS 03583-B-022
DNC 1
CLK 2
DNC 3
PDWN 4
(LSB) D0 5
D1 6
D2 7
D3 8
24 VREF
23 SENSE
22 MODE
21 OTR
20 D13 (MSB)
19 D12
18 D11
17 D10
32 A
31 A
30 VIN
29 VIN
28 A
27 A
26 R
25 R
DGND 1
DRV
DD 1
AD9245CSP
TOP VIEW
(Not to Scale)Figure 3. 32-Lead LFCSP
Table 7. Pin Function Descriptions—32-Lead LFCSP (CP Package) EQUIVALENT CIRCUITS
AVDD
VIN+, VIN–03583-B-003
Figure 4. Equivalent Analog Input Circuit
03583-B-004
AVDD
MODEFigure 5. Equivalent MODE Input Circuit
D13-D0,
OTR
DRVDD03583-B-005
Figure 6. Equivalent Digital Output Circuit
03583-B-006
AVDD
CLK,
PDWNFigure 7. Equivalent Digital Input Circuit
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.0 V, DRVDD = 2.5 V, Sample Rate = 80 MSPS, DCS Disabled, TA = 25°C, 2 V p-p Differential Input, AIN = –0.5 dBFS,
VREF = 1.0 V External, unless otherwise noted
FREQUENCY (MHz)
AMP
ITUDE
(dBFS5101520253035
–11003583-B-032
Figure 8. Single Tone 8K FFT @ 2.5 MHz
FREQUENCY (MHz)
AMP
ITUDE
(dBFS5101520253035–120
–11003583-B-023
Figure 9. Single Tone 8K FFT @ 39 MHz
FREQUENCY (MHz)
AMP
ITUDE
(dBFS5101520253035–120
–11003583-B-024
INPUT AMPLITUDE (dBFS)
NR/S
DR (dBc
AND dBFS
10003583-B-033
Figure 11. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 2.5 MHz
INPUT AMPLITUDE (dBFS)
NR/S
DR (dBc
AND dBFS
10003583-B-034
Figure 12. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 39 MHz
SAMPLE RATE (MSPS)
NR/S
DR (dBc2040608050
10003583-B-025
FREQUENCY (MHz)
AMP
ITUDE
(dBFS5101520253035–120
–1003583-B-029
Figure 14. Two-Tone 8K FFT @ 30 MHz and 31 MHz
FREQUENCY (MHz)
AMP
ITUDE
(dBFS5101520253035–120
–1003583-B-030
Figure 15. Two-Tone 8K FFT @ 69 MHz and 70 MHz
CODE
INL (
SB)2048409661448192102401228814336–1.5
1638403583-B-026
Figure 16. Typical INL
INPUT AMPLITUDE (dBFS)
NR/S
DR (dBc
AND dBFS
10003583-B-031
Figure 17. Two-Tone SNR/SFDR vs. Input Amplitude @ 30 MHz and 31 MHz
INPUT AMPLITUDE (dBFS)
NR/S
DR (dBc
AND dBFS
10003583-B-027
Figure 18. Two-Tone SNR/SFDR vs. Input Amplitude @ 69 MHz and 70 MHz
CODE
DNL (LS2048409661448192102401228814336
1638403583-B-028
Figure 19. Typical DNL
INPUT FREQUENCY (MHz)
NR (dBc255075100
12503583-B-036
Figure 20. SNR vs. Input Frequency
DUTY CYCLE (%)
/SFD354045505560657003583-B-037
Figure 21. SNR/SFDR vs. Clock Duty Cycle
AMP
ITUDE
(dBFS
FREQUENCY (MHz)03583-B-059
Figure 22. 32K FFT WCDMA Carrier @ FIN = 96 MHz; Sample Rate = 76.8 MSPS
INPUT FREQUENCY (MHz)
DR (dBc255075100
12503583-B-038
Figure 23. SFDR vs. Input Frequency
AMP
ITUDE
(dBFS
FREQUENCY (MHz)03583-B-060
Figure 24. Two 32K FFT CDMA-2000 Carriers @
FIN = 46.08 MHz; Sample Rate = 61.44 MSPS
AMP
ITUDE
(dBFS
FREQUENCY (MHz)03583-B-061
Figure 25. Two 32K FFT WCDMA Carriers @
FIN = 76.8 MHz; Sample Rate = 61.44 MSPS
THEORY OF OPERATION The AD9245 architecture consists of a front-end sample and
hold amplifier (SHA) followed by a pipelined switched capaci-
tor ADC. The pipelined ADC is divided into three sections,
consisting of a 4-bit first stage followed by eight 1.5-bit stages
and a final 3-bit flash. Each stage provides sufficient overlap to
correct for flash errors in the preceding stages. The quantized
outputs from each stage are combined into a final 14-bit result
in the digital correction logic. The pipelined architecture per-
mits the first stage to operate on a new input sample, while the
remaining stages operate on preceding samples. Sampling
occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be ac-
coupled or dc-coupled in differential or single-ended modes.
The output-staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing adjustment
of the output voltage swing. During power-down, the output
buffers go into a high impedance state.
ANALOG INPUT AND REFERENCE OVERVIEW The analog input to the AD9245 is a differential switched-
capacitor SHA that has been designed for optimum perform-
ance while processing a differential input signal. The SHA input
can support a wide common-mode range (VCM) and maintain
excellent performance, as shown in Fi. An input
common-mode voltage of midsupply minimizes signal-
dependent errors and provides optimum performance.
gure 26
COMMON-MODE LEVEL (V)
NR/S
DR (dBc
3.003583-B-039
Referring to F, the clock signal alternately switches the
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC’s
input; therefore, the precise values are dependent upon the
application. In IF undersampling applications, any shunt
capacitors should be reduced or removed. In combination with
the driving source impedance, they would limit the input
bandwidth.
igure 27
Figure 27. Switched-Capacitor SHA Input
03583-B-012
VIN+
VIN–
CPAR
CPAR
5pF
5pFFor best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, that define the
span of the ADC core. The output common mode of the
reference buffer is set to midsupply, and the REFT and REFB
voltages and span are defined as follows: VREFREFBREFTSpan
VREFAVDDREFB
VREFAVDDREFT=−×===2
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage, and,
by definition, the input span is twice the value of the VREF voltage.
The internal voltage reference can be pin strapped to fixed
values of 0.5 V or 1.0 V, or adjusted within the same range as
