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AD9244BSTZ-40-AD9244BSTZ-65
14-Bit 40/65 MSPS IF Sampling Analog-To-Digital Converter
14-Bit, 40/65 MSPS A/D ConverterREV.A
FEATURES
14-Bit, 40/65 MSPS ADC
Low Power:
550 mW at 65 MSPS
300 mW at 40 MSPS
On-Chip Reference and Sample-and-Hold
750 MHz Analog Input Bandwidth
SNR > 73 dBc to Nyquist @ 65 MSPS
SFDR > 86 dBc to Nyquist @ 65 MSPS
Differential Nonlinearity Error = �0.7 LSB
Guaranteed No Missing Codes over Full Temperature Range
1 V to 2 V p-p Differential Full-Scale Analog Input Range
Single 5 V Analog Supply, 3.3 V/5 V Driver Supply
Out-of-Range Indicator
Straight Binary or Twos Complement Output Data
Clock Duty Cycle Stabilizer
Output Enable Function
48-Lead LQFP Package
APPLICATIONS
Communications Subsystems (Microcell, Picocell)
Medical and High End Imaging Equipment
Ultrasound Equipment
GENERAL DESCRIPTIONThe AD9244 is a monolithic, single 5 V supply, 14-bit,MSPS/65MSPS analog-to-digital converter with an on-chip,
high performance sample-and-hold amplifier and voltage reference.
The AD9244 uses a multistage differential pipelined architecture
with output error correction logic to provide 14-bit accuracy atMSPS/65MSPS data rates and guarantees no missing codes
over the full operating temperature range.
The AD9244 has an on-board, programmable voltage reference.
An external reference can also be used to suit the dc accuracy
and temperature drift requirements of the application.
A differential or single-ended clock input is used to control all
internal conversion cycles. The digital output data can be pre-
sented in straight binary or in twos complement format. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow.
Fabricated on an advanced CMOS process, the AD9244 is
available in a 48-lead low profile quad flatpack package (LQFP)
and is specified for operation over the industrial temperature
range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
Low Power—The AD9244, at 550 mW, consumes a frac-tion of the power of presently available ADCs in existing
high speed solutions.
IF Sampling—The AD9244 delivers outstanding perfor-mance at input frequencies beyond the first Nyquist zone.
Sampling at 65 MSPS with an input frequency of 100MHz,
the AD9244 delivers 71 dB SNR and 86 dB SFDR.
Pin Compatibility—The AD9244 offers a seamlessmigration from the 12-bit, 65 MSPS AD9226.
On-Board Sample-and-Hold (SHA)—The versatile SHAinput can be configured for either single-ended or differ-
ential inputs.
Out-of-Range (OTR)—The OTR output bit indicateswhen the input signal is beyond the AD9244’s input range.
Single Supply—The AD9244 uses a single 5 V powersupply, simplifying system power supply design. It also
features a separate digital output driver supply to accom-
modate 3.3V and 5V logic families.
FUNCTIONAL BLOCK DIAGRAM
AD9244–SPECIFICATIONS
DC SPECIFICATIONSANALOG INPUT
NOTESGain error is based on the ADC only (with a fixed 2.0 V external reference).Measured at maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.Includes internal voltage reference error.Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 2d for the equivalent analog input structure.Input bias current is due to the inputs looking like a resistor that is dependent on the clock rate.Measured with dc input at maximum clock rate.
Specifications subject to change without notice.
(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS (–65) or 40 MSPS (–40), Differential Clock Inputs, VREF = 2 V,
External Reference, Differential Analog Inputs, unless otherwise noted.)
AD9244WORST 2 or 3
AC SPECIFICATIONS
(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS (–65) or 40 MSPS (–40), Differential Clock Inputs, VREF = 2 V,
External Reference, AIN = –0.5 dBFS, Differential Analog Inputs, unless otherwise noted.)
AD9244
DIGITAL SPECIFICATIONS(AVDD = 5 V, DRVDD = 3 V, VREF = 2 V, External Reference, unless otherwise noted.)NOTESSee Clock section of Theory of Operation for more details.Output voltage levels measured with 5 pF load on each output.
Specifications subject to change without notice.
AC SPECIFICATIONS (continued)
AD9244DATA OUTPUT PARAMETERS
NOTESThe clock period may be extended to 2 µs with no degradation in specified performance at 25°C.With duty cycle stabilizer enabled.With duty cycle stabilizer disabled.Measured from clock 50% transition to data 50% transition with 5 pF load on each output.
Specifications subject to change without notice
(AVDD = 5 V, DRVDD = 3 V, unless otherwise noted.)SWITCHING SPECIFICATIONSFigure 1.Input Timing
